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Introduction
• What is Verilog HDL?
Verilog HDL is a Hardware Description
Language that can be used to model a
digital system at many levels of
abstraction:
–Algorithmic-level
–Gate-level
–Switch-level
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Where can we use Verilog HDL?
• Verilog is designed for circuit verification and
simulation, for timing analysis, for test
analysis (testability analysis and fault
grading) and for logic synthesis.
• For example, before you get to the structural
level of your design, you want to make sure
the logical paths of your design is faultless
and meets the spec.
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Basic Procedure of Using Verilogger
• Preparation – always create a new folder in C drive.
– c:/documents and settings
– your_login_name
– your_project_folder
• Start – all programs –synaptiCAD - Verilogger pro 6.5
• Editor – new HDL file – write your code – save as filename.v
in your project folder
• Project – add HDL files – choose the file you just saved
• Project – save HDL project – save it in the your project
folder too.
We will continue after we finishing the modeling section…..
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Basic Syntax of a Module
Module module_name (port_list);
Declarations:
input, output, wire, parameter…..
System Modeling:
describe the system in gate-level, data-flow, or
behavioral style…
endmodule
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Basic Module Construction
// Compute the logical AND and OR of
inputs A and B.
module AND_OR(andOut, orOut, A, B);
output andOut, orOut;
input A, B;
and TheAndGate (andOut, A, B);
or TheOrGate (orOut, A, B);
endmodule
AND_OR
andOut
orOut
A
B
TheAndGate
TheOrGate
AND_OR
andOut
orOut
A
B
TheAndGate
TheOrGate
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Gate-Level Modeling
Systems structure can be described using Build-in
gates or pre-built modules.
Basic syntax is :
gate-type #delay instance1_name(outputs.., inputs.. ),
:
:
instance6_name(outputs.., inputs.. );
pre-built module module_instance1(output…,inputs..);
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Data-flow Modeling
• The basic mechanism used to model a
design in the dataflow style is the
continuous assignment.
• In a continuous assignment, a value is
assigned to a net.
• Syntax:
assign #delay LHS_net = RHS_expression;
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Behavioral Modeling
• The behavior of a design is described
using procedural constructs. These are:
– Initial statement: This statement executes
only once.
– Always statement: this statement always
executes in a loop forever…..
• Only register data type can be assigned
a value in either of these statements.
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Always Statement
• Syntax: always
#timing_control procedural_statement
• Procedural statement is one of :
– Blocking Procedural_assignment
always
@ (A or B or Cin)
begin
T1=A & B;
T2=B & Cin;
T3=A & Cin;
Cout=T1 | T2 | T3;
end
T1 assignment is occurs first, then T2, then T3….
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Procedural statements
Conditional_statement
always
@(posedge clk or posedge reset)
if ( Sum <60)
begin
Grade = C;
Total_C=Total_C +1;
end
else if (Sum<75)
Grade = B;
else
Grade = A;
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Let’s look at a file to review what
we have learned today…..
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References
• Couple of good verilog books here:
– A Verilog HDL Primer by J. Bhasker
– Verilog HDL: A Guide to Digital Design and
Synthesis by Samir Palnitkar
• Special thanks to
Professor Peckol and Professor Hauck for
their support and the tutorial documents
they provided…..
