- Hardware description languages (HDLs) allow designers to specify logic functions using code that is then synthesized into optimized gates by CAD tools. The two leading HDLs are Verilog and VHDL.
- HDL code is first simulated to verify correctness before being synthesized into a netlist describing the hardware as a list of gates and connections.
- Verilog modules can be behavioral, describing what a module does, or structural, describing how a module is built from simpler modules.
22. Inertial and Transport Delays
• Inertial Delay
– #3 X = A ;
• Wait 3 time units, then assign value of A to X
– The usual way delay is used in simulation
• models logic delay reasonably
• Transport Delay
– X <= #3 A ;
• Current value of A is assigned to X, after 3 time units
– Better model for transmission lines and high-speed
logic
Verilog - 22