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EET205 Analog Electronics
Module 5 Part 3
ARUN P B
Assistant Professor
Department Of EEE
Internal Diagram of 555 Timer IC
 555 IC consist of 8 pins.
 pin 1 : Ground
All voltages are measured w.r.t this
terminal
 Pin 2: Trigger
 IC 555 uses two comparators and a voltage divider consist of 3 equal
resistance.
 Due to voltage divider, the voltage of non inverting terminal of
comparator 2 is fixed at /3.
 Inverting terminal of comparator 1 is taken as trigger.
 If trigger input is less than /3 then comparator 2’s voltage
difference is positive, so its output goes high.
 If trigger is greater than /3 then comparator 2’s voltage
difference is negative and its output will goes low.
DET OF EEE,NSSCE
DET OF EEE,NSSCE
 Output of comparator 2 given as the reset input of R-S Flip flops.
 Pin 6: Threshold
 Threshold input is given as input to the non inverting terminal of
comparator 1.
 Inverting input of comparator 1 is ಴಴
.
 If threshold input is greater than ಴಴
then its output will goes high
or else goes low.
 Pin 3:output
 Complimentary output of R-S Flip flop is fed to output stage power
amplifier to get the output of 555 IC.
 Pin 4 : Reset
 This is an interrupt to the timing device. When pin 4 is grounded, it
stops the working of devices and make it off.
 This provide on/off feature of IC 555.
DET OF EEE,NSSCE
DET OF EEE,NSSCE
 Pin 5: Control Voltage
 In most cases control voltage is not used. Because the voltage at the
control input is already ಴಴
. For such cases it should be connected
to ground through a 0.01μF capacitor.
 If reference level required is other than
಴಴
 Pin 7:Discharge terminal
 This pin is connected internally to the collector of transistor.
 Mostly a capacitor is connected between this terminal and ground.
 When transistor saturates capacitor starts discharges.
 When transistor cut off capacitor starts charging.
 Pin 8:supply terminal
 A supply voltage of +5v to +18v is applied at this terminal.
DET OF EEE,NSSCE
Working of 555 Timer IC
 When the threshold voltage exceeds the control voltage, the output of
comparator 1 will set the input of flip flop and its output will be
high.
 A high output from the flip flop saturates the transistor and
capacitor starts discharges connected at pin 7.
 The complementary signal output of R S flip flop i.e. low goes to the
output at pin 3.
 This will continue until the comparator 2 triggers the flip flop.
 Even if the threshold input is less than control input comparator
cannot cause the flip flop to change again.
 To change the output of flip flop to low; the trigger input must fall
below /3 then comparator 2’s output is high causes the reset
action of flip flop.
 This makes low output at R S Flip flop and causes the transistor
to switch off and hence capacitor starts charging at pin 7
 Complementary output i.e. high value obtained as output at pin 3.
DET OF EEE,NSSCE
Astable multivibrator using IC 555
 Astable multivibrator also called as rectangular wave generator
circuit.
 Circuit doesn’t requires any trigger pulse to change the state of the
output, hence named as free running.
 Astable multivibrator can be obtained by adding two resistors and a
capacitor to the basic 555 IC.
 Timing during which the output either high or low is determined by
the external resistance and capacitance.
DET OF EEE,NSSCE
 Pin 1 is grounded, pin 4 and 8 are shorted and connected to ,
output is taken at pin 3, pin 2 and 6 are shorted and connected to
grounded through a capacitor C.
 Pin 7 is connected to supply through a resistance ,between pin 6
and 7 a resistance is connected.
Working
 When Q is low or output is high, the discharge transistor is cut
off and capacitor starts charging towards through resistance
and .
 So charging time constant is )C.
 As capacitor charges threshold voltage increases, when threshold
voltage exceeds ಴಴
, the comparator 1 has a high output and this
triggers the flip flop and makes output Q is high and timer output
low.
 With Q high discharge capacitor saturates and pin 7 grounded so that
capacitor starts discharges through .
DET OF EEE,NSSCE
DET OF EEE,NSSCE
 So discharge time constant is C.
 With discharging of capacitor, trigger voltage at inverting terminal of
comparator 2 decreases. When it drops below /3 , the output of
comparator 2 goes high and resets the flip flop and Q becomes low
and output of timer becomes high.
 This shows output switches from on transition level to another
automatically (low to high and vice versa).
 Voltage across the capacitor at any instant of time during charging
period is = (1-
ష೟
ೃ಴)…….(1)
if capacitor start charges from 0 to + ಴಴
during time
+ ಴಴
= (1-
ష೟భ
ೃ಴)
ష೟భ
ೃ಴= take antilog on both sides
భ
= ; =-RC
=0.405RC……….(2)
DET OF EEE,NSSCE
If capacitor starts charges from 0 to + during time
Eqn (1) becomes + = (1-
ష೟మ
ೃ಴)
+ =
ష೟మ
ೃ಴ ; take antilog on both sides
మ
= ; =-RC and thus =1.0986RC…….(3)
So capacitor charging from + ಴಴
to + so time period is defined as
= - i.e. (3)-(1)
= 1.0986RC- 0.405RC = 0.693RC………(4)
During capacitor charging it flows through and , since resistors
connected in series R= +
Eqn (4) becomes = 0.693 + C……….(5)
Voltage across the capacitor at any instant of time during capacitor
discharges is =
ష೟
ೃ಴……..(6)
Since capacitor starts discharge from + to + ಴಴
during time
DET OF EEE,NSSCE
Eqn (6) becomes + ಴಴
=
ష೟೚೑೑
ೃ಴
=
ష೟೚೑೑
ೃ಴; take antilog on both sides
= ೚೑೑
; =-RC
=+0.693RC here capacitor starts discharges through only so
=+0.693 C …….(7)
Therefore total time period is + so (6) +(7)
T= 0.693 + C + 0.693 C
T= 0.693 + 2 C…..(8)
The frequency of oscillation is reciprocal of time period
F= =
0.693 ಲ+ 2 ಳ C
=
ಲ+ 2 ಳ C
……….(9)
Duty cycle is defined as the ratio of on time to total time period
D= ೚೙
=
0.693 ಲ+ ಳ C
0.693 ಲ+ 2 ಳ C
= ಲ+ ಳ
ಲ+ 2 ಳ
……….(10)
DET OF EEE,NSSCE
Numerical Problem
 Design a 555 Timer as astable multivibrator with an output signal
frequency of 800Hz and 60 percent duty cycle.
Percent duty cycle is ಲ+ ಳ
ಲ+ 2 ಳ
=
100 + )=60 + 2
=2
Frequency is given by
ಲ+ 2 ಳ C
=800
Put eqn (1) and assume C=0.01μF
800=
ಲ+ 2 2 ಲ
షల
=36,000Ω =36kΩ
=2 =72kΩ
DET OF EEE,NSSCE
Tutorial
1.Design a 555 Timer as astable multivibrator with output signal
frequency 0f 700Hz and 50% duty cycle.
2.Determine the positive pulse width,negative pulse width and free
running frequency for an astable multivibrator using 555 =4.7kΩ,
=1kΩ and C=1μF.
DET OF EEE,NSSCE
555 Timer as Monostable Multivibrator(MMV)
 It is a one shot multivibrator, a pulse generator circuit in which the
duration of the pulse is controlled by the RC network.
 Here one state is stable while the other is quasi stable (unstable) state.
 For auto triggering of output from quasi stable state to stable state
energy is stored in the externally connected capacitor C to a reference
level.
 Time taken for storage determines the pulse width.
 The transition of output stable to quasi stable state is accomplished
by external trigger pulse.
 Pin 1 is grounded. Trigger input is applied at pin 2 .to obtain the
transition of output from stable state to quasi stable state by applying
negative pulse of narrow width at pin 2.
 Pin 4 and pin 8 shorted and connected to , Pin 5 is grounded
through 0.01μF capacitor . Pin 6 and 7 are shorted.
DET OF EEE,NSSCE
 A resistor is connected between pin 6 and 8. at pin 7 a discharge
capacitor is connected.
Working
 Initially, When the output at pin 3 is low i.e. the circuit is in stable
state, the discharge transistor is on and capacitor C is shorted to
ground.
 When a negative pulse is applied at pin 2, the trigger input falls
below the ಴಴
, the output of comparator 2 goes high this causes the
reset of R-S flip flop and thus output Q becomes zero and becomes
high.
 Consequently discharge transistor cut off and hence capacitor starts
charges to through and C .
 So charging time constant is .
 When the capacitor voltage slightly greater than ಴಴
then the
comparator 1’s output goes high, which sets the Flip flop. This
makes Q high and is low.
DET OF EEE,NSSCE
 The transistor saturates and makes the capacitor connected to ground.
 The output of MMV remains low until a trigger pulse is again applied.
DET OF EEE,NSSCE
 Voltage across the capacitor at any instant of time during charging
period is given as
= (1-
ష೟
ೃ಴) here capacitor charges to ಴಴
so = ಴಴
and charging time constant is
಴಴
= (1-
ష೟
ೃಲ಴
)…….(1)
t= ;
t= 1.0986

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Module 5 Part 3.pdf

  • 1. EET205 Analog Electronics Module 5 Part 3 ARUN P B Assistant Professor Department Of EEE
  • 2. Internal Diagram of 555 Timer IC  555 IC consist of 8 pins.  pin 1 : Ground All voltages are measured w.r.t this terminal  Pin 2: Trigger  IC 555 uses two comparators and a voltage divider consist of 3 equal resistance.  Due to voltage divider, the voltage of non inverting terminal of comparator 2 is fixed at /3.  Inverting terminal of comparator 1 is taken as trigger.  If trigger input is less than /3 then comparator 2’s voltage difference is positive, so its output goes high.  If trigger is greater than /3 then comparator 2’s voltage difference is negative and its output will goes low. DET OF EEE,NSSCE
  • 4.  Output of comparator 2 given as the reset input of R-S Flip flops.  Pin 6: Threshold  Threshold input is given as input to the non inverting terminal of comparator 1.  Inverting input of comparator 1 is ಴಴ .  If threshold input is greater than ಴಴ then its output will goes high or else goes low.  Pin 3:output  Complimentary output of R-S Flip flop is fed to output stage power amplifier to get the output of 555 IC.  Pin 4 : Reset  This is an interrupt to the timing device. When pin 4 is grounded, it stops the working of devices and make it off.  This provide on/off feature of IC 555. DET OF EEE,NSSCE
  • 5. DET OF EEE,NSSCE  Pin 5: Control Voltage  In most cases control voltage is not used. Because the voltage at the control input is already ಴಴ . For such cases it should be connected to ground through a 0.01μF capacitor.  If reference level required is other than ಴಴  Pin 7:Discharge terminal  This pin is connected internally to the collector of transistor.  Mostly a capacitor is connected between this terminal and ground.  When transistor saturates capacitor starts discharges.  When transistor cut off capacitor starts charging.  Pin 8:supply terminal  A supply voltage of +5v to +18v is applied at this terminal.
  • 6. DET OF EEE,NSSCE Working of 555 Timer IC  When the threshold voltage exceeds the control voltage, the output of comparator 1 will set the input of flip flop and its output will be high.  A high output from the flip flop saturates the transistor and capacitor starts discharges connected at pin 7.  The complementary signal output of R S flip flop i.e. low goes to the output at pin 3.  This will continue until the comparator 2 triggers the flip flop.  Even if the threshold input is less than control input comparator cannot cause the flip flop to change again.  To change the output of flip flop to low; the trigger input must fall below /3 then comparator 2’s output is high causes the reset action of flip flop.  This makes low output at R S Flip flop and causes the transistor to switch off and hence capacitor starts charging at pin 7  Complementary output i.e. high value obtained as output at pin 3.
  • 7. DET OF EEE,NSSCE Astable multivibrator using IC 555  Astable multivibrator also called as rectangular wave generator circuit.  Circuit doesn’t requires any trigger pulse to change the state of the output, hence named as free running.  Astable multivibrator can be obtained by adding two resistors and a capacitor to the basic 555 IC.  Timing during which the output either high or low is determined by the external resistance and capacitance.
  • 8. DET OF EEE,NSSCE  Pin 1 is grounded, pin 4 and 8 are shorted and connected to , output is taken at pin 3, pin 2 and 6 are shorted and connected to grounded through a capacitor C.  Pin 7 is connected to supply through a resistance ,between pin 6 and 7 a resistance is connected. Working  When Q is low or output is high, the discharge transistor is cut off and capacitor starts charging towards through resistance and .  So charging time constant is )C.  As capacitor charges threshold voltage increases, when threshold voltage exceeds ಴಴ , the comparator 1 has a high output and this triggers the flip flop and makes output Q is high and timer output low.  With Q high discharge capacitor saturates and pin 7 grounded so that capacitor starts discharges through .
  • 10. DET OF EEE,NSSCE  So discharge time constant is C.  With discharging of capacitor, trigger voltage at inverting terminal of comparator 2 decreases. When it drops below /3 , the output of comparator 2 goes high and resets the flip flop and Q becomes low and output of timer becomes high.  This shows output switches from on transition level to another automatically (low to high and vice versa).  Voltage across the capacitor at any instant of time during charging period is = (1- ష೟ ೃ಴)…….(1) if capacitor start charges from 0 to + ಴಴ during time + ಴಴ = (1- ష೟భ ೃ಴) ష೟భ ೃ಴= take antilog on both sides భ = ; =-RC =0.405RC……….(2)
  • 11. DET OF EEE,NSSCE If capacitor starts charges from 0 to + during time Eqn (1) becomes + = (1- ష೟మ ೃ಴) + = ష೟మ ೃ಴ ; take antilog on both sides మ = ; =-RC and thus =1.0986RC…….(3) So capacitor charging from + ಴಴ to + so time period is defined as = - i.e. (3)-(1) = 1.0986RC- 0.405RC = 0.693RC………(4) During capacitor charging it flows through and , since resistors connected in series R= + Eqn (4) becomes = 0.693 + C……….(5) Voltage across the capacitor at any instant of time during capacitor discharges is = ష೟ ೃ಴……..(6) Since capacitor starts discharge from + to + ಴಴ during time
  • 12. DET OF EEE,NSSCE Eqn (6) becomes + ಴಴ = ష೟೚೑೑ ೃ಴ = ష೟೚೑೑ ೃ಴; take antilog on both sides = ೚೑೑ ; =-RC =+0.693RC here capacitor starts discharges through only so =+0.693 C …….(7) Therefore total time period is + so (6) +(7) T= 0.693 + C + 0.693 C T= 0.693 + 2 C…..(8) The frequency of oscillation is reciprocal of time period F= = 0.693 ಲ+ 2 ಳ C = ಲ+ 2 ಳ C ……….(9) Duty cycle is defined as the ratio of on time to total time period D= ೚೙ = 0.693 ಲ+ ಳ C 0.693 ಲ+ 2 ಳ C = ಲ+ ಳ ಲ+ 2 ಳ ……….(10)
  • 13. DET OF EEE,NSSCE Numerical Problem  Design a 555 Timer as astable multivibrator with an output signal frequency of 800Hz and 60 percent duty cycle. Percent duty cycle is ಲ+ ಳ ಲ+ 2 ಳ = 100 + )=60 + 2 =2 Frequency is given by ಲ+ 2 ಳ C =800 Put eqn (1) and assume C=0.01μF 800= ಲ+ 2 2 ಲ షల =36,000Ω =36kΩ =2 =72kΩ
  • 14. DET OF EEE,NSSCE Tutorial 1.Design a 555 Timer as astable multivibrator with output signal frequency 0f 700Hz and 50% duty cycle. 2.Determine the positive pulse width,negative pulse width and free running frequency for an astable multivibrator using 555 =4.7kΩ, =1kΩ and C=1μF.
  • 15. DET OF EEE,NSSCE 555 Timer as Monostable Multivibrator(MMV)  It is a one shot multivibrator, a pulse generator circuit in which the duration of the pulse is controlled by the RC network.  Here one state is stable while the other is quasi stable (unstable) state.  For auto triggering of output from quasi stable state to stable state energy is stored in the externally connected capacitor C to a reference level.  Time taken for storage determines the pulse width.  The transition of output stable to quasi stable state is accomplished by external trigger pulse.  Pin 1 is grounded. Trigger input is applied at pin 2 .to obtain the transition of output from stable state to quasi stable state by applying negative pulse of narrow width at pin 2.  Pin 4 and pin 8 shorted and connected to , Pin 5 is grounded through 0.01μF capacitor . Pin 6 and 7 are shorted.
  • 16. DET OF EEE,NSSCE  A resistor is connected between pin 6 and 8. at pin 7 a discharge capacitor is connected. Working  Initially, When the output at pin 3 is low i.e. the circuit is in stable state, the discharge transistor is on and capacitor C is shorted to ground.  When a negative pulse is applied at pin 2, the trigger input falls below the ಴಴ , the output of comparator 2 goes high this causes the reset of R-S flip flop and thus output Q becomes zero and becomes high.  Consequently discharge transistor cut off and hence capacitor starts charges to through and C .  So charging time constant is .  When the capacitor voltage slightly greater than ಴಴ then the comparator 1’s output goes high, which sets the Flip flop. This makes Q high and is low.
  • 17. DET OF EEE,NSSCE  The transistor saturates and makes the capacitor connected to ground.  The output of MMV remains low until a trigger pulse is again applied.
  • 18. DET OF EEE,NSSCE  Voltage across the capacitor at any instant of time during charging period is given as = (1- ష೟ ೃ಴) here capacitor charges to ಴಴ so = ಴಴ and charging time constant is ಴಴ = (1- ష೟ ೃಲ಴ )…….(1) t= ; t= 1.0986