1. Zanjan University
Department of Electrical Engineering
Bachelor Thesis
Title
Making PLC (Programmable logic controller) by FPGA and
microcontroller
By
Mojtaba Hajimiri
Ali nilechi
Supervisor
Dr. Siroos Toofan
2. PLC (Programmable logic controller) is one of the important
parts in industry. So our purpose in this project were making a
PLC. Towards this end, an electrical circuit is designed based
on FPGA and other microcontrollers. Then, a PCB is designed
using altium designer, and the functionality of the board is
tested.
Our PLC in here contains 2 boards :
1- main board: this board consist of altera cyclone ii
EP2C8T144C8 FPGA and atmega128. we used this board as
our main board. We writes the PLCs main program in quartus
software (by graphical language-like FBD in PLC) on FPGA
and then we sends our commands to atmega128 microcontroller
that can be connected to our power board (by rs232 or ...).
2-power board: this board consists of atmega128
microcontroller as main processor and can been connected to
our main board (by rs232 or ...). We used this board as our
input-output board. this board consists of some protection
circuits in his inputs that can be acquire different types of
inputs. in this board we used relays to control automation
systems.
7. lcd & hmtr & mmc circuit:
1
2
3
4
5
6
HMTR
Header
6
V
C
C
V
C
C
G
N
D
G
N
D
rx0
tx0
V
C
C
G
N
D
V
C
C
3
1
2
1
0
K
R_LCD
RPot
G
N
D
1
2
3
4
5
6
7
8
eeprom
Header
4X2
G
N
D
G
N
D
1
VCC
2
V
O
3
R
S
4
R/W
5
E
6
DB0
7
DB1
8
DB2
9
DB3
1
0
DB4
1
1
DB5
1
2
DB6
1
3
DB7
1
4
A
1
5
K
1
6
LCD
1
2
3
4
5
6
7
8
9
1
0
m
m
c
Header
10
1
K
rmmc1
Res1
1
K
rmmc2
Res1
s
s
o
mosio
v
3
3
scko
v
3
3
v
3
3
G
N
D
misoo
c
4
c
5
c
6
c
7
c
0
c
1
c
2
V
C
C
G
N
D
V
C
C
SDA
14. atmega 128 schematic:
P
E
N
1
PE0
(RXD0/PDI)
2
PE1
(TXD0/PDO)
3
PE2
(XCK0/AIN0)
4
PE3
(OC3A/AIN1)
5
PE4
(OC3B/INT4)
6
PE5
(OC3C/INT5)
7
PE6
(T3/INT6)
8
PE7
(IC3/INT7)
9
PB0
(SS)
1
0
PB1
(SCK)
1
1
PB2
(MOSI)
1
2
PB3
(MISO)
1
3
PB4
(OC0)
1
4
PB5
(OC1A)
1
5
PB6
(OC1B)
1
6
PB7
(OC2/OC1C)
1
7
TOSC2/PG3
1
8
TOSC1/1PG4
1
9
RESET
2
0
V
C
C
2
1
G
N
D
2
2
XTAL2
2
3
XTAL1
2
4
PD0
(SCL/INT0)
2
5
PD1
(SDA/INT1)
2
6
PD2
(RXD1/INT2)
2
7
PD3
(TXD1/INT3)
2
8
PD4
(IC1)
2
9
PD5
(XCK1)
3
0
PD6
(T1)
3
1
PD7
(T2)
3
2
PG0
(WR)
3
3
PG1
(RD)
3
4
PC0
(A8)
3
5
PC1
(A9)
3
6
PC2
(A10)
3
7
PC3
(A11)
3
8
PC4
(A12)
3
9
PC5
(A13)
4
0
PC6
(A14)
4
1
PC7
(A15)
4
2
PG2
(ALE)
4
3
PA7
(AD7)
4
4
PA6
(AD6)
4
5
PA5
(AD5)
4
6
PA4
(AD4)
4
7
PA3
(AD3)
4
8
PA2
(AD2)
4
9
PA1
(AD1)
5
0
PA0
(AD0)
5
1
V
C
C
5
2
G
N
D
5
3
PF7
(ADC7/TDI)
5
4
PF6
(ADC6/TDO)
5
5
PF5
(ADC5/TMS)
5
6
PF4
(ADC4/TCK)
5
7
PF3
(ADC3)
5
8
PF2
(ADC2)
5
9
PF1
(ADC1)
6
0
PF0
(ADC0)
6
1
AREF
6
2
G
N
D
6
3
A
V
C
C
6
4
micro
ATmega128-16AC
1
2
3
4
5
6
7
8
9
1
0
programer
Header
5X2
V
C
C
G
N
D
reset
rx0
tx0
rx0
tx0
reset
SW_RESET
SW-PB
G
N
D
1
K
R
8
Res1
V
C
C
1
2
XTAL
XTAL
1
0
0
p
F
cx1
Cap
1
0
0
p
F
cx2
Cap
G
N
D
1
2
3
4
5
6
HMTR
Header
6
V
C
C
V
C
C
G
N
D
rx0
tx0
G
N
D
V
C
C
G
N
D
V
C
C
G
N
D
G
N
D
1
VCC
2
V
O
3
R
S
4
R/W
5
E
6
DB0
7
DB1
8
DB2
9
DB3
1
0
DB4
1
1
DB5
1
2
DB6
1
3
DB7
1
4
A
1
5
K
1
6
LCD
c
0
c
1
c
2
c
4
c
5
c
6
c
7
1
2
3
4
5
6
7
8
9
1
0
ADC_PORT
Header
5X2
f
0
f
1
f
2
f
3
f
4
f
5
f
6
f
7
f
0
f
1
f
2
f
3
f
4
f
5
f
6
f
7
G
N
D
a_ref
a_ref
1
0
0
n
F
C40
Cap
1
0
0
n
F
C41
Cap
1
0
0
n
F
C38
Cap
G
N
D
G
N
D
1
0
0
n
F
C39
Cap
G
N
D
G
N
D
V
C
C
1
K
R10
Res3
1
2
3
4
5
6
7
8
9
1
0
PIN_OUT
Header
5X2
G
N
D
G
N
D
a
5
a
6
a
7
G
N
D
m_UART_TXD
m_UART_RXD
V
C
C
1
0
K
R
9
Res3
1
2
XTAL1
32.768kHZ
b
0
b
1
b
2
b
4
b
5
b
6
b
7
g
0
g
1
g
2
b
0
b
1
b
2
b
4
b
5
b
6
b
7
c
3
e
0
e
1
e
2
e
3
e
4
e
5
e
6
e
7
e
0
e
1
e
2
e
3
e
4
e
5
e
6
e
7
g
3
d
4
d
5
d
6
d
7
a
0
a
1
a
2
a
3
a
4
1
2
3
4
xtal_jumper
Header
2X2
V
C
C
m_UART_RXD
m_UART_TXD
b
1
3
3
0
R27
Res1
3
1
2
1
0
K
R_lcd
RPot
15. FPGA & microcontroller connection:
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m1
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m4
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m2
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m3
74LVX4245
g
0
g
1
g
2
g
3
V
C
C
V
C
C
V
C
C
V
C
C
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
a
0
a
1
a
2
a
3
a
4
a
5
a
6
a
7
c
0
c
1
c
2
c
3
c
4
c
5
c
6
c
7
d
4
d
5
d
6
d
7
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
139_m_T/R
141_m_N_OE
142_m_I
143_m_I
144_m_I
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
24_m_T/R
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
40_m_T/R
41_m_N_OE
42_m_I
43_m_I
44_m_I
45_m_I
125_m_T/R
G
N
D
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
141_m_N_OE
142_m_I
143_m_I
144_m_I
42_m_I
43_m_I
44_m_I
45_m_I
41_m_N_OE
