Actively Seeking Opportunity in VLSI& Semiconductor Industry. Looking for a challenging career to enhance my professional ability, skills and technical knowledge and growth in Semiconductor industry.
1. MANSOORALIKHAN A
Email: mansooralikhan2016@gmail.com
Mobile: +91-9087503679
OBJECTIVE
To pursue a challenging career in an organization that offers continuous building of
conventional skills, innovative ingenuity and promotes exposure to the recent technologies.
ACADEMIC DETAILS
COURSE INSTITUTE YEAR PERCENTAGE/
CGPA
M.E
(VLSI Design)
College of Engineering
Guindy(CEG),Anna University 2014-2016 7.20
B.E
(ECE)
Anna University of Technology,
Trichy 2010-2014 7.34
HSC Indian Matriculation Higher
Secondary School
2008-2010 92.9%
SSLC Government Higher Secondary
School
2008 92.4%
TECHNICAL EXPOSURE
Programming Language : C, Verilog ,VHDL,RTL
EDA Tools : Cadence Virtuoso(180nm),Xilinx ISE Design Suite
Simulation Tools : MATLAB, LT Spice,Keil
AREA OF INTEREST
Digital Electronics
Digital System Design
ASIC Front End and Back End
Physical Design , RTL Design
RESEARCH AND PROJECTS
ME PROJECT :
“Segmentation Based Energy Efficient Approximate Multiplier for
Digital Signal Processing”
2. OBJECTIVE :
The purpose of this project is to design and construct low power, area ,energy
efficient multiplier. To reduce this energy consumption we apply new multiplication techniques
in the multipliers. The proposed multiplier compared with a precise multiplier can consume 58%
less energy. In the proposed multiplier architecture, the area has reduced compared to other
multiplier architectures which process same number of bits.
My work is to implement new multiplication technique in Xilinx ISE Design
Suite and Power, Area, Delay calculated by Cadence Virutoso 180nm tool.
BE PROJECT:
“A True Random-Based Differential Power Analysis Countermeasure
Circuit for an AES Engine”
OBJECTIVE :
The purpose of this project resolving a security problem on ring oscillators and
implementing a new architecture with self-generated true random sequence.The true random
based architecture is implemented with an AES in Xilinx ISE Design Suite tool.
RESEARCH PUBLICATION
My project has been published in the journal IJARECE(The
International Journal of Advanced Research in Electronics and Communication
Engineering) at Volume 5, Issue 3, March 2016
PERSONAL DETAILS
Date of birth : 10.06.1993
Sex : Male
Nationality : Indian
Marital Status : Single
Languages known : English, Tamil (Read and Write)
Address : 3/566,Marukkalam patti (village),Alapuram(po)
Pappireddipatti(Tk),Dharmapuri (Dt)-636904
DECLARATION
I hereby declare that all the above details furnished by me are true and correct
to the best of my knowledge and belief.
DATE :
PLACE: CHENNAI ( A. Mansooralikhan)
