1. PANAMALA VENKATESWARLU Phone: +91-8019137246
mail: venkateswarlu.panamala@gmail.com
Objective:
To join in an organization which provides an excellent opportunity to enhance my
skills and play a vital role for the development of the organization.
Academic Qualifications:
Study School/college Board/university Academic
year
Percentage
of marks
M.TECH
(VDES)
Gayatri Vidya
Parishad College of
Engineering(A) JNTUK 2014-2016
88.85
(Up to I-
Sem)
PG Diploma in
VLSI Physical
Design
Institute of Silicon
Systems
---- 2012-2013 A Grade
B.Tech
(ECE)
DMS SVH College
Of Engineering
Acharya
Nagarjuna
University
2008-2012
85.69%
INTERMEDIATE Sri Prathiba Junior
College
Board of
Intermediate.
2006-2008 95.3%
S.S.C ZPHS, Kothapatnam,
Ongole.
Board of
Secondary
Education. 2005-2006
80.33%
Projects:
Physical Design
Project 1: (Peripheral Component Interconnect-Top level)
Role: To perform Timing Driven Layout with clock frequency of 149.9MHz, audit
checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing Analysis, CTS,
Detail Routing. To achieve 0 % congestion at trial route stage.
2. PANAMALA VENKATESWARLU Phone: +91-8019137246
mail: venkateswarlu.panamala@gmail.com
Project 2: (Bluetooth-Top level)
Role: To observe the usage of metal layers, perform audit checks, Floor Plan, Power
Plan, Placement, IPO, Trial Route, Timing Analysis, CTS, and Detail Routing. To observe
the relation between core utilization, wire length and number of metal layers.
Project 3: (Spectrum-Block level)
Role: To perform Timing Driven Layout, audit checks, Floor Plan, Power Plan,
Placement, IPO, Trial Route, Timing Analysis, CTS, Detail Routing, RC extract, STA.
Logic synthesis
Project 1 An 8-bit synchronous counter with asynchronous reset.
Project 2 A 256-bit Counter.
Role: To find the frequency of operation of the counter and to generate the constraint file,
TCL file and close timing by performing Wire load and Zero Wire load model.
Layout
Tools : Cadence Virtuoso
Design : Basic gates
Role: Designed Layouts for Digital and Analog Circuits.
Academic Projects:
Title: CBIR USING CSIFT ON DERMATOLOGICAL IMAGES
Abstract:
This project proposes a Content Based Image Retrieval (CBIR) system using
Color Scale Invariant Feature Transform (CSIFT) for skin lesion images, which can be a
helpful diagnostic tool to the Dermatologists. The aim of this work is to support decision
making by retrieving and displaying relevant past cases visually similar to the one under
examination.
Responsibilities: Referred various IEEE papers for the best algorithm to be
suited for the project and for the best retrieval rates.
Experiences:
Experienced in designing of ASIC and Analog ICs with 130nm and 90nm
technologies using Cadence tools.
Experienced in Embedded Programming of various development boards like
PIC16F877A, Arduino Uno and AT89S52.
3. PANAMALA VENKATESWARLU Phone: +91-8019137246
mail: venkateswarlu.panamala@gmail.com
Extra-Curricular Activities:
Achieved the certificate of “BEST ALL ROUNDER” in ECE department of
D.M.S.S.V.H College of engineering.
Achieved the certificate of First in D.M.S.S.V.H College of Engineering by scoring
maximum marks among all the boys’ students of all Engineering Branches.
Participate in a National level Workshop on Robotics conducted by BIT in
association with “GREASTEP, IIT, Kharagpur” at Satyamangalam, Coimbatore.
Presented a National level technical paper on “Mobile ADHOC Networks”
conducted by S.R.K.R Engineering College, Bhimavaram.
Technical Skills:
• Operating Systems : Windows, Linux
• Hardware description Languages : Verilog, VHDL
• EDA Tools : Xilinx ISE 9.0, Microwind
• Frontend Synthesis Tools : Cadence RTL Compiler.
• Backend Tools : Cadence SOC Encounter, Cadence ETS, Virtuoso.
• Scripting Languages : TCL
Personal Profile:
Name : PANAMALA VENKATESWARLU
Fathers Name : PANAMALA SYAMASUNDARA RAO
Date of Birth : 05-07-1991
Nationality : Indian
Mobile : +918019137246
E-mail : venkateswarlu.panamala@gmail.com
Languages Known : Telugu, English.
Hobbies : Playing Cricket, Volleyball.
Declaration:
I hereby declare that all the information furnished above is true to the best of my
knowledge and belief.
Place:
