An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

1. An On-Chip Monitoring Circuit for Signal-Integrity
Analysis of 8-Gb/s Chip-to-Chip Interfaces with Source-
Synchronous Clock
ABSTRACT:
This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal
integrity of high speed signals for a chip-to-chip interface with a source
synchronous clocking scheme. The proposed OCMC consists of a fractional-N
phase-locked loop (PLL)-based frequency synthesizer, a high-bandwidth track-
and-hold circuit, and a 10-bit analog-to-digital converter (ADC) to implement a
subsampling scheme. The proposed fractional-N PLL-based frequency synthesizer
improves the time jitter accumulated in a voltage controlled oscillator using a
fractional frequency divider operated by an eight-phase clock. The bandwidth of
the track-and hold circuit is designed to be 6 GHz, using inductive peaking realized
through a source follower. The OCMC samples 49 points over two unit intervals of
a high-speed input signal when the frequency multiplication of the frequency
synthesizer is 6.125/6. The 10-bit ADC uses the architecture of a pipelined
successive approximation register ADC to reduce the power consumption and chip
area. The proposed OCMC is implemented with 65-nm CMOS technology and a
1.2 V supply. The 8-Gb/s chip-to-chip interface signal is reconstructed with time
and voltage resolutions of 5.1 ps and 1.17 mV, respectively. The proposed

2. architecture of this paper analysis the logic size, area and power consumption using
tanner tool.
SOFTWARE IMPLEMENTATION:
 Tanner tool