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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 10
Input/Output Organization
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter Outline
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Data Transfers
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Source-initiated Data Transfer
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Destination-initiated Data
Transfer
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Source-initiated Data Transfer
with Handshaking
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Destination-initiated Data
Transfer with Handshaking
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Programmed I/O
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Example
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Example
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Example
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Example
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Example
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New Instructions
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New Control Signals
• IO differentiates I/O and memory
accesses
– IO = 1 for I/O access
– IO = 0 for memory access
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New States and RTL Code
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CPU Modifications
• Modify register section
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CPU Modifications
• Modify register section
• Modify ALU
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CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
• Register and ALU sections unchanged
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
• Register and ALU sections unchanged
• One new micro-operation: DR  Input
Port
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Control Unit Changes
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Control Unit Changes - INC
and CLR signals
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Control Unit Changes - INC
and CLR signals
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes -
Memory Read Signal
• Memory Read = READ ^ IO’
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Interrupts
• Polling
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Interrupts
• IRQ - Interrupt Request
• IACK - Interrupt Acknowledge
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Types of Interrupts
• External
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Types of Interrupts
• External
• Internal
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Types of Interrupts
• External
• Internal
• Software
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Processing Interrupts
• Do nothing (until the current instruction
has been executed)
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Processing Interrupts
• Do nothing (until the current instruction
has been executed)
• Get handler address (vectored)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
• Do nothing (until the current instruction
has been executed)
• Get handler address (vectored)
• Invoke handler routine
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Vectored Interrupt Hardware
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Non-vectored Interrupt
Hardware
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Multiple Non-vectored
Interrupts
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Daisy Chaining
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IACKin and IACKout
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Parallel Priority Interrupts
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CPU Modifications
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CPU Modifications
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Interrupt States
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Direct Memory Access
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DMA Controller
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DMA Transfer Modes
• Block/Burst Mode
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DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode
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DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode
• Transparent Mode
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-
operations
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CPU Modifications - Micro-
operations
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CPU Modifications
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CPU Modifications
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I/O Processors
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I/O Processors - operations
• Block transfer commands
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I/O Processors - operations
• Block transfer commands
• ALU operations
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I/O Processors - operations
• Block transfer commands
• ALU operations
• Control commands
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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
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Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
• stop bit(s)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
• stop bit(s)
• bit time
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
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Synchronous Serial
Communication - HDLC
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Asynchronous
Receiver/Transmitters
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UART Internal Configuration
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• Request To Send
• Clear To Send
• Transmission Data
• Data Terminal Ready
• Data Set Ready
• Received Data
• Data Carrier Detect
• Ring Indicator
• Ground
RS 232C Standard - Signals
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RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
• Use DCD to establish connectivity
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
• Use DCD to establish connectivity
• Use TD and RD to transfer data, and
RTS and CTS to coordinate transfers
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 422 Standard - Signals
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Universal Serial Bus Standard
• Connects one port to several devices
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Universal Serial Bus Standard
• Connects one port to several devices
• Transfers data in packets
– Token packets
– Data packets
– Handshake packets
– Special Packets
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
USB Packet Formats
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Summary
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards

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Chapter10.ppt

  • 1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Input/Output Organization
  • 2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline • Asynchronous data transfers • Programmed I/O • Interrupts • Direct Memory Access • I/O Processors • Serial Communication • Serial Communication Standards
  • 3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Data Transfers
  • 4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer
  • 5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer
  • 6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer with Handshaking
  • 7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer with Handshaking
  • 8. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Programmed I/O
  • 9. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example
  • 10. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example
  • 11. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example
  • 12. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example
  • 13. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example
  • 14. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Instructions
  • 15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Control Signals • IO differentiates I/O and memory accesses – IO = 1 for I/O access – IO = 0 for memory access
  • 16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New States and RTL Code
  • 17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section
  • 18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section • Modify ALU
  • 19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section • Modify ALU • Modify control unit (hard-wired)
  • 20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section • Modify ALU • Modify control unit (hard-wired) • Register and ALU sections unchanged
  • 21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications • Modify register section • Modify ALU • Modify control unit (hard-wired) • Register and ALU sections unchanged • One new micro-operation: DR  Input Port
  • 22. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes
  • 23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals
  • 24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals
  • 25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - Memory Read Signal • Memory Read = READ ^ IO’
  • 26. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts • Polling
  • 27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts • IRQ - Interrupt Request • IACK - Interrupt Acknowledge
  • 28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts • External
  • 29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts • External • Internal
  • 30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts • External • Internal • Software
  • 31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts • Do nothing (until the current instruction has been executed)
  • 32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts • Do nothing (until the current instruction has been executed) • Get handler address (vectored)
  • 33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts • Do nothing (until the current instruction has been executed) • Get handler address (vectored) • Invoke handler routine
  • 34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vectored Interrupt Hardware
  • 35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-vectored Interrupt Hardware
  • 36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiple Non-vectored Interrupts
  • 37. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Daisy Chaining
  • 38. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IACKin and IACKout
  • 39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Parallel Priority Interrupts
  • 40. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications
  • 41. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications
  • 42. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupt States
  • 43. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Direct Memory Access
  • 44. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Controller
  • 45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes • Block/Burst Mode
  • 46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes • Block/Burst Mode • Cycle Stealing Mode
  • 47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes • Block/Burst Mode • Cycle Stealing Mode • Transparent Mode
  • 48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations
  • 49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations
  • 50. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications
  • 51. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications
  • 52. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors
  • 53. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations • Block transfer commands
  • 54. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations • Block transfer commands • ALU operations
  • 55. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations • Block transfer commands • ALU operations • Control commands
  • 56. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication • bps - Bits Per Second (baud rate)
  • 57. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication • bps - Bits Per Second (baud rate) • start bit
  • 58. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication • bps - Bits Per Second (baud rate) • start bit • parity bit
  • 59. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication • bps - Bits Per Second (baud rate) • start bit • parity bit • stop bit(s)
  • 60. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication • bps - Bits Per Second (baud rate) • start bit • parity bit • stop bit(s) • bit time
  • 61. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication
  • 62. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Synchronous Serial Communication - HDLC
  • 63. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Asynchronous Receiver/Transmitters
  • 64. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 UART Internal Configuration
  • 65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 • Request To Send • Clear To Send • Transmission Data • Data Terminal Ready • Data Set Ready • Received Data • Data Carrier Detect • Ring Indicator • Ground RS 232C Standard - Signals
  • 66. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active
  • 67. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active • Use RI to indicate call status
  • 68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active • Use RI to indicate call status • Use DCD to establish connectivity
  • 69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection • Use RTS, CTS, DTR, and DSR to verify that both devices are active • Use RI to indicate call status • Use DCD to establish connectivity • Use TD and RD to transfer data, and RTS and CTS to coordinate transfers
  • 70. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 422 Standard - Signals
  • 71. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard • Connects one port to several devices
  • 72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard • Connects one port to several devices • Transfers data in packets – Token packets – Data packets – Handshake packets – Special Packets
  • 73. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 USB Packet Formats
  • 74. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary • Asynchronous data transfers • Programmed I/O • Interrupts • Direct Memory Access • I/O Processors • Serial Communication • Serial Communication Standards