More Related Content
More from AshokRachapalli1 (20)
Chapter10.ppt
- 1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 10
Input/Output Organization
- 2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter Outline
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards
- 3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Data Transfers
- 4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer
- 5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data
Transfer
- 6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Source-initiated Data Transfer
with Handshaking
- 7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Destination-initiated Data
Transfer with Handshaking
- 15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New Control Signals
• IO differentiates I/O and memory
accesses
– IO = 1 for I/O access
– IO = 0 for memory access
- 16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
New States and RTL Code
- 17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
- 18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
- 19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
- 20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
• Register and ALU sections unchanged
- 21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications
• Modify register section
• Modify ALU
• Modify control unit (hard-wired)
• Register and ALU sections unchanged
• One new micro-operation: DR Input
Port
- 23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC
and CLR signals
- 24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes - INC
and CLR signals
- 25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Control Unit Changes -
Memory Read Signal
• Memory Read = READ ^ IO’
- 27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Interrupts
• IRQ - Interrupt Request
• IACK - Interrupt Acknowledge
- 28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of Interrupts
• External
- 29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of Interrupts
• External
• Internal
- 30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Types of Interrupts
• External
• Internal
• Software
- 31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
• Do nothing (until the current instruction
has been executed)
- 32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
• Do nothing (until the current instruction
has been executed)
• Get handler address (vectored)
- 33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Processing Interrupts
• Do nothing (until the current instruction
has been executed)
• Get handler address (vectored)
• Invoke handler routine
- 34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Vectored Interrupt Hardware
- 35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Non-vectored Interrupt
Hardware
- 36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Multiple Non-vectored
Interrupts
- 39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Parallel Priority Interrupts
- 45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer Modes
• Block/Burst Mode
- 46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode
- 47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
DMA Transfer Modes
• Block/Burst Mode
• Cycle Stealing Mode
• Transparent Mode
- 48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-
operations
- 49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
CPU Modifications - Micro-
operations
- 53. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
• Block transfer commands
- 54. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
• Block transfer commands
• ALU operations
- 55. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
I/O Processors - operations
• Block transfer commands
• ALU operations
• Control commands
- 56. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
- 57. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
- 58. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
- 59. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
• stop bit(s)
- 60. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
• bps - Bits Per Second (baud rate)
• start bit
• parity bit
• stop bit(s)
• bit time
- 61. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Asynchronous Serial
Communication
- 62. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Synchronous Serial
Communication - HDLC
- 63. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Asynchronous
Receiver/Transmitters
- 64. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
UART Internal Configuration
- 65. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
• Request To Send
• Clear To Send
• Transmission Data
• Data Terminal Ready
• Data Set Ready
• Received Data
• Data Carrier Detect
• Ring Indicator
• Ground
RS 232C Standard - Signals
- 66. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
- 67. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
- 68. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
• Use DCD to establish connectivity
- 69. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 232C Standard -
Connection
• Use RTS, CTS, DTR, and DSR to verify
that both devices are active
• Use RI to indicate call status
• Use DCD to establish connectivity
• Use TD and RD to transfer data, and
RTS and CTS to coordinate transfers
- 70. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
RS 422 Standard - Signals
- 71. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus Standard
• Connects one port to several devices
- 72. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Universal Serial Bus Standard
• Connects one port to several devices
• Transfers data in packets
– Token packets
– Data packets
– Handshake packets
– Special Packets
- 74. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Summary
• Asynchronous data transfers
• Programmed I/O
• Interrupts
• Direct Memory Access
• I/O Processors
• Serial Communication
• Serial Communication Standards