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- 1. Chapter 5 Differential and Multistage Amplifier
- 2. Outline <ul><li>Introduction </li></ul><ul><li>The CMOS Differential Pair </li></ul><ul><li>Small-Signal Operation of the MOS Differential Pair </li></ul><ul><li>The BJT Differential Pair </li></ul><ul><li>The differential Amplifier with Active Load </li></ul><ul><li>Frequency Response of the Differential amplifier </li></ul><ul><li>Multistage Amplifiers </li></ul>
- 3. Introduction <ul><li>Two reasons of the differential amplifier suited for IC fabrication: </li></ul><ul><ul><li>IC fabrication is capable of providing matched devices. </li></ul></ul><ul><ul><li>Utilizing more components than single-ended amplifier: </li></ul></ul><ul><ul><ul><li>Differential circuits are much less sensitive to noise and interference. </li></ul></ul></ul><ul><ul><ul><li>Differential configuration enable us to bias the amplifier and to couple amplifier stages without the need for bypass and coupling capacitors. </li></ul></ul></ul>
- 4. The MOS Differential Pair <ul><li>Basic structure of differential pair. </li></ul><ul><li>Characteristics </li></ul>
- 5. The MOS Differential Pair
- 6. Operation with a Common –Mode Input Voltage
- 7. Operation with a Common –Mode Input Voltage <ul><li>Symmetry circuit. </li></ul><ul><li>Common-mode voltage. </li></ul><ul><li>Current I divides equally between two transistors. </li></ul><ul><li>The difference between two drains is zero. </li></ul><ul><li>The differential pair rejects the common-mode input signals. </li></ul>
- 8. Operation with a Differential Input Voltage <ul><li>The MOS differential pair with a differential input signal v id applied. </li></ul><ul><li>With v id positive: v GS 1 v GS 2 , i D 1 i D 2 , and v D 1 v D 2 ; thus ( v D 2 v D 1 ) will be positive. </li></ul><ul><li>With v id negative: v GS 1 v GS 2 , i D 1 i D 2 , and v D 1 v D 2 ; thus ( v D 2 v D 1 ) will be negative. </li></ul>
- 9. Operation with a Differential Input Voltage <ul><li>Differential input voltage. </li></ul><ul><li>Response to the differential input signal. </li></ul><ul><li>The current I can be steered from one transistor to the other by varying the differential input voltage in the range: </li></ul><ul><li>When differential input voltage is very small, the differential output voltage is proportional to it, and the gain is high. </li></ul>
- 10. Large-Signal Operation <ul><li>Transfer characteristic curves </li></ul><ul><li>Normalized plots of the currents in a MOSFET differential pair. </li></ul><ul><li>Note that V OV is the overdrive voltage at which Q 1 and Q 2 operate when conducting drain currents equal to I /2. </li></ul>
- 11. Large-Signal Operation <ul><li>Nonlinear curves. </li></ul><ul><li>Maximum value of input differential voltage. </li></ul><ul><li>When v id = 0, two drain currents are equal to I/2. </li></ul><ul><li>Linear segment. </li></ul><ul><li>Linearity can be increased by increasing overdrive voltage(see next slide). </li></ul><ul><li>Price paid is a reduction in gain(current I is kept constant). </li></ul>
- 12. Large-Signal Operation The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of V OV .
- 13. Small-Signal Operation of MOS Differential Pair <ul><li>Linear amplifier </li></ul><ul><li>Differential gain </li></ul><ul><li>Common-mode gain </li></ul><ul><li>Common-mode rejection ratio(CMRR) </li></ul><ul><li>Mismatch on CMRR </li></ul>
- 14. Differential Gain <ul><li>a common-mode voltage applied to set the dc bias voltage at the gates. </li></ul><ul><li>v id applied in a complementary (or balanced) manner. </li></ul>
- 15. Differential Gain Signal voltage at the joint source connection must be zero.
- 16. Differential Gain An alternative way of looking at the small-signal operation of the circuit .
- 17. Differential Gain <ul><li>Differential gain </li></ul><ul><ul><li>Output taken single-ended </li></ul></ul><ul><ul><li>Output taken differentially </li></ul></ul><ul><ul><li>Advantages of output signal taken differentially </li></ul></ul><ul><ul><ul><li>Reject common-mode signal </li></ul></ul></ul><ul><ul><ul><li>Increase in gain by a factor of 2(6dB) </li></ul></ul></ul>
- 18. Differential Gain MOS differential amplifier with r o and R SS taken into account.
- 19. Differential Gain <ul><li>Equivalent circuit for determining the differential gain. </li></ul><ul><li>Each of the two halves of the differential amplifier circuit is a common-source amplifier, known as its differential “half-circuit.” </li></ul>
- 20. Differential Gain <ul><li>Differential gain </li></ul><ul><ul><li>Output taken single-ended </li></ul></ul><ul><ul><li>Output taken differentially </li></ul></ul>
- 21. Common-Mode Gain The MOS differential amplifier with a common-mode input signal v icm .
- 22. Common-Mode Gain <ul><li>Equivalent circuit for determining the common-mode gain (with r o ignored). </li></ul><ul><li>Each half of the circuit is known as the “common-mode half-circuit.” </li></ul>
- 23. Common-Mode Gain <ul><li>Common-mode gain </li></ul><ul><ul><li>Output taken single-ended </li></ul></ul><ul><ul><li>Output taken differentially </li></ul></ul>
- 24. Common-Mode Rejection Ratio <ul><li>Common-mode rejection ratio(CMRR) </li></ul><ul><ul><li>Output taken single-ended </li></ul></ul><ul><ul><li>Output taken differentially </li></ul></ul><ul><ul><li>This is true only when the circuit is perfectly matched. </li></ul></ul>
- 25. Mismatch on CMRR <ul><li>Effect of R D mismatch on CMRR </li></ul><ul><li>Effect of g m mismatch on CMRR </li></ul>
- 26. Mismatch on CMRR <ul><li>Determine the common-mode gain resulting from a mismatch in the g m values of Q 1 and Q 2 . </li></ul><ul><li>Common-mode half circuit is not available due to mismatch in circuit. </li></ul><ul><li>The nominal value g m . </li></ul>
- 27. Mismatch on CMRR <ul><li>Effect of g m mismatch on CMRR </li></ul>
- 28. The BJT Differential Pair <ul><li>Basic operation </li></ul><ul><li>Large-signal operation </li></ul><ul><li>Small-signal operation </li></ul><ul><ul><li>Differential gain </li></ul></ul><ul><ul><li>Common-mode gain </li></ul></ul><ul><ul><li>Common-mode rejection ration </li></ul></ul>
- 29. The BJT Differential Pair The basic BJT differential-pair configuration.
- 30. Basic Operation <ul><li>The differential pair with a common-mode input signal v CM . </li></ul><ul><li>Two transistors are matched. </li></ul><ul><li>Current source with infinite output resistance. </li></ul><ul><li>Current I divide equally between two transistors. </li></ul><ul><li>The difference in voltage between the two collector is zero. </li></ul><ul><li>The differential pair rejects the common-mode input signal as long as two transistors remain in active region. </li></ul>
- 31. Basic Operation <ul><li>The differential pair with a “large” differential input signal. </li></ul><ul><li>Q 1 is on and Q 2 is off. </li></ul><ul><li>Current I entirely flows in Q 1 . </li></ul>
- 32. Basic Operation <ul><li>The differential pair with a large differential input signal of polarity opposite to that in (b). </li></ul><ul><li>Q 2 is on and Q 1 is off. </li></ul><ul><li>Current I entirely flows in Q 2 . </li></ul>
- 33. Basic Operation <ul><li>The differential pair with a small differential input signal v i . </li></ul><ul><li>Small signal operation or linear amplifier. </li></ul><ul><li>Assuming the bias current source I to be ideal and thus I remains constant with the change in v CM . </li></ul><ul><li>Increment in Q 1 and decrement in Q 2 . </li></ul>
- 34. Large-Signal Operation
- 35. Large-Signal Operation <ul><li>Nonlinear curves. </li></ul><ul><li>Linear segments. </li></ul><ul><li>Maximum value of input differential voltages </li></ul><ul><li>Enlarge the linear segment by including equal resistance R e in series with the emitters. </li></ul>
- 36. Large-Signal Operation The transfer characteristics of the BJT differential pair (a) can be linearized by including resistances in the emitters.
- 37. Small Signal Operation The currents and voltages in the differential amplifier when a small differential input signal v id is applied.
- 38. Small Signal Operation A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal v id ; dc quantities are not shown.
- 39. Small Signal Operation <ul><li>A differential amplifier with emitter resistances. </li></ul><ul><li>Only signal quantities are shown (in color). </li></ul>
- 40. Input Differential Resistance <ul><li>Input differential resistance is finite. </li></ul><ul><li>The resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by (1+ β). </li></ul><ul><li>Input differential resistance of differential pair with emitter resistors. </li></ul>
- 41. Differential Voltage Gain <ul><li>Differential voltage gain </li></ul><ul><ul><li>Output voltage taken single-ended </li></ul></ul><ul><ul><li>Output voltage taken differentially </li></ul></ul>
- 42. Differential Voltage Gain <ul><li>Differential voltage gain of the differential pair with resistances in the emitter leads </li></ul><ul><ul><li>Output voltage taken single-ended </li></ul></ul><ul><ul><li>Output voltage taken differentially </li></ul></ul><ul><ul><li>The voltage gain is equal to the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit. </li></ul></ul>
- 43. Differential Half-Circuit Analysis <ul><li>Differential input signals. </li></ul><ul><li>Single voltage at joint emitters is zero. </li></ul><ul><li>The circuit is symmetric. </li></ul><ul><li>Equivalent common-emitter amplifiers in (b). </li></ul>
- 44. Differential Half-Circuit Analysis <ul><li>This equivalence applies only for differential input signals. </li></ul><ul><li>Either of the two common-emitter amplifiers can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier. </li></ul><ul><li>Half circuit is biased at I/2. </li></ul><ul><li>The voltage gain(with the output taken differentially) is equal to the voltage of half circuit. </li></ul>
- 45. Differential Half-Circuit Analysis <ul><li>The differential amplifier fed in a single-ended fashion. </li></ul><ul><li>Signal voltage at the emitter is not zero. </li></ul><ul><li>Almost identical to the symmetric one. </li></ul>
- 46. Common-Mode Gain The differential amplifier fed by a common-mode voltage signal v icm .
- 47. Common-Mode Gain Equivalent “half-circuits” for common-mode calculations.
- 48. Common-Mode Gain <ul><li>Common-mode voltage gain </li></ul><ul><ul><li>Output voltage taken single-ended </li></ul></ul><ul><ul><li>Output voltage taken differentially </li></ul></ul>
- 49. Common-Mode Rejection Ratio <ul><li>Common-mode rejection ratio </li></ul><ul><ul><li>Output voltage taken single-ended </li></ul></ul><ul><ul><li>Output voltage taken differentially </li></ul></ul><ul><ul><li>This is true only when the circuit is symmetric. </li></ul></ul><ul><li>Mismatch on CMRR </li></ul>
- 50. Input Common-Mode Resistance <ul><li>Definition of the input common-mode resistance R icm . </li></ul><ul><li>The equivalent common-mode half-circuit. </li></ul>
- 51. Input Common-Mode Resistance <ul><li>Input common-mode resistance </li></ul><ul><li>Input common-mode resistance is very large. </li></ul>
- 52. Example
- 53. Example (cont’d) <ul><li>Evaluate the following: </li></ul><ul><li>The input differential resistance. </li></ul><ul><li>The overall differential voltage gain(neglect the effect of r o ). </li></ul><ul><li>The worst-case common-mode gain if the two collector resistance are accurate within ±1%. </li></ul><ul><li>The CMRR, in dB. </li></ul><ul><li>The input common-mode resistance(suppose the Early voltage is 100V). </li></ul>
- 54. The Differential Amplifier with Active Load <ul><li>Replace resistance R D with a constant current source results in a much high voltage gain as well as saving in chip area. </li></ul><ul><li>Convert the output from differential to single-ended. </li></ul>
- 55. Differential-to-Single-Ended Conversion A simple but inefficient approach for differential to single-ended conversion.
- 56. The Active-Loaded MOS Differential Pair The active-loaded MOS differential pair.
- 57. The Active-Loaded MOS Differential Pair The circuit at equilibrium assuming perfect matching.
- 58. The Active-Loaded MOS Differential Pair The circuit with a differential input signal applied, neglecting the r o of all transistors.
- 59. Differential Gain of the Active-Loaded MOS Pair <ul><li>The output resistance r o plays a significant role in the operation of active-loaded amplifier. </li></ul><ul><li>Asymmetric circuit. </li></ul><ul><li>Half-circuit is not available. </li></ul><ul><li>The gain will be determined as G m R o </li></ul>
- 60. Short-Circuit Transconductance Determining the short-circuit transconductance G m = i o / v id
- 61. Short-Circuit Transconductance
- 62. Output Resistance Circuit for determining R o . The circled numbers indicate the order of the analysis steps.
- 63. Output Resistance <ul><li>Circuit for determining R o . </li></ul><ul><li>The circled numbers indicate the order of the analysis steps. </li></ul>
- 64. Differential Gain <ul><li>The differential gain is determined as G m R o </li></ul><ul><li>When </li></ul>
- 65. Common-Mode Gain and CMRR <ul><li>Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain. </li></ul><ul><li>Power supplies eliminated. </li></ul><ul><li>R ss is the output resistance of the current source. </li></ul>
- 66. Common-Mode Gain and CMRR <ul><li>Asymmetric circuit. </li></ul><ul><li>Each of the two transistors as a CS configuration with a large source degeneration resistance 2R ss. </li></ul><ul><li>Common-mode gain: </li></ul><ul><li>CMRR </li></ul>
- 67. The Bipolar Differential Pair with Active Load Active-loaded bipolar differential pair.
- 68. Determine the Transconductance
- 69. Determine the output Resistance
- 70. Differential Gain <ul><li>The differential gain is determined as G m R o </li></ul><ul><li>When </li></ul><ul><li>Input differential resistance </li></ul>
- 71. Common-Mode Gain and CMRR <ul><li>Common-mode gain: </li></ul><ul><li>CMRR </li></ul>
- 72. Frequency Response of the Resistively Loaded MOS Amplifier <ul><li>A resistively loaded MOS differential pair with the transistor supplying the bias current explicitly shown. </li></ul><ul><li>It is assumed that the total impedance between node S and ground, Z SS , consists of a resistance R SS in parallel with a capacitance C SS . </li></ul>
- 73. Frequency Response of the Resistively Loaded MOS Amplifier (b) Differential half-circuit. (c) Common-mode half-circuit.
- 74. Frequency Response of the Resistively Loaded MOS Amplifier common-mode gain
- 75. Frequency Response of the Resistively Loaded MOS Amplifier Differential Gain
- 76. Frequency Response of the Resistively Loaded MOS Amplifier CMRR with frequency.
- 77. Multistage Amplifier <ul><li>A four-stage bipolar op amplifier </li></ul><ul><li>A two-stage CMOS op amplifier </li></ul>
- 78. Multistage Amplifier
- 79. Multistage Amplifier <ul><li>The first stage(input stage) is differential-in, differential-out and consists of Q 1 and Q 2 . </li></ul><ul><li>The second stage is differential-in, single-ended-out amplifier which consists of Q 3 and Q 4 . </li></ul><ul><li>The third stage is CE amplifier which consists of pnp transistor Q 7 to shifting the dc level. </li></ul><ul><li>The last stage is the emitter follower. </li></ul><ul><li>Biasing stage. </li></ul>
- 81. Multistage Amplifier Equivalent circuit for calculating the gain of the input stage of the example. Input differential resistance Gain of first stage
- 82. Multistage Amplifier Equivalent circuit for calculating the gain of the second stage of the example. Gain of second stage
- 83. Multistage Amplifier Equivalent circuit for calculating the gain of the third stage of the example. Gain of third stage
- 84. Multistage Amplifier Equivalent circuit for calculating the gain of the output stage of the example. Gain of output stage Output resistance
- 85. Two-Stage CMOS Op-Amp Configuration

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