5

4

3

2

1

Pamirs-Discrete Block Diagram

SYSTEM DC/DC
TPS51120
OUTPUTS

INPUTS

Project code : 91.4S401.001
PCB P/N :...
A

B

C

D

E

INTEL ICH8-M STRAP PIN

19,21 +RTCVCC
4,5,6,7,9,10,11,19,21,37,47

+RTCVCC

Usage/When Sampled

HDA_SDOUT

...
5

3D3V_S0

4

3D3V_S0_CK505

3

2

1

L21

1

SCD1U16V2ZY-2GP

X1
CLK_XTAL_OUT

C332 SC4D7P50V2CN-1GP

1

1

C348
20

SC1...
5

4

3

2

1

XDP Connector
CN2
7

H_A#[3..35]
U62A 1 OF 4

19

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

...
5

4

3

7 H_D#[0..63]

2

1

VCC_CORE_S0
U62B 2 OF 4

VCC_CORE_S0
U62C
3 OF 4

3 CPU_BSEL0
3 CPU_BSEL1
3 CPU_BSEL2

CPU_B...
5

4

3

2

1

VCC_CORE_S0

2

1

C286
SC10U10V5KX-2GP

SC10U10V5KX-2GP

1

C288

2

SC10U10V5KX-2GP

1

C284
DY

2

2

1
...
B6
E5

H_RS#0
H_RS#1
H_RS#2

H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

E12
D7
D8

H_RS...
5

4

3

DDR_A_D[0..63]

1

13

DDR_A_BS[0..2]

2

13

DDR_B_D[0..63]

14

DDR_B_DM[0..7]

DDR_A_DM[0..7]

D

14

DDR_B_BS...
5

4

3

1D05V_S0

L41
L43
N41
N40
D46
C45
D44
E42

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK...
5

4

3

2

1

1D25V_S0_AXF
R412
1

1

C525

1
2

2
2

1

1
2

2

L46

C300

2

SSM5818SLPT-GP

1
2

1D25V_S0

1

C297 BLM...
5

4

3

2

1
1D05V_S0

1D05V_S0

LIB C
U23F 6 OF 10

A

SCD22U10V2KX-1GP

2

1

SC4D7U6D3V3KX-GP
2
1

1

C187
1
SC1U10V3K...
5

4

U23I

D

C

B

A

A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26...
5

4

3

2

8 DDR_A_DQS#[0..7]

DM2

1
2

2

TC5
ST220U2VBM-3GP

1

1
2

1

C224
SCD1U16V2ZY-2GP

2

1

C231
SCD1U16V2ZY-2...
5

4

3

2

1

8 DDR_B_DQS#[0..7]
8 DDR_B_D[0..63]
DM1
8 DDR_B_DM[0..7]
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
...
A

B

C

D

CRT I/F & CONNECTOR

E

5V_CRT_S0

5V_S0
F1

42

1

C13

2

FUSE-1D1A6V-8GP
SCD01U16V2KX-3GP

K

L8

1

VGA_RE...
LED / INVERTER INTERFACE

I=3.57 mA
5V_S5

R592

LED5

1

2

Q34

2CHG_LED#

1

C

LED-B-27-U-GP

255R2F-L-GP

R1

E

B

C...
B

C

5V_S0
D30

2
PR_INSERT

2
VOL_UP_DK# 3

DY

3

Docking Connector

5V_S0

D29

2

DY

VOL_DWN_DK#3

DOCK1

DY

1

1

...
5

4

3

PCI_AD[0..31]

24 PCI_AD[0..31]

PCI_FRAME#
PCI_GNT1#
PCI_REQ1#
PCI_REQ2#

8
7
6
5

SRN8K2J-4-GP
RN65

1
2
3
4

P...
5

4

3

2

1

+RTCVCC

3D3V_S0

LAN100_SLP
2
330KR2F-L-GP

ICH_INTVRMEN
2
330KR2F-L-GP

RN64

+RTCVCC
1
U32A OF 6

LPC_LA...
5

4

3

3D3V_S0

2

1

3D3V_S5

Place closely pin G5

Place closely pin AG9

RN48

PM_BMBUSY#

AG12

BMBUSY#/GPIO0

OCP#
...
5

4

3

2

1

+RTCVCC

20 mils
6
U32F OF 6
C611

1D05V_S0

SC1U10V3ZY-6GP

1D5V_S0_SATAPLL

AJ6

1

SCD1U16V2ZY-2GP

AC8
...
FAN1_VCC

5V_S0

K

1

D13
C151
SC10U10V5ZY-1GP

1

2

C162
SCD1U16V2ZY-2GP

2

1

*Layout* 15 mil

1N4148W-1-GP

A

R56
1...
IDE_PDD[0..15]

SATA HD Connector

CD-ROM CONNECTOR

3D3V_S0

CDROM_LED# 1
R518
INT_IRQ14

2
8K2R2J-3-GP

1

51

C681 1

4...
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Dv3

  1. 1. 5 4 3 2 1 Pamirs-Discrete Block Diagram SYSTEM DC/DC TPS51120 OUTPUTS INPUTS Project code : 91.4S401.001 PCB P/N :06230 Revision : SC Intel CPU Meron 2M/4M SV FSB:667 or 800 MHz CLK GEN D ICS9LPRS355A 5V_S3 DCBATOUT 3V_S5 SYSTEM DC/DC 4,5,6 INPUTS 3 RGB CRT CRT 1D05V_S0 DCBATOUT 1D8V_S3 LVDS DDRII Slot 0 533/667 13 DDRII 667 Channel A Crestline-GM/GML AGTL+ CPU I/F LVDS, CRT I/F 14 LCD SYSTEM DC/DC 14 FAN5234 nVIDIA INPUTS DDR I/F INTEGRATED GRAHPICS DDR II 667 Channel B Slot 1 OUTPUTS 13 Host BUS 533/667MHz DDRII 533/667 D MAX8743 SVIDEO PCIE x 16 NB8M-GS OUTPUTS VGA_CORE_S0 TVOUT 13 DCBATOUT 11A 38,39,40 7,8,9,10,11,12 MAXIM CHARGER MAX8725 C 1394 Ricoh R5C833 SD/SDIO/MMC MS/MS Pro/xD 25 18V 3.0A 100mA PCI CardReader BLUE TOOTH 32 INTEL 24,25 10/100 NIC Marvell 88E8039 LCI CPU DC/DC USB 2.0 USB x 3 23 INPUTS OUTPUTS 10 USB 2.0/1.1 ports 27 VCC_CORE ETHERNET (10/100/1000Mb) SATA HDD ODD DCBATOUT 23 PATA High Definition Audio 23 0.844~1.3V 44A ATA 66/100 ACPI 1.1 AMOM B RJ11 CONN 29 HD Audio MODEM CX20548 PCB LAYER LPC I/F PCI/PCI BRIDGE TPM SLB9635TT LPC Bus 18,19,20,21 L1: L2: L3: L4: L5: L6: L7: L8: L9: L10: 34 INTERNAL ARRAY MIC PCIE+USB 2.0 29 LINE OUT Ricoh R5538 SPDIF PCIE x 1 USB 2.0 x 1 MIC IN PCIE x 1 HD AUDIO CODEC CX20549-12Z KBC ENE KB3910SF 31 28 OP AMP APA2031 A New Card 30 28 Mini-Card 802.11a/b/g26 C MAX8736ETL ICH8-M RJ45 CONN 28 DCBATOUT CAMERA32 OUTPUTS BT+ 5V DMI I/F 100MHz 1394 25 INPUTS Mini-Card WWAN26 Capacity Button32 Touch Pad 32 Int. KB32 Thermal & Fan G792 22 CIR Flash ROM 1MB 33 Signal GND Signal Signal GND VCC Signal Signal GND Signal B 1 2 3 4 5 5 <Core Design> A Wistron Corporation 2CH SPEAKER 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DOCK CRT MIC IN LINE OUT S/PDIF TVOUT Title 10/100 Ethernet Block Diagram CIR Size A3 Document Number Rev Pamirs-Discrete Date: Monday, December 18, 2006 5 4 3 2 Sheet 1 1 SC of 47
  2. 2. A B C D E INTEL ICH8-M STRAP PIN 19,21 +RTCVCC 4,5,6,7,9,10,11,19,21,37,47 +RTCVCC Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config 1 bit1, Rising Edge of PWROK 4 HDA_SYNC PCIE Port Config 1 bit0, Rising Edge of PWROK. GNT2# PCIE Port Config 2 bit0, Rising Edge of PWROK. Comment Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h) XOR Chain Entrance Strap ICH_RSVD tp3 AZ_DOUT_ICH 0 0 1 1 0 1 0 1 1D05V_S0 3,7,10,21,38 1D25V_S0 Signal 1D05V_S0 1D25V_S0 27 1D2V_LAN_S5 1D2V_LAN_S5 28 1D5V_NEW_S0 Description RSVD Enter XOR Chain Normal Operation(default) Set PCIE port cofig bit1 1D5V_NEW_S0 5,10,17,19,20,21,26,28,38,47 7,10,11,13,14,34,37,38 GNT3# GNT0# SPI_CS1# INTVRMEN 3 Reserved Top-Block Swap Override. Rising Edge of PWROK. Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled. 2D5V_LAN_S5 3D3V_AUD_S0 Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap cycles targeting FWH BIOS space). PCI_GNT#3 low = A16 swap override enable Note: Software will not be able to clear the high = default Top-Swap bit until the system is rebooted without GNT3# being pulled down. BOOT BIOS Strap PCI_GNT#0 SPI_CS#1 BOOT BIOS Location Controllable via Boot BIOS Destination bit 0 1 SPI (Config Registers:Offset 3410h:bit 11:10). PCI 1 0 GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high 1 Enables integrated when sampled high PCIE LAN REVERSAL.Rising Edge of PWROK. This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8) SPKR No Reboot. Rising Edge of PWROK. If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5) TP3 XOR Chain Entrance. Rising Edge of PWROK. This signal should not be pull low unless using XOR Chain testing. GPIO33/ HDA_DOCK_EN# 3D3V_LAN_S5 3D3V_S0 17,18,20,21,22,26,27,28,29,31,34,36,39,47 22,26,29,31,34,36 3D3V_S0 3D3V_S5 3D3V_S5 5V_AUX_S5 16,23,32,33,34,36,37,38 5V_AUX_S5 5V_S3 5V_S3 5V_S0 5V_S0 16,21,34,37,40 5V_S5 5V_S5 15,16,17,20,21,22,23,29,30,31,32,33,34,35,47 LPC(Default) 17,39,46,47 AD+ 16,17,34,35,36,37,39,40,47 Low=Disable AD+ DCBATOUT DCBATOUT 13,14,38 DDR_VREF_S0 VccLAN1_05,VccCL1_05 VRM LAN100_SLP High=Enable Low=Disable DDR_VREF_S0 7,13,14,38 DDR_VREF_S3 DDR_VREF_S3 22,31,33,39 KBC_3D3V_AUX Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled. SATALED# 3D3V_AUX_S5 3,4,7,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,40,41,42,43,47 integrated VccSus1_05,VccSus1_5,VccCL1_5 SM_INTVRMEN High=Enable 3D3V_AUX_S5 27,28 3D3V_LAN_S5 integrated VccLan1_05VccCL1_05 LAN100_SLP 1D8V_S3 29,30 3D3V_AUD_S0 Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH. 4 1D5V_S0 1D8V_S3 27,28 2D5V_LAN_S5 Sets bit2 of RPC.PC(Config Registers:Offset 224h) 19,31,32,33,36,39,46 GPIO20 1D5V_S0 KBC_3D3V_AUX 16 DEFAULE HIGH LCDVDD_S0 3 LCDVDD_S0 5,6,35 VCC_CORE_S0 VCC_CORE_S0 No Reboot Strap SPKR LOW = Defaule High=No Reboot Internal Pull-Up.If sampled low,the Flash Descriptor Flash Descriptor Security Security will be overidden.if high,the Security Override Strap measures defined in the Flash Descriptor will be in 8.2K PULL HIGH Rising Edge of PWROK. effect. This should only be used in manufacturing environments INTEL ICH8-M INTEGRATED PULL-UPS and PULL-DOWNS SIGNAL Resistor Type/Value HDA_BIT_CLK PULL-DOWN 20K HDA_RST# NONE HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K HDA_SYNC PULL-DOWN 20K GNT[3:0] PULL-UP 20K GPIO[20] PULL-DOWN 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K CFG 20 Normal Operation ★ Reserved Lane Only PCIE or SDVO PCIE and SDVO are is operation ★ operation simultaneous PWRBTN# PULL-UP 20K SATALED# PULL-UP 20K SDVO_CTRL_DATA NO SDVO Card Present ★ SPI_CS1# PULL-UP 20K SPI_CLK PULL-UP 20K XOR/ALL-Z SPI_MOSI PULL-UP 20K Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation SPI_MISO PULL-UP 20K Wistron Corporation TACH_[3:0] PULL-UP 20K 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SPKR PULL-DOWN 20K TP[3] PULL-UP 20K USB[9:0][P,N] PULL-DOWN 15K CL_RST# TBD 2 INTEL CRESTLINE STRAP PIN CFG Strap CFG 5 CFG 8 Low Power PCI Express CFG 9 PCI Express Graphics Lane Reversal CFG 16 FSB Dynamic ODT CFG 19 DMI Lane Reserved Concurrent SDVO/PCIE LOW 0 DMI X 2 DMI X 4 ★ Normal ★ Low Power mode Lane Reversal Disabled SDVO Present 1 CFG 12 CFG 13 LL(00) LH(01) HL(10) HH(11) HIGH 1 Normal Mode(Lanes★ number in order) Enabled ★ SDVO Card Present 2 <Core Design> 1 Title Table of Content Size A3 Document Number Rev Pamirs-Discrete Date: Wednesday, November 01, 2006 Sheet 2 SA of 47
  3. 3. 5 3D3V_S0 4 3D3V_S0_CK505 3 2 1 L21 1 SCD1U16V2ZY-2GP X1 CLK_XTAL_OUT C332 SC4D7P50V2CN-1GP 1 1 C348 20 SC10U10V5ZY-1GP 2 1 C342 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C620 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SC1U10V3KX-3GP 2 1 C621 DY C614 2 1 C596 2 1 C354 2 1 2 MLB-160808-18-GP C601 2 1 1 CLK_XTAL_IN CLK_XTAL_OUT 3 2 1 FSA 2 R200 17 45 44 13,14,20 ICH_SMBCLK 13,14,20 ICH_SMBDATA 7 6 20 63 CK_PWRGD 19 27 43 52 33 56 CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 54 53 USB_48MHZ/FSLA SRCT6 SRCC6 48 47 SRCT10 SRCC10 41 42 SRCT11/CR#_H SRCC11/CR#_G 40 39 SRCT9 SRCC9 37 38 SRCT4 SRCC4 34 35 2 1 RN41 MCH_3GPLL 2 MCH_3GPLL# 1 SRCT3/CR#_C SRCC3/CR#_D 31 32 SRCT2/SATAT SRCC2/SATAC 28 29 PCIE_SATA PCIE_SATA# 2 1 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 24 25 27MHZ 27MHZSS 2 1 SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 REFCLKP REFCLKN 2 1 CK_PWRGD/PD# 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP PCI2_TME 27_SEL ITP_EN 2 15R2J-GP NC#55 18 15 1 C612 1 FS_B 0 0 1 1 FS_A 2 1 DY SRC8 CPU_ITP 1 1 0 1 100M 133M 200M 166M DY 5 CPU_BSEL2 R449 5 CPU_BSEL1 R203 5 CPU_BSEL0 R201 1 2 1 2 1 2 FSC 10KR2J-3-GP 2 SA 1011 3 4 3 4 3 4 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19 SRN0J-6-GP SRN33J-5-GP-U VGA_27MHZ 43 VGA_27MHZSS 43 PEG_REFCLKP 41 PEG_REFCLKN 41 SRN0J-6-GP B 27_SEL FSB R184 10KR2J-3-GP 27_SEL 0 1 PIN 20 PIN 21 DOT96T SRCT0 DOT96C SRCC0 PIN 24 PIN 25 SRCT1/LCDT_100 27M_NSS SRCT1/LCDT_100 27M_SS 0R2J-2-GP FSA 2K2R2J-2-GP R191 1 2 1KR2J-1-GP MCH_CLKSEL0 7 R174 1 A CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20 R183 10KR2J-3-GP 2 0 1 ITP_EN SRN0J-6-GP RN32 CPU R448 10KR2J-3-GP R447 10KR2J-3-GP CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 1 C313 1 2 1 0 0 0 3D3V_S0_CK505 Output SRN0J-6-GP 3D3V_S0_CK505 FS_C ITP_EN 3 4 C CLK_PCIE_MINI2 26 CLK_PCIE_MINI2# 26 ICS9LPRS355AKLFT-GP SC4D7P50V2CN-1GP C315 1 2 SC4D7P50V2CN-1GP R454 10KR2J-3-GP 2 DY SC4D7P50V2CN-1GP C316 1 2 SC4D7P50V2CN-1GP 2 1 B PCI2_TME SC4D7P50V2CN-1GP 1 C314 1 2 1 2 3D3V_S0_CK505 R453 10KR2J-3-GP 3 4 RN34 GND 1 RN42 R227 1 DY 2 10KR2J-3-GP 3 4 SRN0J-6-GP CLK_PCIE_NEW 28 CLK_PCIE_NEW# 28 3D3V_S0 NEWCARD_CLKREQ# 28 65 R450 GND48 GNDPCI GNDREF CLK_14M_ICH FSLB/TEST_MODE REF0/FSLC/TEST_SEL 55 20 64 5 CLK_PCIE_MINI1 26 CLK_PCIE_MINI1# 26 3 4 SRN0J-6-GP 1 2 R228 10KR2J-3-GP RN37 FSB FSC 2 2 2 2 2 2 CLK_PCIE_LAN 27 CLK_PCIE_LAN# 27 4 SRN0J-6-GP 3 1 DY GND GNDSRC GNDSRC GNDSRC GNDCPU GND 1 1 1 1 1 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN PCIE_MINI2 PCIE_MINI2# CLK_CPU_XDP 4 CLK_CPU_XDP# 4 SA 1011 4 SRN0J-6-GP 3 PCIE_ICH RN40 2 PCIE_ICH# 1 SCLK SDATA CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 4 SRN0J-6-GP 3 DY 1 2 RN39 PCIE_MINI1 1 PCIE_MINI1# 2 RN45 PCIE_NEW 2 PCIE_NEW# 1 RN43 51 50 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 4 SRN0J-6-GP 3 PCIE_LAN PCIE_LAN# SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP# 22 30 36 49 59 26 R185 R192 R193 R195 R194 8 10 11 12 13 14 4 SRN0J-6-GP 3 1 2 RN30 MCH_BCLK 1 MCH_BCLK# 2 RN33 CPU_XDP 1 CPU_XDP# 2 RN36 58 57 SA 1011 20 CLKSATAREQ# 7 CLKREQ#_B 33 PCLK_FWH 34 CLK_PCI_TCG 31 PCLK_KBC 18 CLK_PCI_ICH 24 PCLK_PCM CPU_BCLK CPU_BCLK# 61 60 CPUT1_F CPUC1_F 33R2J-2-GP H_STP_PCI# H_STP_CPU# C CPUT0 CPUC0 X1 X2 2 CLK_48M_ICH 20 20 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO 1D25V_S0_CK505 L49 2 D C327 SC18P50V2JN-1-GP U28 VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 1D25V_S0 C328 SC18P50V2JN-1-GP 4 16 9 46 62 23 2 X-14D31818M-40GP 2 1 1 CLK_XTAL_IN 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP D 1D25V_S0_CK505 C600 1 C595 2 1 C630 2 1 3D3V_S0_CK505 2 1 DY C597 2 1 C594 SCD1U16V2ZY-2GP 2 DY C603 SCD1U16V2ZY-2GP SC10U10V5ZY-1GP 2 1 C337 2 1 2 SC1U10V3KX-3GP 2 1 1 MLB-160808-18-GP C639 2 1KR2J-1-GP MCH_CLKSEL1 7 R445 1 2 1KR2J-1-GP MCH_CLKSEL2 7 <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Design Note: 1. All of Input pin didn't have internal pull up resistor. 2. Clock Request (CR) function are enable by registers. 3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic. Title Size A3 Clock generator CY28548 Document Number Rev Pamirs-Discrete Date: Tuesday, December 19, 2006 Sheet 3 SC of 47
  4. 4. 5 4 3 2 1 XDP Connector CN2 7 H_A#[3..35] U62A 1 OF 4 19 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TP13 TP16 TP7 TP9 TP5 TP10 TP6 TP18 TP8 TP17 A6 A5 C4 D5 C6 B4 A3 TPAD28 TP4 CPU_RSVD11 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1 RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# G6 E4 H_HIT# H_HITM# BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# XDP_BPM#0 AD4 XDP_BPM#1 AD3 XDP_BPM#2 AD1 XDP_BPM#3 AC4 XDP_BPM#4 AC2 XDP_BPM#5 AC1 XDP_TCK AC5 XDP_TDI AA6 XDP_TDO AB3 XDP_TMS AB5 XDP_TRST# AB6 C20 XDP_DBRESET# CONTROL 1 H_LOCK# H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 H_BR0# H_INIT# 7 THERMTRIP# HCLK BCLK0 BCLK1 XDP_BPM#3 XDP_BPM#2 R156 56R2J-4-GP XDP_BPM#1 XDP_BPM#0 2 H4 PROCHOT# THRMDA THRMDC STPCLK# LINT0 LINT1 SMI# CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10 H_IERR# H_INIT# BR0# XDP_BPM#5 XDP_BPM#4 19 H_LOCK# 7 H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 5 H_PWRGOOD_R C7 1 R164 A22 CLK_CPU_BCLK A21 CLK_CPU_BCLK# XDP_TCK 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 NP1 61 2 62 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 63 64 NP2 D 1218 H_RESET#_R R57 1 DY XDP_DBRESET#_R 1 DY R55 XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE 2 68R3J-GP 2 1KR2F-3-GP 2 200R2F-L-GP 1 R64 1D05V_S0 H_RESET# XDP_DBRESET# CLK_CPU_XDP 3 CLK_CPU_XDP# 3 2 0R0402-PAD (Place R1431 with in 200ps (~1") to CPU STC-CONN60A-GP-U1 H_THERMDA H_THERMDC H_THERMTRIP# C120 SCD1U16V2KX-3GP XDP_DBRESET# 20 CPU_PROCHOT# D21 A24 B25 XDP_HOOK1 1D05V_S0 H_HIT# 7 H_HITM# 7 THERMAL A20M# FERR# IGNNE# H_SMI# H_A20M# H_FERR# H_IGNNE# D20 B3 HIT# HITM# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# IERR# INIT# RESET# RS0# RS1# RS2# TRDY# ICH 19 19 19 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 H_BR0# LOCK# ADDR GROUP 1 H_ADSTB#1 19 19 19 REQ0# REQ1# REQ2# REQ3# REQ4# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 C 7 K3 H2 K2 J3 L1 F1 7 7 7 1 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_DEFER# H_DRDY# H_DBSY# DEFER# DRDY# DBSY# H_ADS# H_BNR# H_BPRI# 1 1D05V_S0 2 7 7 7 7 7 H5 F21 E1 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 H1 E2 G5 H_ADS# H_BNR# H_BPRI# RESERVED 7 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 D J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP 0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 0630 Connector Vendor :SmaTec Part Number : QSH-030-01-F-D-TR 35 1D05V_S0 C H_THERMDA 22 H_THERMDC 22 H_THERMTRIP# 7,19 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 layout note:Zo =55 ohm , 0.5" MAX for GTLREF layout note : Change R237 to 649 ohm if using XTP to ITP adapter 3D3V_S0 R59 KEY_NC XDP_DBRESET# 1 BGA479-SKT6-GPU3 2 1KR2J-1-GP 1D05V_S0 original value:BGA479-SKT6-GPU1 XDP_TDI R61 XDP_TMS B R60 XDP_TDO R63 XDP_BPM#5 R89 XDP_HOOK1 R75 1 2 1 2 1 2 1 2 1 2 54D9R2F-L1-GP B 54D9R2F-L1-GP 54D9R2F-L1-GP 54D9R2F-L1-GP 54D9R2F-L1-GP DY XDP_TRST# R58 1D05V_S0 XDP_TCK 2 1 2 51R2F-2-GP 54D9R2F-L1-GP 1 R74 1 R165 56R2J-4-GP B 2 DY CPU_PROCHOT# E C DY Q10 OCP# 20 MMBT3904WT1G-GP A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(1/3)-AGTL+/XDP Size Custom Date: Document Number Rev SC Pamirs-Discrete Tuesday, December 19, 2006 Sheet 4 of 47
  5. 5. 5 4 3 7 H_D#[0..63] 2 1 VCC_CORE_S0 U62B 2 OF 4 VCC_CORE_S0 U62C 3 OF 4 3 CPU_BSEL0 3 CPU_BSEL1 3 CPU_BSEL2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 B22 B23 C21 COMP0 COMP1 COMP2 COMP3 E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# PSI# R171 R172 R132 R131 1 1 1 1 2 2 27D4R2F-L1-GP 2 54D9R2F-L1-GP 2 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSTP# 7,19 H_DPSLP# 19 H_DPWR# 7 H_PWRGOOD 19 H_CPUSLP# 7 PSI# 35 R145 BGA479-SKT6-GPU3 PLACE C173 make sure routing is away other close to the TEST4 PIN, TEST3,TEST4,TEST5 trace reference to GND and noisy signals 166 200 CPU_BSEL2 0 0 CPU_BSEL1 2 H_PWRGOOD_R 4 1KR2J-1-GP B CPU_BSEL 1 Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils . CPU_BSEL0 1 1 1 0 D 1D05V_S0 R155 1 R146 1 C 2 2 0R2J-2-GP 0R2J-2-GP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA VCCA B26 C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 VCCSENSE AF7 VCC_SENSE VSSSENSE AE7 VSS_SENSE BGA479-SKT6-GPU3 TC7 1 DATA GRP2 R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7 AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 DY 1D5V_S0 layout note: place C3 near PIN B26 C298 VCC_SENSE VSS_SENSE CPU_VID[0..6] 35 VCC_SENSE 35 VSS_SENSE 35 1 2 R143 100R2F-L1-GP-U 1 DY MISC H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 2 TPAD28 TP3 TPAD28 TP21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SCD01U16V2KX-3GP 2 C296 1 AD26 C23 D25 C24 AF26 AF1 A26 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 2 V_CPU_GTLREF TPAD28 TP19 TPAD28 TP22 TPAD28 TP20 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 1 SCD1U16V2KX-3GP H_DSTBN#1 H_DSTBP#1 H_DINV#1 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 SE330U2VDM-6-GP 7 7 7 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# DATA GRP1 DATA GRP1 C N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# 2 H_DSTBN#0 H_DSTBP#0 H_DINV#0 DATA GRP3 7 7 7 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP0 DATA GRP0 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 C303 SC10U10V5ZY-1GP Length match within 25 mils . The trace width/space/other is 20/7/25 . B VCC_CORE_S0 1 2 R142 100R2F-L1-GP-U Close to CPU pin within 500mils SCD01U16V2KX-3GP R423 2KR2F-3-GP C602 1 V_CPU_GTLREF <Core Design> 2 1 1 R422 1KR2F-3-GP 2 A Close to CPU pin AD26 Z0=55 ohm with in 500mils . 2 1D05V_S0 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(2/3)-AGTL+/PWR Size A3 Document Number Rev SC Pamirs-Discrete Date: Tuesday, December 19, 2006 Sheet 5 of 47
  6. 6. 5 4 3 2 1 VCC_CORE_S0 2 1 C286 SC10U10V5KX-2GP SC10U10V5KX-2GP 1 C288 2 SC10U10V5KX-2GP 1 C284 DY 2 2 1 C277 SC10U10V5KX-2GP SC10U10V5KX-2GP 1 C274 DY 2 SC10U10V5KX-2GP 1 C271 2 2 1 C263 SC10U10V5KX-2GP 1 2 Place these capacitors on L1 (North side ,Secondary Layer) D VCC_CORE_S0 SC10U10V5KX-2GP 1 C259 2 SC10U10V5KX-2GP 1 C278 2 SC10U10V5KX-2GP 1 C269 2 SC10U10V5KX-2GP 1 C287 2 SC10U10V5KX-2GP 1 C267 DY 2 2 1 C275 SC10U10V5KX-2GP 1 2 Place these capacitors on L1 (North side ,Secondary Layer) SC10U10V5KX-2GP C281 C Mid Frequencd Decoupling B 2 C292 SCD1U16V2KX-3GP 1 2 C293 SCD1U16V2KX-3GP 1 2 C247 SCD1U16V2KX-3GP 1 C249 SCD1U16V2KX-3GP 1 C246 SCD1U16V2KX-3GP 2 1D05V_S0 2 B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 1 C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 D 4 OF 4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 U62D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 SC10U10V5KX-2GP C252 C291 SCD1U16V2KX-3GP Place these inside socket cavity on L1 (North side Secondary) BGA479-SKT6-GPU3 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(3/3)-GND&Bypass Size A3 Document Number Rev SC Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 6 of 47
  7. 7. B6 E5 H_RS#0 H_RS#1 H_RS#2 H_CPURST# H_CPUSLP# H_AVREF H_DVREF H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 2 1 R400 2 10KR2J-3-GP CLKREQ#_B 1 R399 2 10KR2J-3-GP TP49 TP54 TP51 TP55 TP56 TP48 TP52 TP50 TP57 CFG16 TP47 TP46 TP45 From Astro demo schematic 4 4 4 4 4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 TP53 CFG[17:3] have internal pull up CFG[19:18] have internal pull down CFG18 CFG19 CFG20 4 4 4 CRESTLINE-GP-U layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces 20 PM_BMBUSY# 5,19 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 4,19 H_THERMTRIP# 20,35 DPRSLPVR R112 1 20,22 PM_PWROK 20,35 VGATE_PWRGD 1D05V_S0 R114 1 DY PM_POK_R 2 2 0R2J-2-GP 1 1 2 H_SWNG SA 0928 2 1 1 1 Layout Note : Place C151 within 100 mils of NB R163 100R2F-L1-GP-U 2 SCD1U16V2ZY-2GP 1 2 2 A R168 24D9R2F-L-GP 2 2 1 C290 H_RCOMP C295 SCD1U16V2ZY-2GP SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3 BG20 DDR_CS0_DIMMA# BK16 DDR_CS1_DIMMA# BG16 DDR_CS2_DIMMB# BE13 DDR_CS3_DIMMB# DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# 13 13 14 14 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_RCOMP SM_RCOMP# BL15 BK14 SM_RCOMP SM_RCOMP# SM_VREF#AR49 SM_VREF#AW4 AR49 AW4 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# M_ODT0 M_ODT1 M_ODT2 M_ODT3 D 13 13 14 14 1D8V_S3 1 R154 1 R413 2 2 20R2F-GP 20R2F-GP DDR_VREF_S3 DDR_VREF_S3 B42 C42 H48 H47 PEG_CLK PEG_CLK# K44 CLK_MCH_3GPLL K45 CLK_MCH_3GPLL# DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AN47 AJ38 AN42 AN46 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AJ46 AJ41 AM40 AM44 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#0 PM_EXT_TS#1 PWROK RSTIN# THERMTRIP# DPRSLPVR 1 R597 2 2K2R2J-2-GP BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 NC#BJ51 NC#BK51 NC#BK50 NC#BL50 NC#BL49 NC#BL3 NC#BL2 NC#BK1 NC#BJ1 NC#E1 NC#A5 NC#C51 NC#B50 NC#A50 NC#A49 NC#BK2 NC NC R157 2KR2F-3-GP R162 221R2F-2-GP H_VREF G41 L39 L36 J36 AW49 AV20 N20 G36 13 13 14 14 13 13 14 14 AJ47 AJ42 AM39 AM43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 20 20 20 20 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 20 20 20 20 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 20 20 20 20 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 20 20 20 20 C 2D5V_S0 R401 R402 2K2R2J-2-GP 2K2R2J-2-GP DY DY ICH_SDVO_DATA ICH_SDVO_CLK GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN E35 A39 C38 B39 E36 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 DFGT_VID0 DFGT_VID1 DFGT_VID2 DFGT_VID3 DFGT_VR_EN TP44 TP11 TP15 TP12 TP14 B 1D25V_S0 0R2J-2-GP 1D05V_S0 R158 1KR2F-3-GP PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST_R# H_THERMTRIP# DPRSLPVR P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB SM_RCOMP_VOH SM_RCOMP_VOL PM PM B Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 BE29 DDR_CKE0_DIMMA AY32 DDR_CKE1_DIMMA BD39 DDR_CKE2_DIMMB BG37 DDR_CKE3_DIMMB CLK PM_EXTTS#1 SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 1 2 SCD01U25V2KX-3GP 2 C266 2 10KR2J-3-GP M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 1 5 5 5 5 H_RS#0 H_RS#1 H_RS#2 1 R407 AW30 M_CLK_DDR#0 BA23 M_CLK_DDR#1 AW25 M_CLK_DDR#2 AW23 M_CLK_DDR#3 1 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4 DDR MUXING 1 SCD01U25V2KX-3GP 1 2 1 2 C257 SC2D2U10V3ZY-1GP 2 1 C253 5 5 5 5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 PM_EXTTS#0 13 13 14 14 2 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 M14 E13 A11 H13 B12 3D3V_S0 RSVD#H10 RSVD#B51 RSVD#BJ20 RSVD#BK22 RSVD#BF19 RSVD#BH20 RSVD#BK18 RSVD#BJ18 RSVD#BF23 RSVD#BG23 RSVD#BC23 RSVD#BD24 RSVD#BJ29 RSVD#BE24 RSVD#BH39 RSVD#AW20 RSVD#BK20 RSVD#C48 RSVD#D47 RSVD#B44 RSVD#C44 RSVD#A35 RSVD#B37 RSVD#B36 RSVD#B34 RSVD#C34 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 DDR_A_MA14 DDR_B_MA14 3 MCH_CLKSEL0 3 MCH_CLKSEL1 3 MCH_CLKSEL2 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 AV29 BB23 BA25 AV23 2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 L7 K2 AC2 AJ10 R149 1KR2F-3-GP 13 DDR_A_MA14 14 DDR_B_MA14 5 5 5 5 SM_CK0 SM_CK1 SM_CK3 SM_CK4 CL_CLK0 20 CL_DATA0 20 2 VGATE_PWRGD 20,35 0R2J-2-GP CL_RST# 20 CLPWROK_MCH 1 R410 CL_VREF R115 1KR2F-3-GP 1 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 RSVD#P36 RSVD#P37 RSVD#R35 RSVD#N35 RSVD#AR12 RSVD#AR13 RSVD#AM12 RSVD#AN13 RSVD#J12 RSVD#AR37 RSVD#AM36 RSVD#AL36 RSVD#AM37 RSVD#D20 DMI M7 K3 AD2 AH11 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 R147 1KR2F-3-GP M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 1 H_VREF H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_SCOMP H_SCOMP# B9 A9 H_RESET# H_CPUSLP# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 FOR Calero: 80.6 ohm Crestline: 20 ohm U23B 2 OF 10 1D8V_S3 R148 3K01R2F-3-GP SM_RCOMP_VOL 1 R116 392R2F-GP C193 SDVO_CTRL_CLK SDVO_CTRL_DATA CLKREQ# ICH_SYNC# TEST1 TEST2 H35 K36 G39 G40 ICH_SDVO_CLK ICH_SDVO_DATA TP43 TP42 CLKREQ#_B 3 MCH_ICH_SYNC# MCH_ICH_SYNC# A37 TEST1_GMCH R32 TEST2_GMCH 1 R406 2 20 1 2 R144 0R2J-2-GP CFG9 2 H_SWING H_RCOMP K5 L2 AD13 AE13 SM_RCOMP_VOH 2 1 4 5 H_RESET# H_CPUSLP# B3 C2 W1 W2 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 3 4 SCD1U16V2KX-3GP 2 H_SCOMP H_SCOMP# H_ADS# G12 H_ADSTB#0 H17 H_ADSTB#1 G20 H_BNR# C8 H_BPRI# E8 H_BR0# F12 H_DEFER# D6 H_DBSY# C10 CLK_MCH_BCLK AM5 CLK_MCH_BCLK# AM7 H_DPWR# H8 H_DRDY# K7 H_HIT# E4 H_HITM# C6 H_LOCK# G10 H_TRDY# B7 H_A#[3..35] GRAPHICS VID 2 H_SWNG H_RCOMP 4 CFG CFG 54D9R2F-L1-GP 1 R178 54D9R2F-L1-GP 2 1 R179 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 ME 1D05V_S0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 MISC C H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1 D E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 RSVD RSVD H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C270 SC2D2U10V3ZY-1GP 1 2 U23A 1 OF 10 5 H_D#[0..63] HOST 5 20KR2J-L2-GP CRESTLINE-GP-U Layout Note : Place C153 near pin B3 of NB 1 R598 ICH_SDVO_DATA 2 2K2R2J-2-GP A <Core Design> R414 PLT_RST_R# 1 2 Wistron Corporation PLT_RST1# 18,20,26,28,31,33,34,41 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 100R2J-2-GP Title CRESTLINE(1/6)-AGTL+/DMI/DDR2 Size Document Number Custom Date: Monday, December 11, 2006 Sheet 7 Rev SA Pamirs-Discrete of 47
  8. 8. 5 4 3 DDR_A_D[0..63] 1 13 DDR_A_BS[0..2] 2 13 DDR_B_D[0..63] 14 DDR_B_DM[0..7] DDR_A_DM[0..7] D 14 DDR_B_BS[0..2] 14 13 DDR_A_DQS[0..7] DDR_B_DQS[0..7] DDR_A_DQS#[0..7] B A BB19 BK19 BF29 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SA_CAS# BL17 DDR_A_CAS# SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 CRESTLINE-GP-U 14 U23E 5 OF 10 SA_BS0 SA_BS1 SA_BS2 DDR SYSTEM MEMORRY A C SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 SA_RAS# SA_RCVEN# BE18 AY20 DDR_A_RAS# SA_RCVEN# SA_WE# BA19 DDR_A_WE# DDR_A_CAS# 13 DDR_A_RAS# 13 TP58 DDR_A_WE# 13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_BS0 SB_BS1 SB_BS2 AY17 BG18 BG36 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_CAS# BE17 DDR_B_CAS# SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 DDR SYSTEM MEMORY B U23D 4 OF 10 AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 14 13 DDR_B_MA[0..13] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 14 13 DDR_B_DQS#[0..7] DDR_A_MA[0..13] D 13 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 SB_RAS# SB_RCVEN# AV16 AY18 DDR_B_RAS# SB_RCVEN# BC17 DDR_B_WE# SB_WE# DDR_B_CAS# 14 C DDR_B_RAS# DDR_B_WE# B 14 14 TP59 CRESTLINE-GP-U <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRESTLINE(2/6)-DDR2 A/B CH Size A3 Document Number Rev SA Pamirs-Discrete Date: Wednesday, October 18, 2006 Sheet 8 of 47
  9. 9. 5 4 3 1D05V_S0 L41 L43 N41 N40 D46 C45 D44 E42 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK G51 E51 F49 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 G50 E50 F48 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 E44 A47 A45 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 C TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL0 TV_DCONSEL1 TV E27 G27 K27 B CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# K33 G35 E33 C32 F33 CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC VGA H32 G32 K29 J29 F29 E29 N43 M43 PEGCOMP trace width and spacing is 20/25 mils. PEGCOMP PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 G44 B47 B45 PEG_COMPI PEG_COMPO PCI_EXPRESS GRAPHICS D L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS J40 H39 E39 E40 C37 D35 K40 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_RXN15 41 PEG_RXN14 41 PEG_RXN13 41 PEG_RXN12 41 PEG_RXN11 41 PEG_RXN10 41 PEG_RXN9 41 PEG_RXN8 41 PEG_RXN7 41 PEG_RXN6 41 PEG_RXN5 41 PEG_RXN4 41 PEG_RXN3 41 PEG_RXN2 41 PEG_RXN1 41 PEG_RXN0 41 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 M45 TXP0 T38 TXP1 T46 TXP2 N50 TXP3 R51 TXP4 U43 TXP5 W42 TXP6 Y47 TXP7 Y39 TXP8 AC38 TXP9 AD47 TXP10 AC50 TXP11 AD43 TXP12 AG39 TXP13 AE50 TXP14 AH43 TXP15 C489 C506 C480 C195 C196 C502 C499 C487 C512 C491 C494 C189 C486 C482 C191 C483 C490 C507 C479 C194 C197 C501 C500 C488 C515 C492 C495 C190 C485 C481 C192 C484 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved CFG[2:0] FSB Freq select CFG5 (DMI select) PEG_RXP15 41 PEG_RXP14 41 PEG_RXP13 41 PEG_RXP12 41 PEG_RXP11 41 PEG_RXP10 41 PEG_RXP9 41 PEG_RXP8 41 PEG_RXP7 41 PEG_RXP6 41 PEG_RXP5 41 PEG_RXP4 41 PEG_RXP3 41 PEG_RXP2 41 PEG_RXP1 41 PEG_RXP0 41 N45 TXN0 U39 TXN1 U47 TXN2 N51 TXN3 R50 TXN4 T42 TXN5 Y43 TXN6 W46 TXN7 W38 TXN8 AD39 TXN9 AC46 TXN10 AC49 TXN11 AC42 TXN12 AH39 TXN13 AE49 TXN14 AH44 TXN15 1 Strap Pin Table 1 2 R398 24D9R2F-L-GP U23C 3 OF 10 2 0 = DMI x 2 1 = DMI x 4 CFG6 D Reserved 0 = Reserved 1 = Mobile CPU CFG7 (CPU Strap) * 0 = Normal mode 1 = Low Power mode CFG8 (Low power PCIE) CFG9 (PCIE Graphics Lane Reversal) * 0 = Reverse Lane 1 = Normal Operation CFG[11:10] * Reserved 00 01 10 11 CFG[13:12] (XOR/ALLZ) CFG[15:14] = = = = Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation (Default)* Reserved 0 = Disable 1 = Enable * CFG16 (FSB Dynamic ODT) PEG_TXP15 41 PEG_TXP14 41 PEG_TXP13 41 PEG_TXP12 41 PEG_TXP11 41 PEG_TXP10 41 PEG_TXP9 41 PEG_TXP8 41 PEG_TXP7 41 PEG_TXP6 41 PEG_TXP5 41 PEG_TXP4 41 PEG_TXP3 41 PEG_TXP2 41 PEG_TXP1 41 PEG_TXP0 41 * CFG[18:17] C Reversed SDVO_CTRLDATA 0 = No SDVO Device Present * 1 = SDVO Device Present 0 = Normal Operation (Lane number in Order) 1 = Reverse lane CFG19(DMI Lane Reversal) * 0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu. CFG20(PCIE/SDVO consurrent) PEG_TXN15 41 PEG_TXN14 41 PEG_TXN13 41 PEG_TXN12 41 PEG_TXN11 41 PEG_TXN10 41 PEG_TXN9 41 PEG_TXN8 41 PEG_TXN7 41 PEG_TXN6 41 PEG_TXN5 41 PEG_TXN4 41 PEG_TXN3 41 PEG_TXN2 41 PEG_TXN1 41 PEG_TXN0 41 B CRESTLINE-GP-U <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(3/6)-VGA/LVDS/TV Document Number Rev SA Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 9 of 47
  10. 10. 5 4 3 2 1 1D25V_S0_AXF R412 1 1 C525 1 2 2 2 1 1 2 2 L46 C300 2 SSM5818SLPT-GP 1 2 1D25V_S0 1 C297 BLM18AG121SN-1GP 3D3V_S0_HV R128 2 2 2 SC10U10V5KX-2GP 1 1 2 1 1 C302 1D05V_S0_D D15 1D05V_S0 1 0R5J-5-GP 0R5J-5-GP B L20 1D05V_S0 R87 SC10U10V5KX-2GP 1 DY 2 1D25V_S0 1D25V_S0 R403 1 2 1 0R2J-2-GP 1 C301 TC3 ST220U2VBM-3GP C299 TC15 2 2 20mil C176 2 C573 BLM18AG121SN-1GP 1D25V_S0_MPLL 2 10R2J-2-GP 3D3V_S0 2 CRESTLINE-GP-U 2 1 HV 2 A7 F2 AH1 VTTLF1 VTTLF2 VTTLF3 R91 1 1 VCCD_LVDS VCCD_LVDS AH50 AH51 1D05V_S0_PEG 2 J41 H42 VTTLF VTTLF VTTLF 1D05V_S0_PEG ST220U2VBM-3GP VCCD_PEG_PLL VCC_RXR_DMI VCC_RXR_DMI AD51 W50 W51 V49 V50 SCD47U16V3ZY-3GP 1D25V_S0_PEGPLL C SC10U10V5KX-2GP C522 VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG 1 VCCD_HPLL U48 C40 B40 1 AN2 VCC_HV VCC_HV SCD47U16V3ZY-3GP 2 1D25V_S0_HPLL SCD22U16V3ZY-GP 1 1 2 1 1 2 2 SC4D7U6D3V3KX-GP 1 2 1 C575 A43 1 VCCD_QDAC 2 1D5V_S0 0R5J-5-GP C537 1 SCD47U16V3ZY-3GP 2 N28 TV/CRT VCCD_CRT VCCD_TVDAC 1D8V_S3 R176 1D25V_S0_HPLL 1 SM CK A SM 1D25V_S0_AXF SCD1U16V2ZY-2GP M32 L29 2 1D8V_S3_SM_CK VTTLF VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC PEG VCCA_SM_CK VCCA_SM_CK A CK BC29 BB29 C536 2 A PEG 2 VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK AXF 1D25V_S0_DMI BK24 BK23 BJ24 BJ23 BLM18PG121SN-1GP D 0R5J-5-GP 1 3D3V_S0_HV C25 B25 C27 B27 B28 A28 1D5V_S0_TVDAC AJ50 VCC_TX_LVDS TV 1 1 2 VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF DMI 1 SC1U10V3KX-3GP SCD22U16V3ZY-GP 2 AT22 AT21 AT19 AT18 AT17 AR17 AR16 LVDS 2 SC4D7U25V5KX-GP 1 ST22U6D3VBM-1GP 2 C538 C535 SC1U10V3KX-3GP 2 SCD22U16V3ZY-GP 2 1 C533 C555 B23 B21 A21 SCD1U16V2ZY-2GP B C528 C560 SCD1U16V2ZY-2GP 2 1 2 DY 1 DY 1 1D25V_S0_SM_CK C580 SC10U10V5KX-2GP VCC_AXF VCC_AXF VCC_AXF VCC_DMI VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM C203 C550 1D25V_S0 SCD1U16V2ZY-2GP 0R3-0-U-GP C579 2 TC9 ST100U4VBM-U 1 DY SC1U10V3KX-3GP 2 1 2 2 0R5J-5-GP R173 1 1D25V_S0_A_SM R177 1 AW18 AV19 AU19 AU18 AU17 VCCA_PEG_PLL C185 2 SCD1U16V2ZY-2GP 1D25V_S0 U51 AR29 C540 1D5V_S0_TVDAC L17 1 SCD022U16V2KX-3GP 20mil 1D25V_S0_PEGPLL VCC_AXD_NCTF 1D25V_S0_PEGPLL C546 SC10U10V5KX-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C C202 SCD1U16V2ZY-2GP C549 DY C542 2 0R5J-5-GP 1D25V_S0 R117 1 1D25V_S0 0R3-0-U-GP 1 VSSA_PEG_BG 1D25V_S0 R175 1 2 2 K49 1 0R3-0-U-GP 1D25V_S0_AXD AT23 AU28 AU24 AT29 AT25 AT30 1D8V_S3_SM_CK 2 VCCA_PEG_BG 2 VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD C198 1 K50 2 R107 1 POWER C565 2 VSSA_LVDS SC1KP50V2KX-1GP 3D3V_S0_PEG_BG 1D25V_S0_DMI R105 1 SC2D2U6D3V3MX-1-GP VCCA_LVDS B41 C517 3D3V_S0 SC4D7U6D3V3KX-GP VCCA_MPLL A41 1D8V_S0_TXLVDS SC1U10V3KX-3GP AM2 AXD VCCA_HPLL 1D25V_S0_MPLL PLL AL2 A LVDS VCCA_DPLLB 1D25V_S0_HPLL C520 2 0R3-0-U-GP C548 SC1U16V3ZY-GP SCD1U16V2ZY-2GP VCCA_DPLLA C521 SCD1U16V2ZY-2GP B49 H49 C547 SC10U10V5KX-2GP 1 VSSA_DAC_BG TC17 2 VCCA_DAC_BG B32 DY 2 A30 U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 1 VCCA_CRT_DAC VCCA_CRT_DAC VTT A33 B33 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT SCD47U16V3ZY-3GP 2 1 VCC_SYNC 2 J32 CRT D 1 ST220U2VBM-3GP SCD22U16V3ZY-GP U23H 8 OF 10 1 1D05V_S0 C518 SCD1U16V2KX-3GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(4/6)-PWR Document Number Rev SA Pamirs-Discrete Date: Thursday, December 14, 2006 Sheet 10 of 47
  11. 11. 5 4 3 2 1 1D05V_S0 1D05V_S0 LIB C U23F 6 OF 10 A SCD22U10V2KX-1GP 2 1 SC4D7U6D3V3KX-GP 2 1 1 C187 1 SC1U10V3KX-3GP 2 SC1U10V3KX-3GP C186 C188 1 SCD47U16V3ZY-3GP 2 C576 1 SCD22U10V2KX-1GP C559 2 1 CRESTLINE-GP-U SCD22U10V2KX-1GP 2 VCC GFX NCTF 2 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 C567 1 1 2 AW45 BC39 BE39 BD17 BD4 AW8 AT6 2 1 2 1 2 VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF B SCD1U16V2ZY-2GP 1 10R2J-2-GP VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG C568 1 2 C557 SC10U10V5KX-2GP R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 1 R408 K SC10U10V5KX-2GP C551 D C545 C 2 D33 A 2 1 2 3D3V_S0 TC20 C553 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP 1D05V_S0 1 1D05V_S0 VCC SM LF 1 1 SC22U6D3V5MX-2GP 2 1 2 SC22U6D3V5MX-2GP 2 1D05V_S0 CRESTLINE-GP-U CH751H-40PT-1GP 2 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC SM 2 2 2 2 2 2 AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC GFX DY DY DY DY DY DY ST220U2VBM-3GP 1 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 1 R166 1 R167 1 R169 1 R170 1 R113 1 R120 SC1U10V3KX-3GP C558 VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM MCHGND1 MCHGND2 MCHGND3 MCHGND4 MCHGND5 MCHGND6 ST220U2VBM-3GP VSS NCTF VCC NCTF VSS SCB A3 B2 C1 BL1 BL51 A51 VSS AXM NCTF 1 2 1 VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB 2 1 2 1 1 2 2 1 2 DY SCD1U16V2ZY-2GP 1 TC4 C556 2 POWER 1D8V_S3 C524 SCD01U16V2KX-3GP C531 C529 C532 C527 C552 0R3-0-U-GP T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 SCD1U16V2ZY-2GP VCC R409 1 C261 B T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 POWER 1D05V_S0 AL24 AL26 AL28 C563 AM26 C566 AM28 SC10U10V5KX-2GP AM29 SC10U10V5KX-2GP AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF C530 C VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VSS AXM 1 2 1 1 1 2 2 SC22U6D3V5MX-2GP 2 SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP ST220U2VBM-3GP 2 C543 C544 C544 C534 TC8 C574 1 D AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC CORE 2VCC_GMCH1 R30 U23G 7 OF 10 1D05V_S0 VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF SCD1U16V2ZY-2GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C539 AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRESTLINE(5/6)-PWR/GND Document Number Size Custom Rev SA Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 11 of 47
  12. 12. 5 4 U23I D C B A A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 9 OF 10 VSS CRESTLINE-GP-U 2 U23J VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 1 10 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS VSS VSS VSS VSS VSS VSS VSS AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 D C VSS B CRESTLINE-GP-U <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(6/6)-PWR/GND Document Number Rev SA Pamirs-Discrete Date: Wednesday, October 18, 2006 Sheet 12 of 47
  13. 13. 5 4 3 2 8 DDR_A_DQS#[0..7] DM2 1 2 2 TC5 ST220U2VBM-3GP 1 1 2 1 C224 SCD1U16V2ZY-2GP 2 1 C231 SCD1U16V2ZY-2GP 2 1 C242 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C217 SCD1U16V2ZY-2GP SC2D2U16V5ZY-2GP 2 1 C272 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS DDR_VREF_S0 1 C227 C255 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C216 2 1 C241 2 1 C204 2 1 C519 2 1 C523 2 1 C514 2 1 DY C516 2 1 C509 2 1 DY 2 1 C511 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 DY C498 2 C503 SCD1U16V2ZY-2GP 2 1 DY B Layout Note: Place these resistors closely DM1,all trace length Max=1.5" DDR_VREF_S0 SRN56J-4-GP DDR_A_BS2 1 DDR_CKE0_DIMMA 2 RN55 SRN56J-4-GP DDR_A_MA7 4 1 DDR_A_MA6 3 2 11 29 49 68 129 146 167 186 RN58 SRN56J-4-GP 1 4 2 3 4 3 RN11 SRN56J-4-GP DDR_A_MA12 1 DDR_A_MA9 2 DDR_A_MA10 DDR_A_BS0 RN20 SRN56J-4-GP 1 4 2 3 4 3 RN56 SRN56J-4-GP DDR_A_MA4 1 DDR_A_MA2 2 13 31 51 70 131 148 169 188 DDR_A_WE# DDR_CS1_DIMMA# RN23 SRN56J-4-GP 1 4 2 3 4 3 RN57 SRN56J-4-GP DDR_A_MA0 1 DDR_A_BS1 2 M_ODT1 DDR_A_CAS# RN26 SRN56J-4-GP 1 4 2 3 4 3 RN59 SRN56J-4-GP M_ODT0 1 DDR_A_MA13 2 RN53 SRN56J-4-GP DDR_CKE1_DIMMA 1 4 2 3 4 3 RN54 SRN56J-4-GP 1 DDR_A_MA14 DDR_A_MA11 2 DDR_VREF_S3 7 7 M_ODT0 M_ODT1 DDR_VREF_S3 114 119 DDR_CKE0_DIMMA 7 DDR_CKE1_DIMMA 7 30 32 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 7 M_CLK_DDR#0 7 164 166 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 7 M_CLK_DDR#1 7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 OTD0 OTD1 1 2 SC2D2U16V5ZY-2GP DDR_CKE0_DIMMA DDR_CKE1_DIMMA CK1 CK1# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DDR_CS0_DIMMA# 7 DDR_CS1_DIMMA# 7 79 80 CK0 CK0# DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DDR_CS0_DIMMA# DDR_CS1_DIMMA# 10 26 52 67 130 147 170 185 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 ICH_SMBDATA ICH_SMBCLK SDA SCL 195 197 VDDSPD 199 SA0 SA1 198 200 NC#50 NC#69 NC#83 NC#120 NC#163/TEST 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD DDR_A_RAS# 8 DDR_A_WE# 8 DDR_A_CAS# 8 D 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 ICH_SMBDATA 3,14,20 ICH_SMBCLK 3,14,20 SCD1U16V2ZY-2GP R416 1 R417 1 2 10KR2J-3-GP 2 10KR2J-3-GP 3D3V_S0 C569 PM_EXTTS#0 7 C571 SC2D2U6D3V3KX-GP 1D8V_S3 VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 202 GND GND 201 MH1 MH1 MH2 MH2 C B 1 DDR_A_RAS# DDR_CS0_DIMMA# C76 C82 2 RN17 SRN56J-4-GP 1 4 2 3 1 DDR_A_MA3 DDR_A_MA1 A RN8 4 3 2 DDR_A_MA8 DDR_A_MA5 RN13 SRN56J-4-GP 1 4 2 3 110 115 CKE0 CKE1 DY C262 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 DY C251 2 1 C238 SC2D2U16V5ZY-2GP C SC2D2U16V5ZY-2GP 2 1 DY C213 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_ODT0 M_ODT1 1D8V_S3 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 7 DDR_A_MA14 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# CS0# CS1# BA0 BA1 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 8 DDR_A_BS[0..2] Layout Note: Place near DM1 107 106 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 8 DDR_A_MA[0..13] 108 109 113 1 DDR_A_BS0 DDR_A_BS1 8 DDR_A_DQS[0..7] RAS# WE# CAS# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 DDR_A_BS2 8 DDR_A_DM[0..7] 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 1 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 2 8 DDR_A_D[0..63] D 1 A <Core Design> SCD1U16V2ZY-2GP Wistron Corporation DDR2-200P-20-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDRII-SODIMM SLOT1 Size Custom Document Number Rev Pamirs-Discrete Date: Wednesday, October 18, 2006 5 4 3 2 Sheet 13 1 SA of 47
  14. 14. 5 4 3 2 1 8 DDR_B_DQS#[0..7] 8 DDR_B_D[0..63] DM1 8 DDR_B_DM[0..7] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA0 DDR_B_BS1 SRN56J-4-GP 1 4 2 3 4 3 RN22 DDR_CS2_DIMMB# DDR_B_RAS# SRN56J-4-GP 1 4 2 3 4 3 RN24 DDR_B_WE# DDR_B_CAS# SRN56J-4-GP 1 4 2 3 4 3 RN27 DDR_CS3_DIMMB# M_ODT3 1 2 RN9 DDR_B_MA14 SRN56J-4-GP 4 3 SRN56J-4-GP 1 4 2 3 DDR_B_MA12 DDR_B_MA9 RN7 RN14 198 200 NC#50 NC#69 NC#83 NC#120 NC#163/TEST 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 RN16 RN25 GND 201 MH1 MH2 MH2 1 2 1 SRN56J-4-GP M_ODT2 1 DDR_B_MA13 2 RN6 SRN56J-4-GP DDR_B_BS2 1 DDR_CKE2_DIMMB 2 DDR_VREF_S3 7 7 M_ODT2 M_ODT3 DDR_VREF_S3 SC2D2U16V5ZY-2GP SCD1U16V2ZY-2GP R420 1 R421 1 2 10KR2J-3-GP 2 10KR2J-3-GP 3D3V_S0 3D3V_S0 C578 PM_EXTTS#1 7 C577 SC2D2U6D3V3KX-GP C 1D8V_S3 B A 1 1 C77 2 C71 2 ICH_SMBDATA 3,13,20 ICH_SMBCLK 3,13,20 1 GND SRN56J-4-GP DDR_B_MA4 1 DDR_B_MA2 2 D 2 VREF VSS SRN56J-4-GP DDR_B_MA7 1 DDR_B_MA6 2 SRN56J-4-GP A SA0 SA1 OTD0 OTD1 SRN56J-4-GP DDR_B_MA5 1 DDR_B_MA8 2 RN12 4 3 VDDSPD 1 2 SRN56J-4-GP DDR_CKE3_DIMMB 1 DDR_B_MA11 2 4 3 ICH_SMBDATA ICH_SMBCLK 114 119 2 1 2 1 2 1 2 1 2 1 2 1 2 195 197 199 DDR_B_RAS# 8 DDR_B_WE# 8 DDR_B_CAS# 8 1 1 2 1 1 2 2 2 1 1 1 2 1 4 3 RN19 DDR_B_MA10 DDR_B_BS0 RN10 4 3 SDA SCL M_ODT2 M_ODT3 SCD1U16V2ZY-2GP SRN56J-4-GP 1 4 2 3 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP RN21 DDR_B_MA3 DDR_B_MA1 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 C225 Layout Note: Place these resistors closely DM2,all trace length Max=1.5" DDR_VREF_S0 SRN56J-4-GP 1 4 2 3 M_CLK_DDR3 7 M_CLK_DDR#3 7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# C183 B RN18 M_CLK_DDR3 M_CLK_DDR#3 11 29 49 68 129 146 167 186 C215 SCD1U16V2ZY-2GP 2 1 C237 SCD1U16V2ZY-2GP 2 1 C243 SCD1U16V2ZY-2GP 2 1 C235 SCD1U16V2ZY-2GP 2 1 C226 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 C265 164 166 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SCD1U16V2ZY-2GP C234 M_CLK_DDR2 7 M_CLK_DDR#2 7 CK1 CK1# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DY C207 M_CLK_DDR2 M_CLK_DDR#2 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DY C184 30 32 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_VREF_S0 C256 DDR_CKE2_DIMMB 7 DDR_CKE3_DIMMB 7 CK0 CK0# BA0 BA1 C C245 CKE0 CKE1 107 106 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS DY DDR_CS2_DIMMB# 7 DDR_CS3_DIMMB# 7 DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 C221 SCD1U16V2ZY-2GP 2 1 C170 SCD1U16V2ZY-2GP 2 1 C513 SCD1U16V2ZY-2GP 2 1 C232 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 1 C497 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 C244 DDR_CS2_DIMMB# DDR_CS3_DIMMB# 79 80 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DY C508 110 115 DDR_B_BS0 DDR_B_BS1 7 DDR_B_MA14 C541 CS0# CS1# C264 1D8V_S3 DY DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS2 8 DDR_B_BS[0..2] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 Layout Note: Place near DM2 108 109 113 DY 8 DDR_B_MA[0..13] D RAS# WE# CAS# 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 8 DDR_B_DQS[0..7] 202 MH1 <Core Design> Wistron Corporation SCD1U16V2ZY-2GP DDR2-200P-21-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDRII-SODIMM SLOT2 Size Custom Date: 5 4 3 2 Document Number Rev Pamirs-Discrete Wednesday, October 18, 2006 Sheet 1 14 SA of 47
  15. 15. A B C D CRT I/F & CONNECTOR E 5V_CRT_S0 5V_S0 F1 42 1 C13 2 FUSE-1D1A6V-8GP SCD01U16V2KX-3GP K L8 1 VGA_RED CRT_R 2 CRT_R CH751H-40PT-1GP D4 5V_CRT1_S0 4 17 1 2 4 1 A 2 Layout Note: Place these resistors close to the CRT-out connector BLM18BB470SN1-GP L2 CRT_B 17 17 13 JVGA_HS 14 JVGA_VS DDC_CLK_CON 15 DY 3 U3 GMCH_HSYNC 1 C15 SC33P50V2JN-3GP DY DY 5 3 SC22P50V2JN-4GP 2 8 C9 CRT_G 4 6 C20 C11 SC33P50V2JN-3GP DY SC22P50V2JN-4GP 1 1 20.20424.015 5V_CRT1_S0 2 2 5V_CRT1_S0 7 3 DDC_DATA_CON 12 1 1 1 1 CRT_B 11 16 2 DDC_DATA_CON 7 2 8 3 9 4 10 5 CRT_G 2 2 2 2 D11 C21 SC10P50V2JN-4GP Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN. C26 SC10P50V2JN-4GP SC10P50V2JN-4GP SC10P50V2JN-4GP 2 C32 2 BLM18BB470SN1-GP 2 C22 6 1 CRT_R CRT_B 2 1 1 C29 SC10P50V2JN-4GP SC10P50V2JN-4GP SC10P50V2JN-4GP 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP 2 C35 R19 2 R20 1 1 1 1 BLM18BB470SN1-GP L1 R23 SRN2K2J-1-GP CRT1 17 4 3 CRT_G 2 42 VGA_BLUE 1 CRT_G 2 1 1 2 42 VGA_GREEN RN1 1 3 BAV99W-1-GP D12 CRT_R 2 Hsync & Vsync level shift DDC_CLK_CON GMCH_VSYNC DY 3 3D3V_S0 CRT_B PACDN009MR-GP-U 1 4 3 5V_S0 3D3V_S0 RN2 SRN2K2J-1-GP C464 SCD1U16V2ZY-2GP PR_INSERT 17 1 14 1 2 2 1 BAV99W-1-GP 2 5 17,42 GMCH_VSYNC 3 7 4 14 17,42 GMCH_HSYNC U6A HSYNC_5 U1 TSAHCT125PW-GP RN4 VSYNC_5 6 2 1 2 4 3 JVGA_HS JVGA_VS 4 7 SRN33J-5-GP-U U6B TSAHCT125PW-GP DDC_CLK_CON 17 DDC_CLK_CON 3 5 42 VGA_DDCDATA 6 DDC_DATA_CON 2 1 DDC_DATA_CON 17 2 VGA_DDCCLK 42 2N7002DW-1-GP TV OUT CONN L32 C432 C431 BLM18BB470SN1-GP TV_LUMA TV_CRMA TV_COMP 2 2 LUMA CRMA COMP NC#5 2 4 6 7 5 SC10P50V2JN-4GP 1 3 8 9 2 BAV99W-1-GP DY D3 3D3V_S0 2 VGA_TV_LUMA TV_COMP 17 3 SC10P50V2JN-4GP 2 2 1 SC10P50V2JN-4GP 1 3D3V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. VGA_TV_CRMA C438 C437 BLM18BB470SN1-GP 3 1 Title C2 SCD1U16V2ZY-2GP DY SC10P50V2JN-4GP BAV99W-1-GP 2 SC10P50V2JN-4GP 1 TV_LUMA 17 2 2 2 1 2 Wistron Corporation 2 1 1 42 VGA_TV_LUMA 1 <Core Design> DY D2 R2 150R2F-1-GP C3 SCD1U16V2ZY-2GP DY BAV99W-1-GP L34 Place this 2 resistors close to the TV-out connector C1 SCD1U16V2ZY-2GP DY 1 1 GND GND GND GND 1 2 2 1 NC#2 C434 C433 BLM18BB470SN1-GP 2 1 R3 150R2F-1-GP VGA_TV_COMP 3 MINDIN7-16-GP-U L33 1 1 TV1 1 1 1 TV_CRMA 17 SC10P50V2JN-4GP 42 VGA_TV_COMP 5V @ ext. CRT side 2 2 1 1 42 VGA_TV_CRMA 2 connector R1 150R2F-1-GP 3D3V_S0 D1 B C Document Number Rev Pamirs-Discrete Date: Friday, November 24, 2006 DY A CRT/TV Connector Size A3 D Sheet E 15 SA of 47
  16. 16. LED / INVERTER INTERFACE I=3.57 mA 5V_S5 R592 LED5 1 2 Q34 2CHG_LED# 1 C LED-B-27-U-GP 255R2F-L-GP R1 E B CHG_LED 31 LCD/INV CONN R2 PDTC124EU-1-GP 5V_S3 I=3.57 mA LED4 C R1 E B LCDVDD_S0 PWR_LED 31 PWR_LED# C453 SC10U10V5ZY-1GP 5V_S0 14 U68C LED1 8 10 CAPS_LED 31 42 42 7 BRIGHTNESS_CONN 3D3V_S0 K 1 5V_S0 2 R489 1 5 1 3 2 BLON_OUT DCBATOUT 1 2 C456 C454 C455 4 255R2F-L-GP SCD1U16V2ZY-2GP TP_LED 31 LED3 2 A LED-O-16-GP 6 31 R231 LED2 U35 LDDC_CLK LDDC_DATA 1 TSAHCT08PWR-1GP SCD1U25V2ZY-U 2 2 LED-B-27-U-GP 1 1 255R2F-L-GP 2 2 9 1 1 42 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 C458 SCD1U16V2ZY-2GP 2 R141 3D3V_S0 LCD1 5V_S0 I=3.57 mA 5V_S0 R2 PDTC124EU-1-GP 1 LED-B-27-U-GP 2 2 255R2F-L-GP 33 Q33 1 1 2 2 R591 1 SCD1U16V2ZY-2GP 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 40 41 VGA_TXACLK- 42 VGA_TXACLK+ 42 VGA_TXAOUT0- 42 VGA_TXAOUT0+ 42 VGA_TXAOUT1- 42 VGA_TXAOUT1+ 42 VGA_TXAOUT2- 42 VGA_TXAOUT2+ 42 VGA_TXBCLK- 42 VGA_TXBCLK+ 42 VGA_TXBOUT0- 42 VGA_TXBOUT0+ 42 VGA_TXBOUT1- 42 VGA_TXBOUT1+ 42 VGA_TXBOUT2- 42 VGA_TXBOUT2+ 42 1 ACES-CONN40C-GP-U LED-B-27-U-GP 255R2F-L-GP 20.F0813.040 2N7002DW-1-GP 3D3V_S0 1 5V_S0 5V_S0 R596 14 R569 10KR2J-3-GP LED6 2 1 1 MEDIA_LED# 2 3 2 0R2J-2-GP R343 4 3 7 TSAHCT08PWR-1GP RN52 SRN2K2J-1-GP 1 2 LDDC_DATA LED7 A 2 BRIGHTNESS 31 DY 1 0R2J-2-GP LBKLT_CRTL 42 R346 100KR2J-1-GP DY LDDC_CLK 4 K 6 5 1 C452 1 C450 MS_LED# 25 LED-B-67-GP-U2 7 255R2F-L-GP 2 1 2 U68B 14 NC I=3.6 mA R545 1 1 5V_S0 5V_S0 BRIGHTNESS_CONN SATA_LED# 19 LED-B-27-U-GP 255R2F-L-GP R344 3D3V_S0 CDROM_LED# 23 2 1 U68A 2 I=3.57 mA TSAHCT08PWR-1GP BLON_OUT 2 SC1000P50V3JN-GP BRIGHTNESS_CONN 2 SCD1U16V2ZY-2GP 3D3V_S0 Layout 40 mil LCDVDD_S0 5V_S3 2 U55 2 R330 100KR2J-1-GP IN#1 OUT EN GND GND IN#8 IN#7 IN#6 IN#5 2 1 BC1 SC1U10V3ZY-6GP SCD1U16V2ZY-2GP 2 1 G5281RC1U-GP EC47 9 8 7 6 5 U56 R329 10KR2J-3-GP DY DY 1 1 2 3 4 LCDVDD_EN 1 42 1 LCDVDD_S0 LCDVDD_EN 1 R347 DY 2 100R2J-2-GP 6 2 5 3 4 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2N7002DW-1-GP Title LCD/Inverter Connector Size Custom Document Number Date: Tuesday, December 19, 2006 Rev Pamirs-Discrete Sheet 16 of SA 47
  17. 17. B C 5V_S0 D30 2 PR_INSERT 2 VOL_UP_DK# 3 DY 3 Docking Connector 5V_S0 D29 2 DY VOL_DWN_DK#3 DOCK1 DY 1 1 BAV99W-1-GP BAV99W-1-GP AD+ 15 CRT_R 15 CRT_G 15 CRT_B 15 DDC_DATA_CON 15 DDC_CLK_CON 1 2 28 RJ45-7 28 28 14 10 HSYNC_5_1 7 13 14 DOCK_IN# 12 15,42 GMCH_VSYNC U6C RJ45-4 RJ45-6 RJ45-3 RJ45-2 RJ45-1 28 28 DOCK_IN# 31 8 DCBATOUT TSAHCT125PW-GP RN3 1 2 VSYNC_5_1 11 1 SA C90 SCD1U16V2ZY-2GP 28 9 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 DOCK_HS DOCK_VS USB_7USB_7+ 5V_S0 15,42 GMCH_HSYNC 43 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 BAV99W-1-GP 4 4 3 AD+ 46 NP2 44 1 Hsync & Vsync level shift E 1 5V_S0 D10 D 42 NP1 45 DOCK_HS DOCK_VS AD+ EC45 SCD1U25V3ZY-1GP 2 A 4 TV_LUMA 15 TV_CRMA 15 TV_COMP 15 CIR_PR PWR_ON EAPD#_1 R78 PWR_BTN# 31 R76 JACK_DETECT# 29 VOL_UP_DK# 31 VOL_DWN_DK# 31 SPDIF_DOCK 1 1 2 EAPD# 32 2 0R2J-2-GP MUTE_LED# 31,32 0R2J-2-GP DY AUD_AGND DK_SPKR_R_1 DK_SPKR_L_1 DK_MIC_R_CN_1 DK_MIC_L_CN_1 AUD_AGND DOCK_PRESENT 1 EC80 1 EC23 1 EC15 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 1 EC26 1 EC18 CIR_PR 1 EC54 PWR_ON 1 EC19 VOL_UP_DK# 1 EC52 VOL_DWN_DK# 1 EC22 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SC100P50V2JN-3GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP AUD_AGND 41 EAPD# SRN33J-5-GP-U 7 U6D TSAHCT125PW-GP FOX-CONN40-1-GP-U1 DOCK_PRESENT 20.B0045.040 3 PWR_BTN# R371 1 CIR CIR_PR 1 R369 1D5V_S0 2 0R2J-2-GP 2 0R2J-2-GP CIR_SENSE 31 1 29 1 5V_S0 2 0R0402-PAD R94 USB_7+ USB20_P7 Q24 CH3904PT-GP R389 29,41 1 SPDIF 2 1 R90 2 SPDIF_DOCK 1 2 BLM18PG600SN-2GP EC58 SC470P50V2KX-3GP DY EC59 SC470P50V2KX-3GP 2 0R0402-PAD 2 2N7002DW-1-GP DK_SPKR_R 1 L40 DK_SPKR_R_1 2 0R3-0-U-GP 1 1 EC56 SC100P50V2JN-3GP 2 PR_INSERT 29 DK_MIC_R_CN 2 29 1 1 5V_S0 R53 10KR2J-3-GP 15 E 1 USB_7- USB20_N7 1 L39 DY 2 4 R355 100KR2J-1-GP 20 2 5 2 2 6 2 3 2 33R2J-2-GP 1 1 1 R353 DY R390 220R2J-L2-GP 1 2 L-63UH-GP DOCK_IN# 31 DOCK_PRESENT B 330R2J-3-GP TR1 U9 2 2 R351 10KR2J-3-GP 3 4 1 20 C 2 R387 33R3J-2-GP 3 1 L18 EC24 2 DK_MIC_R_CN_1 0R3-0-U-GP SC100P50V2JN-3GP 3D3V_S5 1 1 1 L19 2 DK_MIC_L_CN_1 0R3-0-U-GP EC25 SC100P50V2JN-3GP E U15 C D Q21 CH3906PT-GP 1 R365 3 2 1KR2J-1-GP Q23 2N7002-11-GP G PWR_ON Place near Dock connector Place near Codec 1 BAS40CW-GP R366 10KR2J-3-GP S0 = 4V S3 = 2.5V S5 = 0V <Core Design> 1 Wistron Corporation 2 PM_SLP_S4# 29 DK_MIC_L_CN EC60 SC100P50V2JN-3GP 2 2 B 22KR2J-GP 1 2 R377 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S 20,28,31,36,37,38 DK_SPKR_L_1 2 0R3-0-U-GP 5V_S0 R378 22KR2J-GP 1 1 L41 2 1 DK_SPKR_L 2 29 3D3V_S5 Title Board to board conn/ Docking Size A3 Document Number Rev A B C D SA Pamirs-Discrete Date: Friday, November 24, 2006 Sheet E 17 of 47
  18. 18. 5 4 3 PCI_AD[0..31] 24 PCI_AD[0..31] PCI_FRAME# PCI_GNT1# PCI_REQ1# PCI_REQ2# 8 7 6 5 SRN8K2J-4-GP RN65 1 2 3 4 PCI_GNT3# PCI_REQ3# PCI_SERR# PCI_PIRQG# 8 7 6 5 SRN8K2J-4-GP RN68 1 2 3 4 PCI_GNT#0 PCI_PIRQA# PCI_PLOCK# PCI_PERR# 8 7 6 5 1 2 3 4 1 2 3 4 SRN8K2J-4-GP RN67 PCI_IRDY# 8 7 PCI_TRDY# 6 PCI_PIRQE# PCI_PIRQD# 5 1 2 3 4 C SRN8K2J-4-GP RN69 8 PCI_PIRQH# PCI_PIRQC# 7 PCI_PIRQB# 6 5 PCI_REQ#0 D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# RN61 1 2 3 4 F9 B5 C5 A10 PIRQA# PIRQB# PIRQC# PIRQD# SRN8K2J-4-GP RN63 8 PCI_PIRQF# 7 PCI_GNT2# 6 PCI_DEVSEL# 5 PCI_STOP# 24 PCI_PIRQA# 24 1 3 U32C OF 6 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 3D3V_S0 D 2 PCI_PIRQC# REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 GNT3#/GPIO55 REQ3#/GPIO54 A4 D7 E18 C18 B19 F18 C10 A11 C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 IRDY# PAR PCIRST# DEVSEL# PERR# FRAME# PLOCK# SERR# STOP# TRDY# C8 D9 G6 D16 A7 A17 B7 F10 C16 C9 PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_FRAME# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PLTRST# PCICLK PME# AG24 B10 G7 PCI_PLTRST# CLK_PCI_ICH PCI PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_GNT3# PCI_REQ3# PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 TP78 D TP80 TP90 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 R486 1 Interrupt I/F PCI_REQ#0 24 PCI_GNT#0 24 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# 24 24 24 24 PCI_IRDY# 24 PCI_PAR 24 PCI_DEVSEL# 24 PCI_PERR# 24 PCI_FRAME# 24 PCI_SERR# 24,31 PCI_STOP# 24 PCI_TRDY# 24 CLK_PCI_ICH 3 ICH_PME# 24 8K2R2J-3-GP 2 3D3V_S5 1218 C ICH8-M-1-GP-U 3D3V_S5 U43A 14 SRN8K2J-4-GP PCI_PCIRST# 1 3 PCIRST1# 24,27 1 2 SSLVC08APWR-GP 1 7 PCI_GNT3# R257 100KR2J-1-GP 1KR2J-1-GP 1 R255 0R2J-2-GP DY 2 2 Boot BIOS Strap DY B PCI_GNT0# SPI_CS#1 2 R236 B Boot BIOS Location 3D3V_S5 SPI 1 0 PCI 1 A16 swap override Strap 1 U43B 4 6 Low= A16 swap override Enable High= Default * LPC * 3D3V_S5 PCI_GNT#0 2 R260 1 0R2J-2-GP DY 1KR2J-1-GP DY 1 1 1 DY 2 R465 10KR2J-3-GP 2 DY PCI_PLTRST# 23 2 R237 R235 10R2J-2-GP SC8P250V2CC-GP SSLVC08APWR-GP R264 100KR2J-1-GP 1 CLK_PCI_ICH C357 PLT_RST1# 7,20,26,28,31,33,34,41 1 2 Place closely pin B10 A PLT_RST1# 5 7 PCI_GNT3# PCI_PLTRST# 2 1 14 0 20 SPI_CS1# SPI_CS1# <Core Design> DY A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(1/4)-PCI/INT Size A3 Document Number Date: Monday, December 18, 2006 5 4 3 2 Rev SA Pamirs-Discrete Sheet 1 18 of 47
  19. 19. 5 4 3 2 1 +RTCVCC 3D3V_S0 LAN100_SLP 2 330KR2F-L-GP ICH_INTVRMEN 2 330KR2F-L-GP RN64 +RTCVCC 1 U32A OF 6 LPC_LAD[0..3] INTRUDER# AF25 AD21 INTVRMEN LAN100_SLP ICH_INTVRMEN LAN100_SLP B24 TP77 SC15P50V2JN-2-GP LAN_TXD0 LAN_TXD1 LAN_TXD2 AH21 R451 1 1D5V_S0 RN62 1 2 4 3 GLAN_COMP 2 24D9R2F-L-GP HDA_BITCLK D25 C25 AJ16 AJ15 SRN33J-5-GP-U G9 E6 LPC_DRQ0# 1 2 4 3 R459 H_FERR# TP91 TP92 2 1 56R2J-4-GP SATA_TXN0_C SATA_TXP0_C B SATA2RXN SATA2RXP SATA2TXN SATA2TXP AB7 AC6 1 R499 2 24D9R2F-L-GP IGNNE# AF27 H_IGNNE# H_IGNNE# 4 INIT# INTR RCIN# AE24 AC20 AH14 H_INIT# KBRST# H_INIT# 4 H_INTR 4 KBRST# 31 NMI SMI# AD23 AG28 H_NMI H_SMI# H_NMI 4 H_SMI# 4 AA24 H_STPCLK# H_STPCLK# 4 AE27 THRMTRIP_ICH# TP65 TP8 AA23 1 2 R188 within 2" from R184 C IDE_PDD[0..15] IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 H_THERMTRIP# 4,7 24R2J-GP V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 AA4 AA1 AB3 Y6 Y5 placed within 2" from ICH8M IDE_PDCS1# 23 IDE_PDCS3# 23 W4 W3 Y2 Y3 Y1 W5 23 IDE_PDA0 23 IDE_PDA1 23 IDE_PDA2 23 DCS1# DCS3# SATARBIAS# SATARBIAS TP67 R182 56R2J-4-GP DA0 DA1 DA2 Within 500 mils H_DPSLP# 1D05V_S0 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 SATA_CLKN SATA_CLKP AG1 AG2 3 CLK_PCIE_SATA# 3 CLK_PCIE_SATA H_PWRGOOD 5 H_DPSLP# 5 H_FERR# 4 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA SC3900P50V2KX-2GP 2 SC3900P50V2KX-2GP 2 H_PWRGOOD SATA0RXN SATA0RXP SATA0TXN SATA0TXP AF2 AF1 AE4 AE3 C372 1 C373 1 AD24 AG29 SATALED# AF6 AF5 AH5 AH6 SATA_LED# TP64 H_DPRSTP# 5,7 FERR# HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 AF10 GAP-OPEN TP85 16 HDA_SDOUT AE10 AG14 2 H_DPRSTP# H_DPRSTP# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 G72 1 KBGA20 31 H_A20M# 4 H_A20M# H_DPSLP# H_FERR# HDA_RST# AE13 SRN33J-5-GP-U AF26 AE26 CPUPWRGD/GPIO49 HDA_BIT_CLK HDA_SYNC AG3 AG4 AJ4 AJ3 RN66 AF13 AG26 DPRSTP# DPSLP# GLAN_COMPI GLAN_COMPO AJ17 AH17 AH15 AD13 HDA_SDIN0 23 SATA_RXN0_C 23 SATA_RXP0_C 23 SATA_TXN0 23 SATA_TXP0 LDRQ0# LDRQ1#/GPIO23 1D05V_S0 LPC_FRAME# 31,33,34 STPCLK# GLAN_DOCK#/GPIO13 AE14 29 HDA_RST#_CODEC 29 HDA_SDOUT_CODEC LPC_FRAME# 1 C333 SC15P50V2JN-2-GP 29 C4 SRN10KJ-5-GP 2 1 2 1 2 1031 SA 29 HDA_BITCLK_CODEC 29 HDA_SYNC_CODEC FWH4/LFRAME# A20GATE A20M# LAN_RXD0 LAN_RXD1 LAN_RXD2 4 C 4 3 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LAN_RSTSYNC D21 E20 C20 X2 X-32D768KHZ-40GPU E5 F5 G8 F6 GLAN_CLK C21 B21 C22 3 LPC 2 RTCRST# AD22 D22 C329 2 1 2 1 SC1U10V3KX-3GP 2 C624 ICH_RTCX2 1 2 R198 10MR2J-L-GP AF23 SM_INTRUDER# G69 GAP-OPEN FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 RTCX1 RTCX2 CPU ICH_RTCX1 AG25 AF24 ICH_RTCRST# 2 20KR2J-L2-GP 1 1 R466 1 KBGA20 KBRST# 31,33,34 D ICH_RTCX1 ICH_RTCX2 IDE 1 R452 RTC D SM_INTRUDER# 2 1MR2J-1-GP LAN/GLAN 1 R461 IHDA 1 R467 IDE_PDIOR# 23 IDE_PDIOW# 23 IDE_PDDACK# 23 INT_IRQ14 23 IDE_PDIORDY 23 IDE_PDDREQ 23 3D3V_S0 IDE_PDIORDY 1 R507 2 4K7R2J-2-GP INT_IRQ14 1 R491 2 8K2R2J-3-GP B ICH8-M-1-GP-U 20.F0736.003 ETY-CON3-1-GP 3D3V_AUX_S5 4 +RTCVCC U25 BATT1.1 1 2 3 2 W=20mils 1 1 R457 A W=20mils 3 W=20mils 1 CH715FPT-GP 1 R202 2 W=20mils 5 1KR2J-1-GP RTC1 2 C625 SC1U10V3ZY-6GP 2 100R2J-2-GP XOR CHAIN ENTRANCE STRAP : RSVD <Core Design> A 3D3V_S0 Wistron Corporation R484 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1KR2J-1-GP 1 2 HDA_SDOUT_CODEC Title ICH8(2/4) LAN,HD,IDE,LPC DY Size A3 Document Number Rev Pamirs-Discrete Date: Wednesday, December 13, 2006 5 4 3 2 Sheet 1 19 SA of 47
  20. 20. 5 4 3 3D3V_S0 2 1 3D3V_S5 Place closely pin G5 Place closely pin AG9 RN48 PM_BMBUSY# AG12 BMBUSY#/GPIO0 OCP# AG22 H_STP_PCI# H_STP_CPU# AE20 AG18 STP_PCI# STP_CPU# AH11 CLKRUN# 26,27,28,31 PCIE_WAKE# 24,31,34 INT_SERIRQ AE17 AF12 AC13 WAKE# SERIRQ THRM# AJ20 VRMPWRGD AJ22 TP7 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 ICH_RI# PM_BATLOW#_R XDP_DBRESET# GPIO26 8 7 6 5 7,35 VGATE_PWRGD DY SRN10KJ-6-GP 3,28 31 31 31 RN35 1 2 3 4 SMB_LINK_ALERT# OCP# ECSMI# 8 7 6 5 VRMPWRGD 2 0R2J-2-GP SST_CTL TP71 1 R473 TP97 1 2 0R2J-2-GP R490 ECSMI# CPPE# ECSCI# ECSMI# EC_SWI# 1016 SA DY GPIO17 NEWCARD_RST# GPIO20 TP88 GPIO22 TP94 28 NEWCARD_RST# SRN10KJ-6-GP TP63 TP82 C R483 R471 1 1 3 DPRSLPVR 100KR2J-1-GP ICH_RSVD 1KR2J-1-GP 2 2 CLKSATAREQ# TP95 TP87 TP89 29 DY GPIO1 CPPE#1 ECSCI# CLKSATAREQ# GPIO38 GPIO39 IDE_RESET# SB_SPKR SB_SPKR AD9 MCH_ICH_SYNC# AJ13 7 MCH_ICH_SYNC# ICH_RSVD 32K suspend clock output AJ21 Low--> default 3D3V_S0 AH27 SPKR MCH_SYNC# TP3 CLK_14M_ICH 3 CLK_48M_ICH 3 AE23 PM_PWROK DPRSLPVR/GPIO16 AJ14 DPRSLPVR AE21 BATLOW# 2 R189 10KR2J-3-GP 1 PWRBTN# C2 LAN_RST# AH20 RSMRST# AG27 1 2 R475 0R2J-2-GP EC_RMRST# CK_PWRGD E1 CK_PWRGD_R CLPWROK E3 VGATE_PWRGD AJ25 SLP_M# CL_CLK0 CL_CLK1 F23 AE18 CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 F22 AF19 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 D24 AH23 CL_VREF0_ICH CL_VREF1_ICH CL_RST# AJ23 CLGPIO0/GPIO24 CLGPIO1/GPIO10 CLGPIO2/GPIO14 CLGPIO3/GPIO9 AJ27 AJ24 AF22 AG19 SLP_M# SB_PWR_BTN# 31 PLT_RST1# 7,18,26,28,31,33,34,41 1 R509 2 0R2J-2-GP 1 2 R190 100R2J-2-GP CK_PWRGD 10KR2J-3-GP 2 R186 1 SB_RSMRST# 31 CK_PWRGD 3 VGATE_PWRGD 7,35 TP66 CL_CLK0 7 TP74 CL_DATA0 7 TP73 R470 1 CL_RST# 7 GPIO24 GPIO10 GPIO14 GPIO9 C629 TP62 TP68 TP69 TP75 2 R469 TPM_32K_CLK 34 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 26 26 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 26 26 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 28 28 LAN 3D3V_S0 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 27 27 New Card B 27 27 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C311 1 C312 1 PCIE_C_TXN1 PCIE_C_TXP1 P27 P26 N29 N28 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C309 1 C310 1 PCIE_C_TXN2 PCIE_C_TXP2 M27 M26 L29 L28 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 DMI0RXN DMI0RXP DMI0TXN DMI0TXP PERN1 PERP1 PETN1 PETP1 4 3 5V_S0 26 26 C325 1 C324 1 PCIE_C_TXN3 PCIE_C_TXP3 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C322 1 C323 1 PCIE_C_TXN4 PCIE_C_TXP4 H27 H26 G29 G28 PERN4 PERP4 PETN4 PETP4 F27 F26 E29 E28 PERN5 PERP5 PETN5 PETP5 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP C23 B23 E22 SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO U26 1 SMB_CLK 26,28 SMB_CLK 6 2 SMB_DATA 5 3 4 SMB_DATA 26,28 18 SPI_CS1# USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 RN47 A 1 2 3 4 8 7 6 5 SRN10KJ-6-GP RN46 USB_OC#0 1 USB_OC#9 2 USB_OC#8 3 USB_OC#7 4 3D3V_S5 RN38 8 7 6 5 SRN10KJ-6-GP 8 7 6 5 1 2 3 4 SMB_LINK_ALERT# SMLINK0 SMLINK1 PCIE_WAKE# AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# 1 USB_OC#5 1 2 R477 2 R476 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 7 7 7 7 DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 7 7 7 7 DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 7 7 7 7 T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH DMI_ZCOMP DMI_IRCOMP Y23 Y24 DMI_IRCOMP USB USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 F2 F3 USBRBIAS CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3 Within 500 mils 1 R462 2 24D9R2F-L-GP USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 TP98 TP99 USB20_N8 USB20_P8 USB20_N9 USB20_P9 1 R244 B 23 23 28 28 23 23 23 23 32 32 32 32 26 26 17 17 17 17 1D5V_S0 3D3V_S0 USB1 New Card USB2 USB3 CAMERA BT 35 MINICARD 1 DOCK R472 330R2J-3-GP DY 2 CK_PWRGD 2 VRMPWRGD Q13 2N7002-11-GP CLK_EN# G A Wistron Corporation 2 22D6R2F-L1-GP Within 500 mils R233 1 0R2J-2-GP R474 1 0R2J-2-GP <Core Design> 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(3/4) PM,USB,GPIO 10KR2F-2-GP Size Custom 10KR2F-2-GP Date: 5 1 7 7 7 7 SRN10KJ-6-GP ICH8-M-1-GP-U USB_OC#3 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 USBRBIAS# USBRBIAS ICH_SMBCLK 3,13,14 2N7002DW-1-GP USB_OC#4 USB_OC#2 USB_OC#1 USB_OC#6 V27 V26 U29 U28 DMI_CLKN DMI_CLKP SPI 1 2 Mini Card 2 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP D23 F21 26 26 K27 K26 J29 J28 D27 D26 C29 C28 Mini Card 1 RN29 SRN2K2J-1-GP 3,13,14 ICH_SMBDATA 2 U32B 2 OF 6 28 28 2 DY 1 2 10R2J-2-GP R468 453R2F-1-GP D 1 R594 3D3V_S0 S 32KHZ 7 TSLCX08MTCX-GP 2 3K24R2F-GP G792_CLK 22 5 Direct Media Interface 2 10R2J-2-GP SCD1U16V2KX-3GP 2 1 14 1 R593 10KR2J-3-GP SB_SPKR 1 2 R485 DY PCI-Express 1 2 3D3V_S0 32KHZ C R463 453R2F-1-GP ICH8-M-1-GP-U C633 6 3D3V_S0 3K24R2F-GP 1 4 1 2 PM_BATLOW#_R PM_PWROK 7,22 DPRSLPVR 7,35 3D3V_S5 ICH_SUSCLK DY D High--> No boot R595 10KR2J-3-GP U70B C671 SC4D7P50V2CN-1GP GPIO26 PWROK SYSGPIO INT_SERIRQ THERM_SCI# RN31 1 2 3 4 DY PM_SLP_S3# 22,28,31,34,37,38,40 PM_SLP_S4# 17,28,31,36,37,38 S4_STATE#/GPIO26 GPIO H_STP_PCI# H_STP_CPU# MISC 1 2 OCP# SRN10KJ-6-GP DY C371 SC4D7P50V2CN-1GP ICH_SUSCLK AG23 AF21 AD18 SMBALERT#/GPIO11 DY 10KR2J-3-GP 3 3 D3 SLP_S3# SLP_S4# SLP_S5# 7 PM_BMBUSY# 4 2 SUSCLK 1 2 SUS_STAT#/LPCPD# SYS_RESET# 2 F4 AD15 XDP_DBRESET# 24,31,34 PM_CLKRUN# 1 3D3V_S5 GPIO22 34 LPC_PD# 4 XDP_DBRESET# 1 2 3 4 1 RN44 SRN2K2J-1-GP CLK_14M_ICH CLK_48M_ICH CLK14 CLK48 POWER MGT R239 AG9 G5 8 7 6 5 2 4 3 3D3V_S0 GPIO RI# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 GPIO37 SATA AF17 ICH_RI# SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3 AJ12 AJ10 AF11 AG11 SCD1U16V2KX-3GP 2 1 3D3V_S0 D Controller Link R232 SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 SMB 2 AJ26 AD19 AG21 AC17 AE19 CLOCKS SMB_CLK SMB_DATA SMB_LINK_ALERT# SMLINK0 SMLINK1 R493 10R2J-2-GP DY RN50 1 2 1 R245 10R2J-2-GP 3D3V_S0 U32D 4 OF 6 SRN10KJ-6-GP NEWCARD_RST# 10KR2F-2-GP CLK_14M_ICH 1 RN28 SRN2K2J-1-GP 1 CLK_48M_ICH 2 INT_SERIRQ PM_CLKRUN# CLKSATAREQ# THERM_SCI# 8 7 6 5 4 3 1 2 3 4 4 3 2 Document Number Rev Pamirs-Discrete Monday, December 18, 2006 Sheet 1 20 SA of 47
  21. 21. 5 4 3 2 1 +RTCVCC 20 mils 6 U32F OF 6 C611 1D05V_S0 SC1U10V3ZY-6GP 1D5V_S0_SATAPLL AJ6 1 SCD1U16V2ZY-2GP AC8 AD8 AE8 AF8 3D3V_S0 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 AA3 U7 V7 W1 W6 W7 Y7 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 VCCSATAPLL VCCSUS1_5 AC16 VCCSUS1_5_ICH_1 VCCSUS1_5 J7 VCCSUS1_5_ICH_2 VCC1_5_A VCC1_5_A VCCSUS3_3 C3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 AC18 AG20 AC21 AC22 AH28 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 P6 P7 N7 C1 P1 R1 P2 P3 R3 P4 P5 R5 R6 VCCCL1_05 G22 VCCCL1_5 3D3V_S0 VCCCL3_3 VCCCL3_3 F20 G21 1 2 1 2 SCD1U16V2ZY-2GP 1 2 1 1 K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 D C 2 2 PCI ATX C616 C635 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 3D3V_S5 B25 VCCGLAN3_3 2 C637 3D3V_S5 1 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 TP93 3D3V_S5 SCD1U16V2ZY-2GP 2 VCCGLANPLL A26 A27 B26 B27 B28 TP79 C677 C599 C665 SCD1U16V2ZY-2GP C674 SC4D7U6D3V3KX-GP VCCPSUS VCCLAN3_3 VCCLAN3_3 VCCPUSB VCCLAN1_05 VCCLAN1_05 TP96 TP72 3D3V_S0 VCCCL1_05_ICH VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF B ICHGND1 A1 R504 A2 A28 A29 ICHGND2 R446 AJ28 AH1 AH29 AJ1 ICHGND3 R503 AJ2 AJ29 ICHGND4 B1 R508 B29 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP ICH8-M-1-GP-U TP70 3D3V_S0 C631 A 1 BLM18PG121SN-1GP C317 SC4D7U10V5ZY-3GP 1 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS <Core Design> ICH8-M-1-GP-U SC1U10V3ZY-6GP 2 SC2D2U10V3KX-GP SC10U6D3V5MX-3GP 2 C618 2 C307 1D5V_S0_GLANPLL L48 1 1D5V_S0 2 2 1 1 BLM18PG121SN-1GP 1 1 L23 VCC1_5_A A24 VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2 F17 G18 F19 G20 TP81 TP76 3D3V_S0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A22 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A W23 1D5V_S0 1D5V_S0 VCCUSBPLL USB CORE 2 SCD1U16V2ZY-2GP 1 VCC1_5_A VCC1_5_A VCC1_5_A 1 J6 AF20 ARX 1 VCCSUS1_05 VCCSUS1_05 C592 1 1 1 SCD1U16V2ZY-2GP 2 VCC1_5_A VCC1_5_A F1 L6 L7 M6 M7 C666 2 C672 A AD11 D1 1D5V_S0 C678 AC12 VCCSUSHDA AA5 AA6 1D5V_S0 SCD1U16V2ZY-2GP VCCHDA VCC1_5_A VCC1_5_A 2 C668 SC1U10V3ZY-6GP VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A GLAN POWER 2 B SCD1U16V2ZY-2GP 3D3V_S0 AC1 AC2 AC3 AC4 AC5 1D5V_S0 C654 SCD1U16V2ZY-2GP VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A 2 1 1 2 SC10U6D3V5MX-3GP SC1U10V3ZY-6GP (DMI) C667 (SATA) C655 C663 C680 SCD1U16V2ZY-2GP AC10 AC9 C683 3D3V_S0 SC4D7U6D3V3KX-GP 3D3V_S0 AE7 AF7 AG7 AH7 AJ7 1D5V_S0 2 1 2 AD2 VCC3_3 VCC3_3 VCC3_3 VCC3_3 AC7 AD7 C369 2 1 2 VCC3_3 SCD1U16V2ZY-2GP 3D3V_S0 G12 G17 H7 C675 BLM18PG121SN-1GP SCD1U16V2ZY-2GP 1 2 AF29 2 2 VCC3_3 1D05V_S0 C648 1 K L52 1 1D5V_S0 AC23 AC24 1 C676 SCD1U16V2ZY-2GP 2 1 2 20 mils ICH_V5REF_SUS V_CPU_IO V_CPU_IO 2 100R2J-2-GP AE28 AE29 2 D21 CH751H-40PT-1GP C320 SC22U6D3V5MX-2GP R29 VCC_DMI VCC_DMI 1 R247 1D25V_S0 1 A 1 C SCD01U16V2KX-3GP 1D5V_S0 C326 SC10U6D3V5MX-3GP 2 3D3V_S5 C598 2 5V_S5 VCCDMIPLL L22 1 2 IND-1UH-36-GP 1D5V_DMIPLL_S0 1 K ICH_V5REF_RUN C647 SCD1U16V2ZY-2GP 2 1 2 20 mils VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B C664 1 1 2 1 2 1 2 D18 CH751H-40PT-1GP C619 SC2D2U6D3V3MX-1-GP R234 100R2J-2-GP C318 SC10U6D3V5MX-3GP 3D3V_S0 A 1 5V_S0 C321 SC10U6D3V5MX-3GP 1 2 ST220U2VBM-3GP C308 C613 2 AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 BLM18PG121SN-1GP CORE 1D5V_A3GP_S0 2 VCCP CORE 1 V5REF_SUS A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 SCD1U16V2ZY-2GP G4 IDE ICH_V5REF_SUS VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 V5REF V5REF 1 T7 A16 VCCA3GP ICH_V5REF_RUN L50 5 OF 6 VCCRTC 2 U32E AD25 D 1D5V_S0 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 1 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 1 C622 Wistron Corporation DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(4/4) POWER&GND Size Custom Document Number Rev Pamirs-Discrete Date: Thursday, October 19, 2006 5 4 3 2 Sheet 1 21 SA of 47
  22. 22. FAN1_VCC 5V_S0 K 1 D13 C151 SC10U10V5ZY-1GP 1 2 C162 SCD1U16V2ZY-2GP 2 1 *Layout* 15 mil 1N4148W-1-GP A R56 10KR2J-3-GP EAN1 2 5 RN5 3D3V_S0 4 3 G792_SCL G792_SDA 1 2 FAN1_FG1 SRN10KJ-5-GP 3 2 1 1 FAN1_VCC *Layout* 15 mil 2 C145 SC1000P50V3JN-GP 4 ACES-CON3-1-GP 20.F0735.003 5V_S0 2 FAN1 FG1 CLK SDA SCL NC#19 DXP1 DXP2 DXP3 1 VCC DVCC 7 9 11 C163 SCD1U16V2ZY-2GP 1 4 14 16 18 19 DGND DGND 5 17 SGND1 SGND2 SGND3 8 10 12 G792_CLK 20 G792_SDA G792_SCL G792_DXP2 1 2 2 1 1 1 R99 10KR2F-2-GP C154 SC4D7U10V5ZY-3GP 2 C475 SC1U10V3ZY-6GP 6 20 3 5V_G792_S0 2 200R2F-L-GP 15 13 3 2 1 Setting T8 as 100 Degree THRM# HW_THRM_SHDN# V_DEGREE ALERT# THERM# THERM_SET RESET# GTHERMDA 42 1 Q5 PMBS3904-1-GP 1 G792SFUF-GP 3D3V_S5 2 2 V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC G792_DXN2 3 R100 100KR2F-L1-GP Q6 PMBS3904-1-GP 1 C200 SC2200P50V2KX-2GP 2 31R505 THRM# EC_RST# 1 2 0R2J-2-GP 2 R83 1 U17 *Layout* 30 mil C199 SC2200P50V2KX-2GP 2 5V_S0 1 7 SSLVC08APWR-GP R309 DXP1:108 Degree DXP2:H/W Setting DXP3:88 Degree G21 H_THERMDA 4 1 G20 GAP-CLOSE GAP-CLOSE C180 SC2200P50V2KX-2GP H_THERMDC 4 1 G792_RST# 2 PM_SLP_S3# 20,28,31,34,37,38,40 13 1 12 11 7,20 PM_PWROK 2 2 14 GTHERMDC 42 U43D 2 100KR2J-1-GP Place near chip as close as possible KBC_3D3V_AUX R510 100KR2J-1-GP 1N4148W-1-GP U63 5 5 1 1 2 GND G792_SCL EC_RST# 3 EC_RST# 31 1 KBC_SDA1 31,32 2 6 VCC A B 3 34,36 PWR_S5_EN# 4 Y S5_ENABLE 31 C682 SC1U10V3ZY-6GP 2 4 2 3D3V_S0 U51 G792_SDA A 3D3V_S0 31,32 KBC_SCL1 1 D37 K 5V_AUX_S5 74AHCT1G00DCKR-GP 2N7002DW-1-GP <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Thermal/Fan Controllor G792 Size Custom Document Number Date: Monday, October 23, 2006 Rev Pamirs-Discrete Sheet 22 of SA 47
  23. 23. IDE_PDD[0..15] SATA HD Connector CD-ROM CONNECTOR 3D3V_S0 CDROM_LED# 1 R518 INT_IRQ14 2 8K2R2J-3-GP 1 51 C681 1 4 2SATA_RXN0 5 SATA_RXP0 1 6 SC3900P50V2KX-2GP 7 SC3900P50V2KX-2GP SATA_RXP0_C 19 2 C679 8 9 10 11 12 100 mil 19 IDE_PDDREQ 19 IDE_PDIOR# 13 14 5V_S3 15 5V_USB1_S3 17 18 19 IDE_PDA2 19 IDE_PDCS3# 1 19 20 21 22 1 C684 SC10U10V5ZY-1GP SYN-CONN22A-GP-U2 1 5V_S0 24 20.F0817.022 CD_AUDL 29 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 2 C462 SCD1U16V2ZY-2GP 1 FUSE-2A8V-3GP 2 2 19 IDE_PDDACK# 16 100 mil 2 F2 1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 IDE_PDA2 34 36 38 40 42 44 DY 46 C685 C686 48 50 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP NP2 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 CD_AGND 29 RSTDRV#_5 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 3D3V_S0 1 SATA_TXP0 19 R270 4K7R2J-2-GP 2 2 19 SATA_RXN0_C NP1 2 29 CD_AUDR 3 19 SATA_TXN0 1 R267 CDROM1 HDD1 23 1 1 2 4K7R2J-2-GP 3D3V_S0 C355 SCD1U16V2ZY-2GP 2 C656 SC10U10V5ZY-1GP 2 SCD1U16V2ZY-2GP 2 1 C669 2 C657 SC10U10V5ZY-1GP 5V_S0 1 1 5V_S0 19 IDE_PDIOW# 19 IDE_PDIORDY 19 INT_IRQ14 19 IDE_PDA1 19 IDE_PDA0 19 IDE_PDA1 IDE_PDA0 IDE_PDCS1# 19 CDROM_LED# 16 5V_S0 primary channel:low 52 TYCO-CONN50-4R-GP-U 20.80353.050 USB PORT 3 HDMI_1_TXC 13 2 2 C570 2 C572 3D3V_S0 TC21 SE100U16VM-L1-GP 3 2 D14 2 HDMI_1_TXC# HDMI_TXC# HDMI_HDP 3 DY BAV99PT-GP-U SKT2 20 4 1 5V_USB1_S3 1 HDMI_1_TXD1 HDMI_TXD1 TSAHCT08PWR-1GP 1 1 1 7 PCI_PLTRST# SCD1U16V2ZY-2GP SC1000P50V3JN-GP 43 43 2 FUSE-1D1A6V-8GP HDMI_1_TXD2# HDMI_TXD2# 18 100 mil 4 1 43 1 RSTDRV#_5 11 5V_USB2_S3 F3 L57 ACM2012H-900-GP ACM2012H-900-GP L56 U68D 12 5V_S3 4 HDMI_TXC 1 43 5V_S0 14 HDMI_1_TXD2 HDMI_TXD2 2 43 L54 ACM2012H-900-GP 1 USB_PN0 R181 2 0R0402-PAD USB_1- USB1 22 12 10 9 8 7 6 5 4 3 2 20 43 HDMI_1_TXD2# HDMI_1_TXD1 3 2 HDMI_1_TXD2 HDMI_1_TXD1# HDMI_TXD1# HDMI_1_TXD1# HDMI_1_TXD0 HDMI_1_TXD0# HDMI_1_TXC 42 HDMI_1_TXD0 42 42 TP60 HDMI_SCL HDMI_SDA 5V_S0 HDMI_1_TXC# 1 2 R364 0R2J-2-GP HDMI_SCL HDMI_SDA HDP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4A 3A 1 USB_PP0 2 150R2J-L1-GP-U 1 B NUMLK_LED C R1 R2 PDTC124EU-1-GP USB_1- R85 1A 42 11 NUMLK_LED# ACES-CON10-5-GP E HDMI_HDP HDMI_HDP 1 2 L16 1 2 BLM15AG221SN-GP 20.F0735.010 HDP <Core Design> 10KR3F-L-GP R71 100KR3J-L-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 SKT-HDMI23P-GP 4 1 R367 Q22 23 1 USB_1+ 5V_USB2_S3 ACM2012H-900-GP L55 HDMI_TXD0# 2 0R0402-PAD USB_1+ 21 43 R180 31 2A USB_PN3 USB_PP3 USB_PN2 USB_PP2 5V_S3 20 2 3 HDMI_TXD0 2 43 HDMI_CEC 20 20 20 20 1 Title HD/CDROM/USB HDMI_1_TXD0# Size A3 Document Number Date: Tuesday, December 12, 2006 Rev Pamirs-Discrete Sheet 23 of SA 47

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