3. Verilog A vs SPICE
Verilog-A
designed to describe models
for SPICE-class simulators
SPICE simulators
work by building up a
system of nonlinear
differential equations that
describe the circuit that they
are to simulate
SPICE representation of a circuit being much slower to
simulate than a Verilog representation.
4. Verilog vs Verilog-A
Module
A unit of Verilog code that is used to describe a component.
A circuit is described with a hierarchical composition of modules
In Verilog, built-in primitives
generally describe gates
In Verilog-A, the built-in primitives
describe common circuit components
Resistors
Capacitors
Inductors
Semiconductor Devices
5. Structural Model
A module that simply refers to other
modules is often referred to as a
structural model, or a netlist
Behavioral model.
a module that uses equations to describe a
component is referred to as a behavioral model.
In Verilog-A, components are constructed using nodes and branches.
Modeling in Verilog-A
6. Modeling in Verilog-A (Cont.)
Description consists of two things:
The way that the nodes and branches connected (their
topology),
The way in which the potential and flow are related on
each branch (the branch relations).
7. Modeling in Verilog-A (Cont.)
module resistor (t1, t2);
electrical t1, t2;
parameter real r=1;
branch (t1, t2) res;
analog V(res) <+ r*I(res);
endmodule
module resistor (t1, t2);
electrical t1, t2;
parameter real r=1;
analog V(t1,t2) <+ r*I(t1,t2);
endmodule
8. module vdd (dd);
electrical dd;
parameter real dc=2.5;
analog V(dd) <+ dc;
endmodule
Modeling in Verilog-A (Cont.)
9. Modeling in Verilog-A (Cont.)
module series_rlc (t1, t2);
electrical t1, t2;
parameter real r=1;
parameter real l=1;
parameter real c=1 exclude 0;
analog begin
V(t1,t2) <+ r*I(t1,t2);
V(t1,t2) <+ l*ddt(I(t1,t2));
V(t1,t2) <+ idt(I(t1,t2))/c;
end
endmodule
10. Modeling in Verilog-A (Cont.)
module shunt_rlc (t1, t2);
electrical t1, t2;
parameter real r=1 exclude 0;
parameter real l=1 exclude 0;
parameter real c=1;
analog begin
I(t1,t2) <+ V(t1,t2)/r;
I(t1,t2) <+ idt(V(t1,t2))/l;
I(t1,t2) <+ c*ddt(V(t1,t2));
end
endmodule
11. Modeling in Verilog-A (Cont.)
module shunt_rlc (t1, t2);
electrical t1, t2;
parameter real r=1;
parameter real l=1;
parameter real c=1;
branch (t1, t2) res, ind, cap;
analog begin
V(res) <+ r*I(res);
V(ind) <+ l*ddt(I(ind));
I(cap) <+ c*ddt(V(cap));
end
endmodule
12. Modeling in Verilog-A (Cont.)
module series_rlc (t1, t2);
electrical t1, t2, n1, n2;
parameter real r=1;
parameter real l=1;
parameter real c=1;
branch (t1, n1) res;
branch (n1, n2) ind;
branch (n2, t2) cap;
analog begin
V(res) <+ r*I(res);
V(ind) <+ l*ddt(I(ind));
I(cap) <+ c*ddt(V(cap));
end
endmodule
13. Modeling in Verilog-A (Cont.)
// voltage controlled voltage
source
module vcvs (pout, nout, pin, nin);
electrical pout, nout, pin, nin;
parameter real gain=1;
analog V(pout,nout) <+ gain*V(pin,nin);
endmodule
14. Modeling in Verilog-A (Cont.)
// voltage controlled current source
module vccs (pout, nout, pin, nin);
electrical pout, nout, pin, nin;
parameter real gain=1;
analog V(pout,nout) <+ gain*I(pin,nin);
endmodule
15. Modeling in Verilog-A (Cont.)
// current controlled voltage source
module ccvs (pout, nout, pin, nin);
electrical pout, nout, pin, nin;
parameter real gain=1;
analog I(pout,nout) <+ gain*V(pin,nin);
endmodule
16. Modeling in Verilog-A (Cont.)
// current controlled current source
module cccs (pout, nout, pin, nin);
electrical pout, nout, pin, nin;
parameter real gain=1;
analog I(pout,nout) <+ gain*I(pin,nin);
endmodule
