2. Outline
• Basic Concepts
• Semiconductor Random Access Memories
• Read Only Memories
• Speed, Size, and Cost
• Cache Memories
• Mapping Function
• Virtual Memories
3. Basic Concepts
• The memory subsystem is an integral and important component of
any computer system.
• The execution speed of programs is mainly dependent on the speed
of with which instructions and data can be transferred between the
processor and memory.
• Ideally, the memory would be fast, large, and inexpensive.
Unfortunately, it is impossible to meet all three of these requirements
simultaneously.
• The memory of a computer comprises a hierarchy, including a cache,
the main memory, and secondary storage
4. Basic Concepts
• The maximum size of the memory that can be used in any computer
is determined by the number of address lines of the processor.
• For example, a 16-bit computer that generates 16-bit addresses is capable of
addressing up to 216=64K memory locations.
• Similarly, machines whose instructions generate 32-bit addresses can utilize a
memory that contains up to 232=4G memory locations.
• machines with 64-bit addresses can access up to 264 = 16E (exa) ≈ 16 × 1018
locations.
• Most modern computers are byte addressable (When the data space
in the cell = 8 bits then the corresponding address space is called as
Byte Address).
• The number of bits stored or retrieved in one memory access is called
the word length.
5. Basic Concepts
• Fig shows a possible address assignment for a byte-addressable 32-bit
computer. This is the big-endian type arrangement.
• From the system standpoint, we can view the memory unit as a block box.
6. Connection of the Memory to the Processor
• Data transfer between the memory
and processor takes place through the
use of two processor registers, MAR
and MDR.
• If MAR is k-bits long, the memory unit
can contain up to 2k addressable
locations.
• If MDR is n-bits long, n bits of data can
be transferred between memory and
processor at a time.
• The external bus also includes the
control lines Read/Write(R/W) and
memory function completed(MFC) for
coordinating the data transfer.
7. Terminologies used are:
• Memory access time: the time elapses between the initiation of an operation and the
completion of that operation.
• Memory cycle time: which is the minimum time delay required between the initiation of
two successive memory operations.
• Random Access Memory (RAM): A memory is called random-access memory, if any
location can be accessed for a Read or Write operation in some fixed amount of time
that is independent of the location’s address
• cache memory: small, fast memory a cache memory. inserted between the larger,
slower main memory and the processor. It holds the currently active portions of a
program and their data.
• Virtual memory: used to increase the apparent size of the physical memory when large
program segment is to be executed.
• With this technique, only the active portions of a program are stored in the main
memory, and the remainder is stored on the much larger secondary storage device.
8. Block Transfers
• Data move frequently between the main memory and the cache and
between the main memory and the disk.
• Data Transfers do not occur one word at a time. Data are always
transferred in contiguous blocks involving tens, hundreds, or
thousands of words.
9. Semiconductor RAM Memories
• Semiconductor random-access memories (RAMs) are available in a
wide range of speeds. Their cycle times range from 100 ns to less than
10 ns.
Internal Organization of Memory Chips
10. Internal Organization of Memory Chips
• Memory cells are usually organized in the form of an array, in which each
cell is capable of storing one bit of information.
• Each row of cells constitutes a memory word, and all cells of a row are
connected to a common line referred to as the word line, which is driven by
the address decoder on the chip.
• The cells in each column are connected to a Sense/Write circuit by two bit
lines, and the Sense/Write circuits are connected to the data input/output
lines of the chip.
• During a Read operation, these circuits sense, or read, the information
stored in the cells selected by a word line and place this information on the
output data lines.
• During a Write operation, the Sense/Write circuits receive input data and
store them in the cells of the selected word.
11. Internal Organization of Memory Chips
• A very small memory circuit consisting of 16 words of 8 bits each. This
is referred to as a 16 × 8 organization.
• The data input and the data output of each Sense/Write circuit are
connected to a single bidirectional data line that can be connected to
the data lines of a computer. Two control lines, R/W and CS, are
provided.
• The R/W (Read/Write) input specifies the required operation, and the
CS (Chip Select) input selects a given chip in a multichip memory
system.
• The memory circuit in the above Figure stores 128 bits and requires
14 external connections for address, data, and control lines. It also
needs two lines for power supply and ground connections.
13. 1K (1024) memory
• This circuit can be organized as a 128 × 8 memory, requiring a total of
19 external connections.
• The same number of cells can be organized into a 1K × 1 format. In
this case, a 10-bit address is needed, but there is only one data line,
resulting in 15 external connections.
• The required 10-bit address is divided into two groups of 5 bits each
to form the row and column addresses for the cell array. A row
address selects a row of 32 cells, all of which are accessed in parallel.
But, only one of these cells is connected to the external data line,
based on the column address
14. Static Memories
• A static memory cell is capable of retaining their state as long as power is
applied .
• static RAM (SRAM) cell may be implemented using a latch.
• Two inverters are cross-connected to form a latch.
• The latch is connected to two bit lines b and b’ by transistors T1 and T2.
• These transistors act as switches that can be opened or closed under
control of the word line.
• When the word line is at ground level, the transistors are turned off and
the latch retains its state. This is maintained as long as the signal on the
word line is not changed and power is applied to the circuit.
16. Static Memories
Read operation
• The word line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit line b is high and the signal on bit line
b′ is low.( X = 1, Y = 0)
• If the cell is in state 0, the signal on bit line b is low and the signal on bit line b′
is high.( X =0, Y = 1).
• The Sense/Write circuit at the end of the two bit lines monitors their state
and sets the corresponding output accordingly.
Write operation
• During a Write operation, the Sense/Write circuit drives bit lines b and b′,
instead of sensing their state.
• It places the appropriate value on bit line b and its complement on b′ and
activates the word line. This forces the cell into the corresponding state,
which the cell retains when the word line is deactivated.
17. CMOS Cell
• SRAM cell can be realized using CMOS gates.
• Transistor pairs (T3, T5) and (T4, T6) form the
inverters in the latch.
• In state 1, the voltage at point X is
maintained high by having transistors T3 and
T6 on, while T4 and T5 are off. If T1 and T2
are turned on, bit lines b and b′ will have high
and low signals, respectively.
• Continuous power is needed for the cell to
retain its state. If power is interrupted, the
cell’s contents are lost. When power is
restored, the latch settles into a stable state,
but not necessarily the same state the cell
was in before the interruption.
18. SRAM
• Merit:
It has low power consumption because the current flows in the cell only when
the cell is being accessed.
Static RAMs can be accessed quickly. It access time is few nanoseconds.
• Demerit:
SRAMs are said to be volatile memories because their contents are lost when
the power is interrupted.
19. Dynamic RAMs
• Static RAMs are fast, but their cells require several transistors. Less
expensive and higher density RAMs can be implemented with simpler cells.
But, these simpler cells do not retain their state for a long period, unless
they are accessed frequently for Read or Write operations. Memories that
use such cells are called dynamic RAMs (DRAMs).
• Information is stored in a dynamic memory cell in the form of a charge on a
capacitor, but this charge can be maintained for only tens of milliseconds.
Since the cell is required to store information for a much longer time, its
contents must be periodically refreshed by restoring the capacitor charge
to its full value. This occurs when the contents of the cell are read or when
new information is written into it.
20. Dynamic RAMs
• A dynamic memory cell that consists of a capacitor, C, and a transistor,
T, is shown in Figure.
21. Write operation
• In order to store information in the cell, the transistor T is turned on
and the appropriate voltage is applied to the bit line, which charges
the capacitor.
• After the transistor is turned off, the charge remains stored in the
capacitor, but not for long. The capacitor begins to discharge. This is
because the transistor continues to conduct a tiny amount of current,
measured in Pico amperes, after it is turned off.
• Hence the information stored in the cell can be retrieved correctly
before the threshold value of the capacitor drops down,
22. Read Operation
• During a read operation, the transistor is turned on and a sense
amplifier connected to the bit line detects whether the charge on the
capacitor is above the threshold value.
• If charge on capacitor > threshold value →Bit line will have logic value
1.
• If charge on capacitor < threshold value → Bit line will set to logic
value 0.
23. A 16- megabit DRAM chip configured as 2M x
8, is shown in Figure
24. Description
• The cells are organized in the form of a 4K × 4K array.
• The 4096 bit cells in each row are divided into 512 groups of 8, so
that a row can store 512 bytes of data.
• 21 bit address is needed to access a byte in the memory (12 bit to
select a row, and 9 bits specify the group of 8 bits in the selected
row).
• A (0-8) → Column address of a byte.
• A (9-20) → Row address of a byte.
25. Read/Write Operation:
• During Read/ Write operation, the row address is applied first.
• Row address is loaded into the row address latch in response to a
signal pulse on Row Address Strobe (RAS) input of the chip.
• When a Read operation is initiated, all cells on the selected row are
read and refreshed.
• Shortly after the row address is loaded, the column address is applied
to the address pins and loaded into Column Address Strobe (CAS).
• The information in this latch is decoded and the appropriate group of
8 Sense/Write circuits is selected.
26. Read/Write Operation:
• R/W =1(read operation).
• The output values of the selected circuits are transferred to the data lines D0 - D7.
• R/W=0 (write operation).
• The information on D0 - D7 is transferred to the selected circuits.
• RAS and CAS are active low so that they cause the latching of address when
they change from high to low. This is because they are indicated by RAS
and CAS.
• To ensure that the contents of a DRAM‘s are maintained, each row of cells
must be accessed periodically. Refresh operation usually perform this
function automatically.
• A specialized memory controller circuit provides the necessary control
signals RAS and CAS that govern the timing. The processor must take into
account the delay in the response of the memory. Such memories are
referred to as Asynchronous DRAM‘s.
