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1. Design and Implementation of VLSI Systems
(EN1600)
Lecture 23: Sequential Circuit Design (2/2)

2. Sequencing methods

3. Sequencing timing terminology
tpd Logic Prop. Delay tpdq Latch D-Q Prop Delay
tcd Logic Cont. Delay tpcq Latch D-Q Cont. Delay
tpcq Latch/Flop Clk-Q Prop Delay tsetup Latch/Flop Setup Time
tccq Latch/Flop Clk-Q Cont. Delay thold Latch/Flop Hold Time
S. Reda EN160 SP’07

4. 1. Max-Delay (setup) constraint: Flip-flops

5. 2. Max-Delay (setup) constraint: 2-phase latches

6. 2. Min-delay (hold) constraint: Flip-flip

7. 2. Min-delay (hold) constraint: 2-phase
latches
S. Reda EN160 SP’07

8. 3. Time borrowing
φ1
φ2
φ1 φ2 φ1
Latch
Latch
Latch
Combinational
(a) Combinational Logic
Logic
Borrowing time across Borrowing time across
half-cycle boundary pipeline stage boundary
φ1 φ2
Latch
Latch
Combinational
(b) Combinational Logic Logic
Loops may borrow time internally but must complete within the cycle
S. Reda EN160 SP’07

9. How much time can be borrowed?
φ1 φ2
D1 Q1 D2 Q2
Combinational Logic 1
L1
L2
φ1
φ2 tnonoverlap
Tc
tsetup
Tc/2 tborrow
Nominal Half-Cycle 1 Delay
D2
Tborrow <= Tc/2 –(tsetup + tnonoverlap)
S. Reda EN160 SP’07

10. 4. Clock Skew
• We have assumed zero clock skew
• Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing
S. Reda EN160 SP’07

11. 4. Skew: flip-flops
S. Reda EN160 SP’07

12. 4. Skew: 2-phase latches
S. Reda EN160 SP’07