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European Microwave PLL Class

PLL Class at European Microwave Conference - October 2011

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European Microwave PLL Class

  1. 1. PLL Modeling Using CAE Tools Eric Drucker, Master PLL Engineer Agilent Technologies Santa Rosa, CA 1
  2. 2. Introduction -1  Outline  Linear system and feedback review  Linear model for PLL  AC and small signal transient analysis using various CAE tools  Mathematical, ADS and SPICE noise models for PLL components (VCO, divider, phase detector)  PLL phase noise optimization and modeling  Detailed description and demonstration of ADS non-linear building blocks using transient and envelope simulation  Switching speed analysis of PLL using ADS; step versus ramp switching. 2
  3. 3. Linear Modeling 3
  4. 4. Linear Circuit Review -1  Linear Circuit Review  Loop and nodal analysis  KVL and KCL (Kirchhoff voltage and current laws) • Voltage around loop = 0 • Net current into node = 0  Thévenin equivalent circuit  Can write circuit equations in time domain or Laplace domain  Laplace Transform  The Laplace transform represents a linear differential equations with constant coefficients (circuit elements are not time varying); s is d/dt operator  Transfer function in s characterizes system  Inverse Laplace transform used for small signal time domain 4
  5. 5. Linear Circuit Review -2  Numerator of transfer function contain the zeros  Denominator of transfer function contain the poles  Bode plots for frequency response gain and phase, s = j  Each pole is -20 dB/decade or -6 dB/octave  Each zero is +20 dB/decade or +6 dB/octave  Poles and zeros can be pure real or complex 5
  6. 6. Linear Circuit Review -3 Differential Equation for R-C R 1 v i R i dt v(t) i(t) C C dv di 1 R i dt dt C Laplace Equation for R-C Network R Vout(s) 1 (s C ) Vout (s ) Vin (s ) Vin(s) I(s) 1/sC R 1 (s C ) 6
  7. 7. Linear Circuit Review -4 Differential Equation for R-L-C dv1 R v i R L i dt dt C L dv di d 2i 1 v(t) i(t) C R L 2 i dt dt dt C d 2i R di 1 1 dv i dt 2 L dt L C L dt Laplace Equation for R-L-C Network 1 s C 1 Vout (s ) Vin (s ) R Vout(s) R s L 1 R s C s2 L C 1 SL s C Vin(s) I(s) 1/sC 1 2 T (s ) L C n s 2 R s 1 s2 2 n s 2 n L L C 7
  8. 8. Linear Circuit Review -5 i 6 fstop npd fstart 1000 fstop 1 10 npd 100 i 0 log npd 0.5 fi 10 fstart si j fi fstart 6 3 R 1000 C 0.016 10 L 25 10 1 1 sC sC TRC ( s) TRLC ( s) dBRC 20 log TRC si dBRLC 20 log TRLC si 1 1 i i R R s L s C s C 1 1 2 sC 1 LC n 1 2 2 R 1 2 2 R s L R s C 1 s L C s s s 2 n s n s C L L C 1 4 R n n 5 10 0.4 L C 2 L n 6 3 Step Function is for V in(s) = 1/s tstep 0.1 10 tstop 0.2 10 t 0 tstep tstop 1 C t R Inverse Laplace Transform vRC ( t) 1 e 2 2 2 t n 2 2 2 2 2 2 2 2 2 t n cosh t n n e n n n n n sinh t n n e vRLC ( t) 2 2 n 1 8
  9. 9. Linear Circuit Review -6 Bode Plot for RC and RLC Circuit Time Domain Plot for RC and RLC Circuit 5 1.4 0 1.2 5 1 Amplitude 10 0.8 dB 15 0.6 20 0.4 25 0.2 30 3 4 5 6 0 1 10 1 10 1 10 1 10 0 20 40 60 80 100 120 140 160 180 200 Frequency in Radians /Sec Time in uS 9
  10. 10. Basic Control Theory -1  Basic Control Theory  Forward block, G(s)  Feedback block, H(s)  Loop Gain G(s)*H(s)  System Transfer Function = Forward Gain/(1 + Loop Gain)  Bode plots for open and closed loop gain and phase, s = j  Root locus plots in complex plane for loop gain & stability analysis  Only denominator counts for stability (“poles in right half plane”)  Initial and final value theorem gives insight into limits of time domain performance when excited by step, ramp, etc.. 10
  11. 11. Basic Control Theory -2 C(s) Forward Gain R(S) 1 Loop Gain + (s) R(s) G(s) C(s) R(s) Reference Input - C(s) Controlled Output ε(s) Error C(s) G(s) R(s) 1 G(s) H(s) H(s) (s) 1 R(s) 1 G(s) H(s) R(s) can be step (1/s), ramp (1/s 2 ) or Sinusoid 11
  12. 12. Basic Control Theory -3  Stability/Frequency Response  c = gain crossover frequency is when the magnitude of the open loop gain = 1 (0 dB) o  M = phase margin is the phase of the open loop response -180 at the point the magnitude of the open loop response =1; the smaller the phase margin (closer to 180o) the more the peaking and ringing in the time domain  GM = the gain of the open loop response at the point the phase of the open loop response = -180o (second order systems have gain margin)  Can plot open loop gain and phase using a polar plot (Nyquist Chart)  If trajectory encircles –1 point, loop is unstable  -3dB = frequency is when the magnitude of the closed loop response is 3 down dB from the DC value, for a low pass function, or 3 dB down from the “high frequency” response for a high pass function  MP = the amount, in dB, the loop response rises above the DC or high frequency value  Important: The gain crossover and closed loop 3 dB frequency(s) are typically not the same 12
  13. 13. Basic Control Theory -4 dB Open Loop Gain 40 dB +4 dB dB G(s)*H(s) 0 dB peaking 20 dB -4 dB -8 dB Gain Crossover 0 dB -12 dB peak 3 dB Gain Margin frequency frequency -20 dB Normalized Closed G(s) H(s) Loop Gain 1 G(s) H(s) -40 dB Degrees Open Loop 0 Phase -90o Phase Margin -180o -270o -360o 13
  14. 14. Basic Control Theory -5  Non-Inverting Op-Amp (Series-Series Feedback) + + VOUT - VOUT VIN Rf - Rf VIN Ri Ri GBW Ri Rf G( s ) A(s ) , H (s ) Av 1 s Ri Rf Ri GBW G( s ) s T (s ) 1 G( s ) * H ( s ) GBW Ri 1 s Ri Rf s 0 1 Ri Rf Rf Av 1 Ri Ri Ri Ri Rf 14
  15. 15. Basic Control Theory -6  Inverting Op-Amp (Shunt-Shunt Feedback) Rf VIN VNI VNI VOUT - VOUT Ri Rf Ri + VOUT VIN VOUT A(s ) VNI ,VNI A(s ) Rf Av VOUT VOUT Ri VIN VOUT A(s ) A(s ) Ri Ri Rf + VOUT VOUT A(s ) Rf A(s ) VIN - Rf Rf Rf VIN Rf Ri Ri A(s ) Rf Ri Ri 1 A(s ) Ri Rf Ri Ri Rf G(s ) A(s ), H (s ) ,k Rf Ri Rf Ri GBW G(s ) Rf s T (s ) k 1 G(s ) H (s ) Rf Ri 1 Ri GBW Rf Ri s Rf Rf Ri Rf s 0,T (s ) Rf Ri Ri Ri 15
  16. 16. Basic Control Theory -7  General form for Inverting Op-Amp Zf Zi VOUT Zi - + Zg + VIN VIN - Zf Zg||Zf Zg||Zi Zf (s ) || Zg (s ) A(s ) T (s ) Zf (s ) || Zg (s ) Zi (s ) Zi (s ) || Zg (s ) 1 A(s ) Zf (s ) Zi (s ) || Zg (s ) 16
  17. 17. Basic Control Theory -8 5 dB(v_op3_out) 0 dB(v_op2_out) dB(v_op1_out) -5 -10 -15 Red – Amp1 -20 Blue – Amp2 -25 Purple – Amp3 1E6 1E7 1E8 2E8 freq, Hz 17
  18. 18. Model for Phase Lock Loop -1  Basic PLL  Input reference frequency  Phase detector (summing node)  Loop filter (typically integrator plus more)  Voltage controlled oscillator  Optional frequency divider  Linear Laplace Analysis  Based on classical control theory  Phase, (s), is the variable of interest; PLL is control system for phase signals; v(t) = Vosin( ot + (t))  Used to compute small signal performance for FM/ M modulation transfer functions, noise transfer functions, loop stability, linear hold in & lock range, linear tracking 18
  19. 19. Model for Phase Lock Loop -1  Basic PLL  Input reference frequency  Phase detector (summing node)  Loop filter (typically integrator plus more)  Voltage controlled oscillator  Optional frequency divider  Linear Laplace Analysis  Based on classical control theory  Phase, (s), is the variable of interest; PLL is control system for phase signals; v(t) = Vosin( ot + (t))  Used to compute small signal performance for FM/ M modulation transfer functions, noise transfer functions, loop stability, linear hold in & lock range, linear tracking 19
  20. 20. Model for Phase Lock Loop -2 Phase Detector Loop Filter VCO Reference fout = N*fref fref = 25 MHz 3000 MHz N 120 v(s) Phase Loop Filter VCO Detector + (s) KV K F(s) o(s) s i(s) - 1/N Divider 20
  21. 21. Model for Phase Lock Loop -3  Low Pass Transfer Function  Modulate the phase of the reference (“wiggle”) and look at the phase at the VCO output  VCO is virtual integrator in the phase domain  Note at “DC” the “gain’ is N  This will be significant for noise analysis v vco (t ) Vo sin( 0t (t )) o (s) G(s) KV Vc i (s) 1 G( s ) H ( s ) t Kv G(s) K F(s) (t ) KV Vc dt s H(s) 1/N KV (s ) Vc K F(s) Kv K F(s) Kv 1 s o (s) s s N KV N VCO(s ) i (s) Kv 1 Kv 1 1 K F(s) 1 K F(s) s s N s N o (s) G( s ) H ( s ) LP (s ) N i (s) 1 G( s ) H ( s ) 21
  22. 22. Model for Phase Lock Loop -4  High Pass Transfer Functions  Modulate the phase of the VCO and look at the phase at the output  This transfer function represents how the loop will act on VCO phase noise  Modulate the phase of the reference and look at the phase error  They are the same transfer function o (s) G(s) i (s) 1 G( s ) H ( s ) G(s) 1 Kv 1 H(s) K F(s) s N o (s) o (s) 1 HP (s ) v (s) (s) 1 K Kv 1 F(s) s N 22
  23. 23. Model for Phase Lock Loop -5  Frequency Model  Modulate the frequency of the reference and look at the frequency at the output  If input is step in frequency, this models small signal switching  Same low pass transfer function as for phase Phase Loop Filter VCO Detector 1 + K F(s) KV fi(s) s fo(s) - 1 1 1/N K F(s) K v s fo (s) s fi (s) 1 1 1 K F(s) K v s N fo (s) o (s) G( s ) H ( s ) LP (s ) N fi (s) i (s) 1 G(s ) H (s ) 23
  24. 24. Model for Phase Lock Loop -6  Type & Order  Type is the number of poles at DC (integrators); VCO counts as 1)  Order is total number of poles; order type (max. power of s in denominator)  Phase Detector  Different types (mixer, digital exclusive OR, digital phase/frequency)  Most common is digital phase frequency detector  Loop Filter (Should Be Called Loop Controller)  Determines type and order  Typically, passive filters are not used alone  Active integrator used with voltage output phase detector  Can use simple R-C integrator with current output (charge pump)  Can “mix & match” different types of filters; i.e. active integrator + passive lead lag  Can also include standard filters (Butterworth) 24
  25. 25. Model for Phase Lock Loop -6  VCO  Acts as integrator for phase signals  KV = MHz/V; assumed to be constant but not true for wide frequency range loops  Usually, as frequency of VCO increases, KV decreases  Divider  Division ratio = 1/N; assumed to be constant but not true for wide frequency range loops  As frequency increases, 1/N decreases  For wide range loops some compensation is necessary 25
  26. 26. Loop Controllers -1 26
  27. 27. Loop Controllers -2 27
  28. 28. Loop Controllers -3 28
  29. 29. Loop Controllers -4 29
  30. 30. PLL Configurations -1  Specifications  Uses ADI 4156 chip  Synergy 2 to 4 GHz VCO at 3 GHz  100 MHz reference to chip  25 MHz phase detector frequency  Methodology  Start with simple configuration  Explore more complicated configurations  Setting of loop BW relates to noise performance  Analyze final configuration in depth  Configurations for Current Output Phase Detectors  Output is current source with up and down summed together on chip  Simple R-C loop controllers gives type II, 2nd order  Parallel C gives type II, 3rd order  Additional R-C or R-L-C can be added 30
  31. 31. PLL Configurations -2  Why Op-Amp  Most single chip PLL’s are powered from a relatively low voltage (3.3, 5 volts)  This limits the tuning range to the compliance of the current source  Use op-amp as current to voltage converter  This has noise implications  Voltage Output Phase Detectors  Up and down have separate outputs  Need differential summing amplifier or differential integrator  Lead Lag Network  Inserted between op-amp and VCO  Prevents op-amp noise from modulating VCO essentially increasing the phase noise of the VCO  Can be “married” with R-C or R-L-C 31
  32. 32. PLL Configurations -3 Phase Detector +V Phase Detector +V K VCO K Rf_int Cf_int VCO Kv = VCC 132 MHz/v - Kv = Reference Reference 132 MHz/v fr = 25 MHz fr = 25 MHz + R_int VBB C_int Type II, 2nd Order N= N= 1/120 1/120 Cp_int Phase Detector +V Phase Detector +V K VCO K Rf_int Cf_int VCO Kv = VCC 132 MHz/v - Kv = Reference Reference 132 MHz/v fr = 25 MHz fr = 25 MHz + R_int Cp_int VBB C_int N= Type II, 3rd Order N= 1/120 1/120 32
  33. 33. PLL Configurations -4 Cp_int +V +V Phase Detector VCO Phase Detector Rf_int Cf_int K K VCO Kv = VCC 132 MHz/v - Kv = Reference R_vco Reference 132 MHz/v fr = 25 MHz fr = 25 MHz + R_vco R_int Cp_int C_vco VBB C_vco C_int Type II, 4th Order N= (2 real poles) N= 1/120 1/120 +V +V Phase Detector VCO Phase Detector Rf_int Cf_int K K VCO Kv = VCC L_vco 120 MHz/v - Kv = Reference R_vco Reference L_vco 132 MHz/v fr = 25 MHz fr = 25 MHz + R_vco R_int C_vco VBB C_vco C_int Type II, 4th Order N= (2 complex poles) N= 1/120 1/120 33
  34. 34. PLL Configurations -5 Resistive Lead-Lag Resistor - Lead-Lag Rld _ lg_ 1 Integrator VCO Att + R_ld_lg_2 Rld _ lg_ 1 Rld _ lg_ 2 R_ld_lg_1 1 R_ld_lg_2 zero Capacitor C_ld_lg_1 2 Rld _ lg_ 1Cld _ lg_ 1 Lead-Lag C_ld_lg_2 C_ld_lg_1 1 pole 2 (Rld _ lg_ 1 Rld _ lg_ 2 )Cld _ lg_ 1 2 pole Passive Filter Lead-Lag R_ld_lg_2 Capacitive Lead-Lag R_ld_lg_1 Cld _ lg_ 2 L_ld_lg Att = C_ld_lg_2 Cld _ lg_ 1 Cld _ lg_ 2 + C_ld_lg_1 1 zero 2 Rld _ lg_ 2Cld _ lg_ 2 1 pole 2 (Cld _ lg_ 1 Cld _ lg_ 2 )Rld _ lg_ 2 34
  35. 35. PLL Configurations -6 H Combination Sum & Loop Filter Rf Ri Ri Cf CLR D Q 0.0010 R C1 - SET Q 0.0005 + real(I_Probe1.i[0]) Loop Filter Ri Ri 0.0000 CLR D Q V C1 Rf -0.0005 SET Q RLEAK Phase Detector -0.0010 Cf 0 5 10 15 20 25 30 35 40 Post Detection Filter time, msec H Separate Sum & Loop Filter Rf_sum Ri_sum Ri_sum CLR D Q Rf_int R C1 Cf_int - Ri_int SET Q + - Ri_sum Ri_sum + CLR D Q Loop Filter V C1 Rf_sum SET Q Phase Detector Post Detection Filter 35
  36. 36. Simple PLL Analysis -1  Calculation of Component Values  Assume gain crossover (20 KHz)  Calculate Rf_int from gain crossover, KV and K  Rule of thumb: zero ¼ to ½ gain crossover; pole 1.5X to gain crossover; gives 35o to 55o phase margin  Calculate Cf_int, Cp_int assuming zero is 6.67 KHz and pole 60 KHz 36
  37. 37. Simple PLL Analysis -2  Closed Form Solution  Only for type II, 2nd order  Phase margin, natural frequency, damping factor, low pass response and low pass 3 dB point  Mathcad Analysis  Bode Plots (magnitude & phase) for open and closed loop gain  Solver function to find “true” gain crossover, phase margin, 3 dB points  The worse the phase margin, the greater the peaking in the closed loop response for both low pass and high pass; also more overshoot in the time domain response  The closer the zero is to gain crossover, the worse the phase margin  The closer the pole is to gain crossover, the worse the phase margin  Moving the zero closer to “DC” improves the phase margin  Moving the pole closer to improves the phase margin 37
  38. 38. Simple PLL Analysis -3 38
  39. 39. Simple PLL Analysis -4 39
  40. 40. Simple PLL Analysis -5 40
  41. 41. MathCad Linear Analysis -1 +5.0V Ip R_f_int +5.0V 15 dB VCC C_f_int R_ldlg_2 Pad 100 MHz Phase - R_ldlg_1 Oscillator R Frequency L_ldlg Detector + C_ldlg_2 VBB C_ldlg_1 Synergy 2 to 4 GHz VCO ADI 4156 FN N.f Chip From simple PLL Add lead-lag Add L-C filter 41
  42. 42. MathCad Linear Analysis -2 42
  43. 43. MathCad Linear Analysis -3 43
  44. 44. MathCad Linear Analysis -4 44
  45. 45. MathCad Linear Analysis -5 45
  46. 46. MathCad Linear Analysis -6 46
  47. 47. ADS Linear Modeling -1  Introduction  Used for open and closed loop response, noise analysis, and small signal time domain response  Just simple AC analysis  Models are not found in menus  They are sub-circuits from examples  Linear Components without Noise  LinearPFD is one input voltage controlled current source with, K transconductance in Amps/Radian  Linear PFD2 is two input voltage controlled current source with K transconductance, in Amps/Radian  LinearVCO is voltage controlled voltage source with KV, gain, in Hz/Volts and includes virtual integrator  LinearDivider is voltage controlled voltage source with 1/N equal to gain 47
  48. 48. ADS Linear Modeling -2 48
  49. 49. ADS Linear Modeling -3  Linear AC Analysis  Uses simple ADS linear models  Variables KV, IP, N, fX  Zeros and poles ratios in relation to fX  Calculate component values based on above constraints  Measure open and close loop gain using floating voltage source  ADS can automatically calculate gain crossover and phase margin  Also calculates high pass and low pass peak, peak frequency and 3 dB point  Searching for 3 dB points is tricky in that search only works on monotonic function; start searching at peaks Eqn low_pass_peak_index=max_index(low_pass) Eqn low_pass_sub_range=build_subrange(low_pass,low_pass_peak_freq,10e6) Eqn low_pass_peak_freq=freq[low_pass_peak_index] Eqn high_pass_sub_range=build_subrange(high_pass,0,high_pass_peak_freq) Eqn low_pass_peak_dB=low_pass[low_pass_peak_index] Eqn low_pass_3_dB=freq[low_pass_index+low_pass_peak_index] Eqn high_pass_peak_index=max_index(high_pass) Eqn low_pass_index=find_index(low_pass_sub_range,-3) Eqn high_pass_peak_freq=freq[high_pass_peak_index] Eqn high_pass_index=find_index(high_pass_sub_range,-3) Eqn high_pass_peak_dB=high_pass[high_pass_peak_index] Eqn high_pass_3_dB=freq[high_pass_index] 49
  50. 50. ADS Linear Modeling -3 50
  51. 51. Measurement of Loop Dynamics Set Input Z = 1 M HP 3577 Network Analyzer Source Out R In A In Ip R R_f_int 50 R 15 dB VCC C_f_int Pad - 100 MHz Phase - Oscillator R Frequency + Detector + R VBB R +5.0V Power R_ldlg_2 Splitter ADI 4156 FN N.f R_ldlg_1 L_ldlg Chip C_ldlg_2 C_ldlg_1 Synergy 2 to 4 GHz VCO 51
  52. 52. ADS Linear Modeling -4 fx IP KV N 20.00 k 2.464 m 131.8 120.0 R_int C_int R_ldlg_1 R_ldlg_2 C_ldlg_1 C_ldlg_2 L_ldlg 510.262 6.238E-8 247.302 3179.601 1.000E-7 1.001E-8 2.784E-4 45 -90 40 -100 35 -110 30 m2 -120 25 m1 -130 open_loop_phase-180 20 freq=19.95kHz -140 open_loop_gain 15 open_loop_gain=-0.001 -150 10 -160 5 m1 -170 0 -180 -5 -190 -10 -200 -15 -210 -20 m2 -220 -25 freq=19.95kHz -230 -30 open_loop_phase-180=-132.777 -240 -35 -250 -40 -260 -45 -270 1E2 1E3 1E4 1E5 1E6 freq, Hz Eqn gain_cross_over_index=find_index(open_loop_gain, 0) phase_margn gain_cross_over Eqn gain_cross_over=freq[gain_cross_over_index] 47.223 19952.623 Eqn phase_margn=open_loop_phase[gain_cross_over_index] 52
  53. 53. ADS Linear Modeling -5 5 0 m3 m4 -5 -10 high_pass_3_dB low_pass_3_dB -15 10715.193 36307.805 high_pass low_pass -20 m3 m4 -25 freq=10.72kHz freq=36.31kHz high_pass=-3.023 low_pass=-2.941 -30 -35 -40 -45 -50 1E2 1E3 1E4 1E5 1E6 freq, Hz low_pass_peak_dB low_pass_peak_freq high_pass_peak_dB high_pass_peak_freq 3.661 12022.644 2.690 38904.515 53
  54. 54. LT SPICE Linear Modeling -1 •Use voltage and current controlled sources to mimic VCO, divider, phase detector •Ideal Integrator using voltage controlled current source to emulate VCO virtual integrator •Separate sum for phase detector •Voltage controlled current source for charge pump •Floating voltage source for loop gain, high pass, low pass response 54
  55. 55. LT SPICE Linear Modeling -2 55
  56. 56. LT SPICE Linear Modeling -1 56
  57. 57. MathCad Transient Analysis -1 57
  58. 58. MathCad Transient Analysis -2 58
  59. 59. MathCad Transient Analysis -3 1 MHz step at output 59
  60. 60. ADS Transient Simulation(Step) -1  Transient Analysis  Uses same linear components as for AC analysis  Only for small signal performance with linear KV  Uses another VCO as reference  Step “reference” VCO with pulse of amplitude 1/N so output = 1  Output frequency is KV*v_tune as there is no access to the “frequency” output of the VCO  Monitor phase detector current which should go to zero when loop has settled  Graph frequency error abs(1-freq_out) on log scale to see fine grain settling performance  Settles to within 100 ppm in 315 S 60
  61. 61. ADS Transient Simulation(Step) -2 61
  62. 62. ADS Transient Simulation(Step) -3 Small Signal Transient Response 1.50 150 1.25 125 1.00 100 0.75 75 0.50 50 v_ref_freq*120 I_PD.i, uA 0.25 25 freq_out 0.00 0 -0.25 -25 -0.50 -50 -0.75 -75 -1.00 -100 -1.25 -125 -1.50 -150 0 25 50 75 100 125 150 175 200 225 250 time, usec 62
  63. 63. ADS Transient Simulation(Step) -4 Frequency Error 1 1E-1 m1 time= 315.3usec 1E-2 freq_error=1.062E-4 freq_error 1E-3 m1 1E-4 1E-5 0 50 100 150 200 250 300 350 400 450 500 time, usec 63
  64. 64. ADS Transient Simulation(Step) -5 Small Signal Transient Response 2.0 1.8 1.6 1.4 1.2 freq_out 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150 175 200 225 250 time, usec Vary filter poles from 1.5 to 5 fx 64
  65. 65. LT PSICE Transient Simulation -1 Virtual integrator at input to convert frequency step to ramp ramp 65
  66. 66. LT PSICE Transient Simulation -2 66
  67. 67. Phase Noise Basics -1  Frequency Domain  Uses small signal approximation for phase/frequency modulation  L(f) is normalized power spectral density (PSD) in one sideband referred to the carrier at a frequency offset f; called single sideband phase noise; units dBc/Hz  If you had an ideal, infinitely tunable receiver with a 1 Hz bandwidth; measure signal power at carrier then measure the noise sideband power relative to carrier this would be L(f)  If you had an ideal phase demodulator the output would be the “baseband” time domain voltage representing the phase noise; a low frequency spectrum analyzer is used to “extract” the frequency domain information, this would be S (f)  S (f) double sideband spectral density in (radians)2/Hz; normalized to 1 radian2  S (f) = 2*L(f)  Double sided noise, S (f), 3 dB more in power than single sideband noise, L(f) 67
  68. 68. Phase Noise Basics -2 Power Ps dBc Ideal Receiver with a Signal 1 Hz Bandwidth Noise f fo 1 Hz Low Frequency Ideal Phase Spectrum Signal Demodulator Analyzer 68
  69. 69. Phase Noise Basics -3  Phase Noise Regions  Amplifiers (RF and Op-Amps), dividers, phase detectors have flat and 1/f phase noise  Oscillators have flat, 1/f, 1/f2, 1/f3 regions "Low" Q Leeson's Model L(fm) dB f-3 2 f FkTB 1 fo 2f1/ f 1 fo f1/ f L(f) f -2 L(fm ) 1 f-4 40 dB/dec FkT/2P 2P f 3 4QL 2 fm 2 QL fm QL resonator loaded Q f f-3 30 dB/dec f1/f fc/2Q f 10 dB/div P resonator power "High" Q f1/ f flicker noise corner f-2 20 dB/dec f-3 fm offset from carrier L(f) fo RF frequency f-1 flicker phase f-1 FkT/2P F oscillator noise figure 10 dB/dec f-0 white phase 1 Decade/div f/2Q f1/f 69
  70. 70. Phase Noise Analysis -1  Analysis Methodology  Measure and/or get phase noise data L(f) from manufacturers data sheet(s) k1 k2 k3  Put noise in form of: L(f ) k0 f f2 f3  K0 is floor; k1 is flicker phase; k2 is white FM; k3 is flicker FM for L(f)  Multiply by 2 to get S (f), noise power k1 k2 k3 S (f ) 2 k0 f f2 f3  Coefficients represents 1 Hz intercepts for the different regions  Each noise source is modified by the appropriate closed loop transfer function to the loop output  Multiply the noise source equation by the |(transfer function)|2  Sum all the various noise powers to get composite PLL output phase noise 2  Subtract 3 dB to get back to L(f) S _ OUT (f ) S (f ) T ( j f ) 70
  71. 71. Phase Noise Analysis -2  Analysis Results - VCO Noise  Inside the loop bandwidth, the loop will reject VCO noise  The “rejection” is the magnitude of the high pass transfer function or ~ the difference between 0 dB and the value of the open loop transfer function  Between gain crossover and the zero frequency, the loop can reject VCO noise at 20 dB/decade  Between the zero frequency and “DC”, the loop can reject VCO noise at 40 dB/dec  Best to put the zero as close to gain crossover as possible without compromising the phase margin 71
  72. 72. Phase Noise Analysis -3  Analysis Results - Inside the Loop Noise Sources  The reference noise, referred to the phase detector frequency, divider noise and phase detector noise can all be “lumped” together  Outside the loop bandwidth, the loop will reject this noise  At “DC” the multiplication is N  The “rejection” is the magnitude of the low pass transfer function or ~ the difference between 0 dB and the value of the open loop transfer function  Between gain crossover and the 1st pole frequency, the loop can reject this noise at 20 dB/decade  Between the 1st pole frequency and the loop can reject VCO noise at 40 dB/dec assuming only 1 additional polse  Best to put the polse as close to gain crossover as possible without compromising the phase margin 72
  73. 73. Phase Noise Analysis -4  General Observations  The optimum loop bandwidth is where the sum of all the inside the loop bandwidth noise sources multiplied by N equals the VCO noise  Not hard and fast rule  Sometimes a narrower loop bandwidth is required to prevent “pollution” of VCO noise at higher offsets  Sometimes most important quantity is integrated phase noise; especially for digital communications systems  The most important thing is to keep N as small as possible 73
  74. 74. MathCad Phase Noise Modeling -1 +V Rf_int Cf_int VCO VCO Noise Reference 25 MHz C_ldlg2 R= VCC - Kv = 1/4 R_ldlg1 L_ldlg R_ldlg2 132 MHz/v + C_ldlg1 VBB Reference Noise N= 1/120 100 MHz Reference Chip Noise 74
  75. 75. MathCad Phase Noise Modeling -2 75
  76. 76. MathCad Phase Noise Modeling -3 76
  77. 77. MathCad Phase Noise Modeling -4 77
  78. 78. MathCad Phase Noise Modeling -5 78
  79. 79. MathCad Phase Noise Modeling -6 79
  80. 80. MathCad Phase Noise Modeling -7 80
  81. 81. ADS Phase Noise Modeling -1  Linear Components with Noise Slopes  Has same gain as linear components  Include terms for flat, 1/f, 1/f2, 1/f3, and more (not usually necessary)  If you know a point (frequency and dBc/Hz) that is in each region, the device is completely characterized  The noise is entered in L(f), but 3 dB is subtracted from the final noise results  Can also use noise equation; set all frequencies to 1 Hz and enter L0=20*log(k0), L1=20*log(k1), etc.  There is no phase detector model, but a divider with N=1 can be used 81
  82. 82. ADS Phase Noise Modeling -2 82
  83. 83. ADS Phase Noise Modeling -3  Linear Components with Noise  LinDiv_wNoise is same as LinDiv_wNoiseSlps  LinVCOwNoise is same as LinVCOwNoiseSlps  LinearPFDwNoise is current output PD with added flat noise current at output  LinearPFDwNoiseV is voltage output PD with added flat noise voltage at output 83
  84. 84. ADS Phase Noise Modeling -4 Eqn Ref_noiz=dB(ref_noiz.noise)-3 Eqn Dividr_noiz=dB(dividr_noiz.noise)-3 Eqn VCO_noiz=dB((vco_noiz.noise))-3 Eqn Ped_noiz=dB(sqrt(ref_noiz.noise**2+dividr_noiz.noise**2))-3+dB(N0) Eqn Opt_BW_noiz=VCO_noiz-Ped_noiz Eqn opt_bw=freq[opt_bw_index] Eqn opt_bw_index=find_index(Opt_BW_noiz,0) -60 -66 -72 -78 -84 -90 -96 -102 -108 Dividr_noiz VCO_noiz Ped_noiz Ref_noiz -114 opt_bw -120 -126 19952.623 -132 -138 -144 -150 -156 -162 -168 -174 -180 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 84
  85. 85. ADS Phase Noise Modeling -5 85
  86. 86. ADS Phase Noise Modeling -6 fx IP KV N 20.00 k 2.464 m 131.8 120.0 R_int C_int C_ldlg_1 C_ldlg_2 R_ldlg_1 R_ldlg_2 L_ldlg 510.3 62.38 n 100.0 n 10.01 n 247.3 3.180 k 278.4 u 45 -90 40 -100 phase_margn gain_cross_over 35 -110 30 m2 47.223 19952.623 -120 25 -130 open_loop_phase-180 20 -140 15 -150 open_loop_gain 10 -160 5 m1 -170 0 -180 -5 -190 -10 -200 -15 -210 -20 m2 m1 -220 -25 freq= 19.95kHz freq= 19.95kHz -230 -30 open_loop_phase-180=-132.777 open_loop_gain=-0.001 -240 -35 -250 -40 -260 -45 -270 1E2 1E3 1E4 1E5 1E6 freq, Hz Eqn gain_cross_over_index=find_index(open_loop_gain, 0) Eqn gain_cross_over=freq[gain_cross_over_index] Eqn phase_margn=open_loop_phase[gain_cross_over_index] 86
  87. 87. ADS Phase Noise Modeling -7 ADI Loop Phase Noise at 3 GHz -80 -85 -90 -95 -100 -105 -110 Noise in dBc/Hz -115 -120 -125 -130 -135 -140 -145 Eqn loop_out_noiz=dB(loop_out.noise)-3 -150 -155 -160 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 87
  88. 88. LT Spice Phase Noise Modeling -1 noise noise -20 dB/dec = f-2 R R flat = f0 resistor _ noise frequency frequency noise noise 10 dB/dec= f-1 -30 dB/dec = f-3 diode _ noise frequency frequency 2 K f ID in 2qID SPICE diode model f 2 2 2 2 kT K f ID en RD i n for diode, ignore 2qID qID f 2 en 4kTR for resistor 88
  89. 89. LT SPICE Phase Noise Modeling -2  Theory  Can model noise sources in conjunction with loop to get accurate phase noise plot  Use resistor to get “flat” noise  Use diode to get 1/f noise  Use resistor & integrator to get 1/f2 noise  Use diode & integrator to get 1/f3 noise 89
  90. 90. LT SPICE Phase Noise Modeling -3 90
  91. 91. LT SPICE Phase Noise Modeling -4 91
  92. 92. LT SPICE Phase Noise Modeling -5 Divider Noise 92
  93. 93. LT SPICE Phase Noise Modeling -6 VCO Noise 93
  94. 94. LT SPICE Phase Noise Modeling -7 94
  95. 95. Phase Noise Measurement -1 95
  96. 96. Phase Noise Measurement -2 96
  97. 97. Phase Noise Measurement -3 Block Diagram of E5500 PNTS 97
  98. 98. Phase Noise Measurement -4 98
  99. 99. Phase Noise Measurement -5 Block Diagram of E5052A SSA 99
  100. 100. ADS Non-Linear Modeling 100
  101. 101. Harmonic Balance -1  Analyze circuits with Linear and Non-linear components  You define the tones, harmonics, and power levels  You get the spectrum: Amplitude vs. Frequency  Use only Frequency domain sources  Data can be transformed to time domain (ts function)  Solutions use Newton-Raphson technique  Automatically chooses best mode for convergence  Transient can be run from HB controller (freq dividers)  Similar to Spectrum Analyzer 101
  102. 102. Harmonic Balance (Flow Chart) -2 Simulation Frequencies Start Number of Harmonics DC analysis Number of Mixing Products always done Linear Components Nonlinear Components Measure Linear Measure Nonlinear Circuit Currents Circuit Voltages in the Frequency-Domain in the Frequency-Domain • Inverse Fourier Transform: Nonlinear Voltage Now in the Time Domain • Calculate Nonlinear Currents • Fourier Transform: Nonlinear Currents Now back in the Frequency Domain Test: Error > Tolerance: if yes, modify & recalculate Kirchoff’s Law if no, then Stop= correct answer. satisfied! 102
  103. 103. Harmonic Balance (First and Last Iterations) -3 IR IY-port IC IL ID Start in the Test uses Frequency Domain Calculate currents Convert: ts -> fs (Kirchoff’s law): If I error is not near zero, then iterate again. Initial Estimate: IR IC IL ID IY spectral voltage If within tolerance Last Estimate IR IC IL ID IY then V Final with least error Solution 103
  104. 104. Circuit Envelope -1  What is Circuit Envelope ?  Time samples the modulation envelope (not carrier)  Compute the spectrum at each time sample  Output a time-varying spectrum  Use equations on the data  Faster than HB or Spice in many cases  Integrates with System Simulation & Agilent Ptolemy  Also, Envelope can be used for PLL simulations,lock time, spurious signals, modulation in the loop 104
  105. 105. Circuit Envelope -2 Captures time and frequency characteristics: dBm (fs (Vout[1])) 105
  106. 106. Circuit Envelope -3 Example setup: one tone with 3 harmonics Stop time – Determines resolution bandwidth of spectrum. – Large enough to resolve spectral components of interest. Time step – Determines modulation bandwidth of the spectrum. – Small enough to capture highest modulation frequency. Stop Time Resolution BW Time Modulation BW step 106
  107. 107. Circuit Envelope -4  Envelop Set-Up  0 is baseband  Freq[1] is 1st frequency; order is number of harmonics  Freq[2] is 2nd frequency; order is number of harmonic  Stop is resolution BW  Step is maximum frequency 107
  108. 108. Non-Linear Components (Phase Detectors) -1 PhaseFreqDet2  Models classic D flip-flop phase detector  Outputs are zero impedance complimentary voltage sources  Inputs are impedance; trigger is 0.5 volts  Can be used for transient and envelope simulation  Also has dead zone and jitter in pS  Jitter is white out up to the ½ reference sampling frequency  Can be used to model reference clock feed-thru  The output of this model is a pulse train whose average value is proportional to the input phase difference, and may contain significant signal energy at the reference clock rate, and at clock harmonics  Need to filter before using in PLL 108
  109. 109. Non-Linear Components (Phase Detectors) -2  PhaseFreqDet2  Time step must be less than one-half the reference period, and typically less than one-tenth the period.  Linear interpolation is used to get much finer time resolution than the analysis time step  Input waveforms should be sawtooth’s to minimize simulator jitter  Sine waves will work with a small enough time step; square waves should be avoided  PhaseFreqDetCP  Charge pump version  Output current is ± IP; but also can be variable as, for example, a function of the output voltage to model saturation effects  Can be used for transient and envelop simulation  Also has dead zone and jitter in pS  Jitter is white out to the reference sampling frequency 109
  110. 110. Non-Linear Components (Phase Detectors) -3  PhaseFreqDetTuned  Tuned Phase Detector  This tuned phase-frequency demodulator is used with circuit envelope simulation that models the ideal behavior of the phase frequency detectors used in phase-locked loops (does not work in transient mode)  Need to specify frequency  Sensitivity is in mA/degree  It generates a baseband output signal equal to the phase difference between the VCO and REF inputs  Does not include reference frequency feed thru effects  Time step can be greater than the reference frequency and only a function of the PLL bandwidth  Faster simulation 110
  111. 111. Non-Linear Components (Phase Detectors) -4 111
  112. 112. Non-Linear Components (Phase Detectors) -5 112
  113. 113. Non-Linear Components (Phase Detectors) -6 Charge Pump PD with Reference Information 4 2.0 1.5 2 1.0 I_PD_1.i, mA I_PD_2.i, mA v_VCO_N, V v_Ref, V 0.5 0 0.0 -0.5 -2 -1.0 -1.5 -4 -2.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 time, usec Voltage Output PD with Reference Information 4 1.5 2 1.0 v_VCO_N, V v_Ref, V v_Q1, V v_Q2, V 0 0.5 -2 0.0 -4 -0.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 time, usec 113
  114. 114. Non-Linear Components (Phase Detectors) -7 1.0 0.5 v_pd_1, V v_pd_2, V 0.0 -0.5 -1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 time, msec 114
  115. 115. Non-Linear Components (Phase Detectors) -8 115
  116. 116. Non-Linear Components (Phase Detectors) -9 0.0010 0.0005 real(I_Probe1.i[0]) 0.0000 -0.0005 -0.0010 0 5 10 15 20 25 30 35 40 time, msec 116
  117. 117. Non-Linear Components (Phase Detectors) -10  Why are Reference and Divided VCO Signals Sawtooth Waves?  Ideally, charge pump current pulse width is equal to time difference between PDF input signals  In a simulation, this width must be a multiple of the timestep  Envelope simulation uses interpolation to get finer resolution than the timestep  Sawtooth waves are easiest to interpolate  Ideal current pulse can’t be simulated  If the current pulse is 1 timestep wide, the amplitude is reduced to give the same area as an ideal pulse 117
  118. 118. Non-Linear Components (VCO and Divider) -1  Case 1  fVCO = 1 GHz, KV = 100 MHz/V, V = 0.1 V, N=100, N = 10  Envelope simulation with only fVCO specified  Time step << 1/fREF  Slope of VCO phase gives VCO frequency  From 0 to 1 S and from 2 to 3 S, VCO frequency is 1 GHz  At t = 1 S VCO frequency changes 1 GHz to 1.01 GHz because tune voltage increases by 0.1 volts  The phase slope indicates a 10 MHz frequency change has occurred  The frequency of the divided output changes from 10 MHz to 10.1 MHz  At t = 3 uS, the VCO frequency is back to 1 GHz, but the N changes by 10  The frequency of the divided output changes from 10 MHz to 9.09 MHz 118
  119. 119. Non-Linear Components (VCO and Divider) -2 119
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PLL Class at European Microwave Conference - October 2011

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