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# 3Sem-Logic Design Notes-Unit7-Sequential Design

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VTU 3rd Semester E&C Department, Logic Design Unit 7 Detailed Notes

VTU 3rd Semester E&C Department, Logic Design Unit 7 Detailed Notes

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## 3Sem-Logic Design Notes-Unit7-Sequential DesignDocument Transcript

• 12       ODD     SEMESTER                                  LOGIC  DESIGN-­‐3-­‐CLASS  NOTES  –  UNIT7            Shivoo  Koteshwar  Professor,  E&C  Department,  PESIT  SC      Sequential  Design  1     • Introduction   • Mealy  and  Moore  Models   • State  Machine  Notation   • Synchronous  Sequential  Circuit  Analysis    Reference  Books:   • Digital  Logic  Applications  and  Design”,  John  M  Yarbrough,  Thomson  Learning,  2001   • “Logic  and  computer  design  Fundamentals”,  Mono  and  Kim,  Pearson,  Second   edition,  2001    UNIT  7:    Sequential  Design  -­‐  I:  Introduction,  Mealy  and  Moore  Models,  State  Machine  Notation,  Synchronous  Sequential  Circuit  Analysis,  [(Text  book  1)  6.1,  6.2,  6.3]                                    6  Hours      P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Sequential Machine:A sequential circuit is said to be a synchronous sequential circuit if itsatisfies the following conditions: • There is at least one flip-flop in every loop • All flip-flops have the same type of dynamic clock • All clock inputs of all the flip-flops are driven by the same clock signalThere are two versions of this model called the Mealy Model and the Mooremodel. The only difference is in the way the output signals are generated. • Mealy Model: Outputs depend on current state and inputs • Moore Model: Outputs only depend on current stateDifferences between Moore and Mealy Models:   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    State Machine Notation:Input Variable: All variables that originate outside the sequential machine(SM)Output Variable: All variables that exit the SMState Variable: The output of memory (FF) defines the state of a SM.Excitation Variable: Inputs to memory (FF)State: The state of the SM is defined by the content of memoryFlip Flop   Shivoo  Koteshwar’s  Notes                                          3                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0     IMPLEMENTING A STATE DIAGRAM USING J-K FLIPFLOPThis is a 5-step process: 1. Understand the State Diagram 2. Write the State Table 3. Encode the states and rewrite the state table 4. Select FF to be used a. Derive the excitation Table (Optional if you remember it) b. Fill the excitation variable (Inputs for Flip-Flops) c. Simplify using K-Maps 5. Write the schematic diagramStep1: Understand the State DiagramLooking at the state diagram, we notice that it’s a mealy modelimplementation. The state diagram shows that there are 4 states (A, B, Cand D), 2 input variables (x and y) and one output (z)Note: In the State table, PS = Present State & NS = Next State   Shivoo  Koteshwar’s  Notes                                          4                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step2: Write the State Table:Step3: Encode the states and rewrite the state table2n states are possible with n number of Flip Flops. So 4 states require 2 Flip-Flops.   Shivoo  Koteshwar’s  Notes                                          5                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step4: Select FF to be usedAs in this problem, we are supposed to implement using JK Flip-Flops, letsfollow these 3 steps: a. Derive the excitation Table b. Fill the excitation variable c. Simplify using K-Maps   Shivoo  Koteshwar’s  Notes                                          6                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step4(a): Deriving Excitation Table for J-K Flip-FlopFrom the above, we can write the following table:Expanding this we can write the table as below:   Shivoo  Koteshwar’s  Notes                                          7                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    In the above table, we notice the following: • For both J=0, K=0 and J=0, K=1, when Present state is 0, next state is 0. This means, irrespective of value of K, when J=0 and Present state is 0, the Next state will be 0 OR J=0, K=d, PS=0 => NS=0 • For both J=0, K=0 and J=1, K=0, when Present state is 1, next state is 1. This mean, irrespective of value of J, when K=1 and Present state is 1, the Next state will be 1 OR J=d, K=0, PS =1 => NS= 1 • For both J=0, K=1 and J=1, K=1, when Present state is 1, next state is 0. This means irrespective of value of J, when K=0 and Present state is 1, the Next state will be 0 OR J=d, K=0, PS=1 => NS=0 • For both J=1, K=1 and J=1, K=0, when Present state is 0, next state is 1. This means, irrespective of value of K, when J=1 and Present state is 0, the Next state will be 1 OR J=1, K=d, PS=0 => NS=1We can re-write the table as below:Step  4(b): Filling the Excitation Table (Inputs for Flip-Flops)In the state table derived earlier, we have PS=FAFB (Outputs of the flip-flops) and state variables (Next State). Now using these two and theexcitation table of J-K Flip-Flop, we need to derive the inputs or theexcitation of the 2 Flip-Flops to be usedFor example, for row1, bit 1 (FA), to get Present State=0 and Next State=0,we need JAKA=0d. Similarly fill the JAKA column using bit 1 of FAFB column& NS column and JBKB column using bit 0 of FAFB column & NS column   Shivoo  Koteshwar’s  Notes                                          8                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    When we fill the entire table, we get the following:   Shivoo  Koteshwar’s  Notes                                          9                                                                                          shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step  4(c): Simplify using K-Maps         Shivoo  Koteshwar’s  Notes                                          10                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step5: Write the Schematic Diagram   Shivoo  Koteshwar’s  Notes                                          11                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Synchronous Sequential Circuit AnalysisDesign is a synthesis process to take pieces and put them together to form afunctional whole. Analysis, on the other hand, requires breaking the wholeinto component pieces • Synthesis process is easier then analysis because the designer’s reasons for making a particular decision are clear • Here we will start with a circuit and proceed to determine the state table or state diagramAnalysis is a 6 step process 1. Understand the schematic diagram 2. Derive the equations for inputs of flip-flops (Excitation variables) and outputs 3. Using the equation, fill the K-Maps 4. Write the State Table a. Using K-Maps, fill the state table b. Derive the excitation table for JK Flip-Flop (Optional if you remember it) c. Fill the state variable (Next State) 5. Decode the states and rewrite the state table 6. Write the State Diagram   Shivoo  Koteshwar’s  Notes                                          12                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step1: Understand the Schematic DiagramLooking at the schematic diagram, we notice that it’s implemented using JKFlip-Flops. The schematic shows that there are 2 Flip-Flops so possiblestates would be 4 – A, B, C and D. We also notice that there are 2 inputs xand y and one input, z.Step2: Derive the equations for inputs of flip-flops (Excitationvariables) and outputs   Shivoo  Koteshwar’s  Notes                                          13                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step3: Using the equation, fill the K-MapsStep4: Write the State TableThis is a 3 step process: a. Using K-Maps, fill the state table b. Derive the excitation table for JK Flip-Flop (Optional if you remember it) c. Fill the state variable (Next State)   Shivoo  Koteshwar’s  Notes                                          14                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step4(a): Using K-Maps, fill the State TableStep4(b): Deriving Excitation Table for J-K Flip-FlopFrom the above, we can write the following table:   Shivoo  Koteshwar’s  Notes                                          15                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Expanding this we can write the table as below:In the above table, we notice the following: • For both J=0, K=0 and J=0, K=1, when Present state is 0, next state is 0. This means, irrespective of value of K, when J=0 and Present state is 0, the Next state will be 0 OR J=0, K=d, PS=0 => NS=0 • For both J=0, K=0 and J=1, K=0, when Present state is 1, next state is 1. This mean, irrespective of value of J, when K=1 and Present state is 1, the Next state will be 1 OR J=d, K=0, PS =1 => NS= 1   Shivoo  Koteshwar’s  Notes                                          16                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0     • For both J=0, K=1 and J=1, K=1, when Present state is 1, next state is 0. This means irrespective of value of J, when K=0 and Present state is 1, the Next state will be 0 OR J=d, K=0, PS=1 => NS=0 • For both J=1, K=1 and J=1, K=0, when Present state is 0, next state is 1. This means, irrespective of value of K, when J=1 and Present state is 0, the Next state will be 1 OR J=1, K=d, PS=0 => NS=1We can re-write the table as below:Step  4(c): Filling the State Variable (Next State)In the state table derived earlier, we have PS=FAFB (Outputs of the flip-flops) and inputs to Flip-Flops. Using these two and the excitation table ofJ-K Flip-Flop, we need to derive the State variables (Next State)For example, for row1, bit 1 (FA), with Present State=0 and JAKA=01, thenext state would be 0.Similarly fill the NS bit1 column using bit 1 of FAFB column & JAKA columnand NS bit0 column using bit 0 of FAFB column & JBKB column.   Shivoo  Koteshwar’s  Notes                                          17                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    We get the following table:Step  5: Decode the states and rewrite the state table   Shivoo  Koteshwar’s  Notes                                          18                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    In the above state table, we notice that in each state, all possiblecombinations of inputs (xy) are covered i.e 4 possible combinations. Youcan write the state diagram using the above table.Optional: For ease of writing the state diagram, we can further try to reducethe number of arcs from each state (circle) by studying the state tablee.g. In State A, irrespective of y, when x=0, it stays at A and when x=1, itgoes to B. So you can reduce from 4 arcs to 2 arcs, eliminate 2 arcs.Similarly you can do the same at state BSo the final table looks like   Shivoo  Koteshwar’s  Notes                                          19                                                                                    shivoo@pes.edu
• Logic  Design  (3rd  Semester)                                                                                                                            UNIT  7  Notes  v1.0    Step6: Write the state diagram   Shivoo  Koteshwar’s  Notes                                          20                                                                                    shivoo@pes.edu