This is my DVLSI Project Presentation on I2C Protocol.

1. Mr.Tejas Dave Chovatiya Ravi Jitendra Edle Sachin Nigam Prepared by:- Guide by:- “ I2C Bus Protocol Implementation” THAKUR INSTITUTE OF CAREER ADVANCEMENT

3. Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C Master Core WISHBORN Interface Prescale Register Command Register Transmit Register Status Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator

4. External connection

5. Register List Status Register R 8 100 SR Command Register W 8 011 CR Receive Register R 8 110 RXR Transmit Register W 8 101 TXR Control Register RW 8 Null CTR Clock Prescale Register Hi-byte RW 8 001 PRERhi Clock Prescale Register Lo-byte RW 8 000 PRERlo Description Access Width Address Name

6. Control register

7. Transmit Register Receive Register

8. Command Register

9. Status Register

11. I2C Protocol 1. Master sends start condition (S) and controls the clock signal 2. Master sends a unique 7-bit slave device address 3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit 4. Slave with matching 7-bit device address always sends acknowledge bit (ACK) 5. Transmitter (slave or master) transmits 1 byte of data

12. I 2 C Protocol (cont.) 6. Receiver issues an ACK bit for the byte received 7. Repeat 5 and 6 if more bytes need to be transmitted 8. Master always sends stop condition (P) a. For write transaction (master transmitting), master issues stop condition (P) after last byte of data. b. For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done

14. Bit Command Controller I

15. A B I 2 C Signals C D I

24. Addr 000 Addr 001 Addr 011 Addr 100 Addr 101 Addr 110 SDA SCL Internal structure I2C Master Core WISHBORN Interface Prescale Register Command Register Transmit Register Status Register Receiver Register Data IO Shift Register Bit & Byte Controller Clock Generator

26. Thank you