Defect-Aware Design Paradigm for Reconfigurable Architectures
1. Defect-Aware Design
Paradigm for Reconfigurable
Architectures
Rahul Jain, Anindita Mukherjee, Kolin Paul
Indian Institute of Technology, Delhi
Conference Travel Supported by XILINX-CMC, Hydrabad,
India
2. Introduction
VLSI Technology progress
for finer dimensions and
larger chip area has lead to:
More Complex Fabrication
Techniques
High defect densities
High Manufacturing Costs
Decrease in Critical Defect
Size
Increase in defect/fault- Milton Godwin et al, “Examining
upcoming yield enhancement
sourcing complexity factor challenges in the 2001 roadmap”,
Micro Magazine, 2002 Issue
Lower Yield
3. Introduction
Low Yield problem can be overcome by
Fault Tolerance
Defect Tolerance
This Relaxes Stringent Constraints on
Manufacturing Processes
Lowers Cost
A tradeoff between process technology
complexity in terms of yield and post-
fabrication complexity in terms of defect-
tolerance
4. Motivation
Defect-tolerance more important as we near
lithographic limits
We are moving towards era of molecular electronics
CAEN- Chemically assembled electronic
nanotechnology
Expected to have about 10% defects
Reconfigurable Devices (e.g. FPGA’s) obvious
choice to incorporate post-fabrication defect-
tolerance
Area Penalty
Time Penalty
5. Defect Aware Design Flow
FPGA used as the Reconfigurable Fabric
PnR now expects a Defect Map as input
Observations:
Interconnect defects are the bottleneck as they
occupy the most area
Defect Distribution is clustered [C. H. Stapper 89]
Congestion Aware Placement gives best Results
6. Experimental Setup
VPR used as the FPGA PnR infrastructure
placement and routing tool for array-based
FPGAs from University of Toronto
VPR modified to accept Defect Map as input
Defects mapped to CLBs and interconnects
Defective components assigned ZERO
capacity, hence cannot be used in PnR
7. Motivational Example
Conducted to Study the PnR behaviour for
different Defect Densities
Uniform Random Defect distribution for CLB’s
and Routing Resources (RR) assumed
Expected Behaviour:
Placement always possible if enough defect-free
CLB’s available
As we increase the defect density of RR the circuit
gets unroutable
8. Motivational Example
Observed Behavior
Expected behavior most of the time
But some cases where Circuit is routable for Higher CLB
defects with same or even Higher RR defects
Reason for this is that at Higher CLB defects the
Placement is more distributed and hence no/less
congestion
Conclusion
Area Penalty Inevitable
Placement is more distributive hence Time Penalty incurred
Congestion Awareness needed at the Placement Step
9. Defect Map Generation
Simulation Model by C.H Stapper used
Model takes chip as a 2D Grid Array
Uses a Symmetrical Bivariate Gaussian
Distribution
Cluster Shaping done on this Distribution
Clusters randomly Rotated and Displaced
10. Mapping Defects on FPGA Fabric
FPGA Fabric divided into a
2-D Array of cells of side
equal to interconnect width
Interconnect modeled as 1-
D Array of cells
CLB modeled as 2-D array
of cells
Defect Map Generated for
this FPGA 2D-Array
If any defect maps to any
Resource, Assign Zero
capacity to the Resource
11. VPR Cost Functions
Experiment Conducted to find the best PnR
methodology in Defect Aware Environment
VPR uses Simulated Annealing for Placement and
Path_Finder Algorithm for routing
4 types of Placement Cost Functions
Bounding Box with Linear Cost function (BB_L)
Bounding Box with Non-Linear Cost function (BB_NL)
Net_timing_driven (Net)
Path_timing_ driven (Path)
12. VPR Cost Functions
Comparison of 4 Cost Functions
T_Crit (10-8 s)
chan
Bench nx/ny
wd BB_NL BB_L Net path
gcd 15 6 5.70 5.49 NA NA
scf 23 11 5.57 NA NA NA
table3 27 11 7.58 8.32 6.28 6.0
table5 22 11 8.07 8.14 NA NA
apex1 21 7 8.55 NA NA NA
13. RISA
Bounding Box, Non Linear Algorithm gives
the best results
It is an implementation of cost-function RISA
[Cheng, ICCAD’94]
RISA balances demand and supply over an
array of NxN regions
RISA performs better than others because it
is congestion aware
RISA takes routability into account while
doing placement
14. RISA
Demand:
w×l w× l
D i , horiz = q × ; D i ,vert = q ×
Y×L X ×W
k k
Chih-Liang Eric Cheng, “RISA:
Supply: accurate and efficient placement
routability modeling”, Proceedings of
v Sij = Tv / N h Sij = Th / N the 1994 IEEE/ACM international
conference on Computer-aided design
15. CA-RISA
Supply reduced due to defects
Penalize defects with a weighing factor W
Large value of W pushes the placements
away from highly defective regions
h Sij = Th / N − W * ∑∑ N hdef
i j
v Sij = Tv / N − W * ∑∑ N vdef
i j
25. Future Work
Proposed Methodology requires the circuit to
be Placed and Routed for Each Chip
Separately
Not a Feasible Option
Incorporate Defect Map into the Flow as late
as possible
One Possibility is to do PnR for non-defective
fabric and at the last step incrementally map
the solution to the defective fabric
26. Conclusion
CA-RISA proposed and compared to existing
methodology
This is not a Complete Solution
A motivation for Defect Aware Design
Paradigm
Tries to highlight the bottlenecks of the
Present Methodology
