3. INTRODUCTION
Motion Estimation is one of the most important block Video
compression system. [5]
Block-Matching algorithm (BMA) used for motion estimation (ME) in
various video coding.
FS is highly computational so, we use fast BMA Techniques.
Adaptive Rood Pattern Search (ARPS) most efficient in terms of
the computational speed and achieves good PSNR.
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4. OBJECTIVE
• To design an efficient architecture for block-matching motion estimation
using ARPS search technique
• To enhance the architecture for mesh based motion estimation which will
help to incorporate the non-translational motions such as shear, rotation,
zoom etc. present in the video.
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12. Adaptive Rood Pattern Search method
• Two main issues are:
1) Pre-determining the motion behavior of current block ?
2) Size and shape of the search pattern ?
• For First issue,
Current block’s motion behavior can be predicted by its neighboring blocks’ MVs.
• For Second issue, two types of search patterns are used:-
1. Adaptive rood pattern (ARP)
2. Small search pattern (URP)
• Prediction of the target motion vector is achieved with the help of ROS (region of search).
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13. Adaptive Rood Pattern
• Predicted MV along with four-armed rood pattern is added
into ARP which is similar to target MV.
• ARP’s size,
L = Max {| MVpredicted(x)|,| MVpredicted(y)|}
• Leftmost blocks in each frame have a fixed arm length of 2
pixels.
• ARP has either 5 (non overlapping) or 4 (with overlapping)
search points in the initial search stage.
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Figure. 1. Adaptive Rood Pattern
[1][2]
14. Fixed Pattern – for refined search
• Initial search, leads to new search center.
• Small search pattern (URP) is used for local refined
search unrestrictedly and repeatedly .
• MME point of current step becomes center for next
iteration until MME point is at the center of the fixed
pattern.
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Figure. 2. Two type of fixed Search Patterns
[1][2]
24. FUTURE WORK
Optimization of the proposed Architecture in terms of speed, power
and area. Use of CIF frames as test sequence.
Developing an Architecture for Fixed Mesh based motion estimation
using ARPS technique.
Enhancing the Fixed Mesh into Adaptive Mesh (Hierarchical) for
accurate motion estimation.
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25. REFERENCES
[1] Yao Nie and Kai-Kuang Ma “Adaptive Rood Pattern Search for Fast Block-Matching Motion Estimation”
IEEE Transactions, Image Processing, Vol. 11, No. 12, pp. 1442-1448, December 2002.
[2] Kai-Kuang Ma and Gang Qiu “An Adaptive Rood Pattern Search For Fast Block-Matching Motion
Estimation in JVT/H.26L” IEEE Conference, Circuits and Systems, Vol. 2, pp. II – 708 – II – 711, 2003.
[3] Mohammed Sayed and Wael Badawy “An Affine-Based Algorithm and SIMD Architecture for Video
Compression with Low Bit-Rate Applications” IEEE Transactions, Circuits and Systems for Video
Technology, Vol. 16, No. 4, April 2006.
[4] Wael Badawy, Guoqing Zhang and Magdy Bayoumi “VLSI Architecture for Hierarchical Mesh Based
Motion Estimation”, IEEE conference, Signal processing systems, pp. 110-119, October 1999.
[5] Iain E.G. Richardson, “H.264 and MPEG-4 Video Compression Video Coding for Next generation
Multimedia”, 2003.
[6] S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,” second edition, Prentice Hall
publication, February 2003.
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Applications such as video-on-demand, video conferencing, streaming video, digital TV/HDTV broadcast, CD/DVD storage, etc., demands amount of reduction in video data for storing or transmitting the video efficiently
As Speed and accuracy of pattern based algorithms depend on pattern size and magnitude of the target motion vector.
Adjacent macro block’s belong to same moving object have similar motions so they can be used for prediction of target motion vector.
DESCRIPTION OF THE BLOCKS IN THE PROPOSED ARCHITECTURE
FRAME STORAGE RAM’s :-
The pixel values of the current and the reference frames are stored in two RAMs each of size 256 * 256 words having 8-bit width. Each word in the memory (corresponding to each pixel in the stored frame) is addressed by a 16-bit address in such a way that the eight most significant bits make the row-address and the eight least significant bits make the column-address of the pixel in the frame. The frame size considered here is 176 * 144 size of the standard QCIF format is. Before storing the pixel values in RAM, the dimensions of the frame are extended to nearest larger number which is an integer power-of-2 i.e. 256 * 256 in this case, by padding zeros in the remaining places.
CURRENT FRAME AND REFERENCE FRAME BASE ADDRESS GENERATOR :-
These two units will be storing the current and the reference base address and will be generating addresses of the current macro block for block-matching algorithm and the addresses of the nodes in case of mesh based motion estimation. This block will provide the 16-bit address of the current block and the reference block to the block address generator unit.
BLOCK ADDRESS GENERATOR :-
This unit is needed to generate offset addresses, with respect to the given block address, in order to scan individual pixels of the given 8 * 8 block in raster-scan order. In other words, it takes the address of an 8 * 8 block as input and generates addresses to the pixels of that block. The input address is the address of the top-left corner pixel of the given 8 * 8 block. A counter is used to address each individual pixel of the given 8 * 8.
SAD :-
The SAD module computes the sum of absolute differences (SAD) of the current block and the reference block in comparison by taking absolute difference of corresponding pixel values in both the blocks and accumulating 64 absolute differences for (8 * 8) block. All pixel values are 8-bit values. So the maximum possible SAD is 255 * 64 = 16320 which can be stored in a 14-bit register. If the reference block address falls out of the bounds, then the SAD register is loaded with the maximum possible register value i.e. 16383. A block address is invalid if any of its pixel has row address beyond the range [0, 175] and/or column address beyond the range [0, 144]. The SAD computed for each block is stored in a register and it is compared with the existing minimum SAD (MSAD) stored in another register. If the SAD of the recent matching is less than the existing minimum SAD then the comparator raises an indication of availability of a new MSAD, which then asserts load signals for the MSAD and the store the motion vector corresponding to that block in the motion vector register.
MOTION VECTOR :-
This block will save the values of the motion vectors for each of the macro blocks present in the current frame.
