Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.
WhatsApp 9892124323 ✓Call Girls In Khar ( Mumbai ) secure service - Bandra F...
Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy
1. Francesca Palumbo
Università degli Studi di Sassari
PolComIng – Information
Engineering Unit
2014 IEEE International Workshop on gnal rocessing ystems
October 20 – 22 2014, Belfast, UK
and Luigi Raffo
DIEE – Dept. of Electrical and Electronics Eng.
EOLAB - Microelectronics and Bioeng. Lab.
2. OUTLINE
• Introduction
– Problem statement
– Background
– The power issue
• Automatic Power-Awareness Strategies
– Baseline Multi-Dataflow Composer
– Static Power: Structural Optimization
– Dynamic Power: Behavior Optimization
• Performance Assessment
– Design Under Test
– Structural Evaluation
– Behavior Evaluation
• Final Remarks and Future Directions
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau2
3. OUTLINE
• Introduction
– Problem statement
– Background
– The power issue
• Automatic Power-Awareness Strategies
– Baseline Multi-Dataflow Composer
– Static Power: Structural Optimization
– Dynamic Power: Behavior Optimization
• Performance Assessment
– Design Under Test
– Structural Evaluation
– Behavior Evaluation
• Final Remarks and Future Directions
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau3
4. PROBLEM STATEMENT
CONSUMER NEEDS:
• HIGH PERFORMANCES real time applications:
– Media players, video calling...
• UP-TO-DATE SOLUTIONS
– Support for the last audio/video codecs, file formats...
• MORE INTEGRATED FEATURES in mobile devices:
– MP3, Camera,Video, GPS...
• LONG BATTERY LIFE
– Convenient form factor, affordable price...
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau4
5. PROBLEM STATEMENT
CONSUMER NEEDS:
• HIGH PERFORMANCES real time applications:
– Media players, video calling...
• UP-TO-DATE SOLUTIONS
– Support for the last audio/video codecs, file formats...
• MORE INTEGRATED FEATURES in mobile devices:
– MP3, Camera,Video, GPS...
• LONG BATTERY LIFE
– Convenient form factor, affordable price...
POSSIBLE SOLUTION:
• DATAFLOW MODEL OF COMPUTATION
– Modularity and parallelism EASIER INTEGRATIONAND FAVOURED RE-USABILITY
• COARSE-GRAINED RECONFIGURABILITY
– Flexibility and resource sharing MULTI-APPLICATION PORTABLE DEVICES
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau4
6. BACKGROUND
DATAFLOW FORMALISM
• Directed graph of actors
(functional units).
• Actors exchange tokens (data
packets) through dedicated
channels.
CHARATERISTICS
• Explicit the intrinsic
application parallelism.
• Modularity favours model
long-term adaptivity.
A
D
C
actions
state
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau5
B
7. BACKGROUND
DATAFLOW FORMALISM
• Directed graph of actors
(functional units).
• Actors exchange tokens (data
packets) through dedicated
channels.
CHARATERISTICS
• Explicit the intrinsic
application parallelism.
• Modularity favours model
long-term adaptivity.
A
D
C
actions
state
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau5
B
8. BACKGROUND
FINE- GRAINED (FG) RECONFIGURATION
• High flexibility bit-level reconfiguration
• Slow and memory expensive configuration phase
• Suitable for applications with high control flow
COARSE-GRAINED (CG) RECONFIGURATION
• Medium flexibility word-level reconfiguration
• Fast configuration phase
• Suitable for applications with high level of instruction/data parallelism
FG CG
Bit-level Word-level
Flexibility
Reconf.
Speed
Config.
Storage
ASIC
GPP
DSP
RECONFIGURABLE
DESIGNS
Performance
Flexibility
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau6
20. STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau11
21. STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
B
3μW
F
5μW
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
F
5μW
S0
2μW
S1
2μW
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau11
22. STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
B
3μW
F
5μW
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
F
5μW
S0
2μW
S1
2μW
= 52μW
= 53μW
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau11
23. STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
B
3μW
F
5μW
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
F
5μW
S0
2μW
S1
2μW
= 52μW
= 53μW
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau11
24. A
B
DC D B D B D
α β γ
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
25. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γ
αγβ
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
26. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γ
αγβ
longest
chain
2 SBoxes
S1 S2
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
27. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
S1 S2
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
28. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
longest
chain
4 SBoxes
S1 S2
S0
S1
S2
S5
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
29. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
longest
chain
4 SBoxes
S1 S2
S0
S1
S2
S5
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
30. A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
longest
chain
4 SBoxes
S1 S2
S0
S1
S2
S5
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau12
STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
41. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B F
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
42. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B F
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
43. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B FA
B
D
C
A
B
D
C
E F
S0 S1
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
44. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B F
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
45. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B FE B F
A
B
D
C
E F
S0 S1
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
46. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B FE B F
A
B
D
C
E F
S0 S1
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau14
50. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C E
Net 1
Net 2
Net 3
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau15
51. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C E
Net 1
Net 2
Net 3
A
B
D
C E
LR1
LR2
LR3
LR4
LR5
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau15
52. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
label actors
LR1 A
LR2 C
LR3 D
LR4 B
LR5 E
DPN regions
Net1 LR1,LR2,LR3,LR4
Net2 LR1,LR3
Net3 LR3,LR4,LR5
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau15
55. DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
S0
S1
E
C
D
B
A
S3
S4
LR1
LR2
LR3
LR4
LR5
en1
en2
en3
en4
en5
ck
ck
ck
ck
ck
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau15
56. OUTLINE
• Introduction
– Problem statement
– Background
– The power issue
• Automatic Power-Awareness Strategies
– Baseline Multi-Dataflow Composer
– Static Power: Structural Optimization
– Dynamic Power: Behavior Optimization
• Performance Assessment
– Design Under Test
– Structural Evaluation
– Behavior Evaluation
• Final Remarks and Future Directions
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau16
60. [MS:MergedSpecifications]
POWER OPTIMAL (TOP.p):
all merged
STRUCTURAL EVALUATION
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau18
61. [MS:MergedSpecifications]
POWER OPTIMAL (TOP.p):
all merged
FREQ OPTIMAL (TOP.f ):
5 over 7 merged
STRUCTURAL EVALUATION
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau18
62. [MS:MergedSpecifications]
POWER OPTIMAL (TOP.p):
all merged
FREQ OPTIMAL (TOP.f ):
5 over 7 merged
STRUCTURAL EVALUATION
DESIGN
STATIC POWER
ESTIMATION [mW ]
STATIC POWER
MEASURE [mW]
ESTIMATION
ERROR
TOP.f 30.175 29.650 1.77%
TOP.p 25.833 25.716 0.45%
TOP.p vsTOP.f -13.75% -14.39% 7.78%
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau18
63. BEHAVIORAL EVALUATION
NOCG = without clock gating implementation
AUTO = with the synthesizer automatic register-level clock gating implementation
CG = with the proposed high-level clock gating implementation
DESIGN # of LRs
NOCG AREA
[μm2]
CG AREA
[μm2]
CG vs NOCG
TOP.f 9 135819 136076 +0.19%
TOP.p 13 124026 124579 +0.25%
TOP.p vsTOP.f +44.44% -8.68% -8.45% +31.58%
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau19
64. BEHAVIORAL EVALUATION
DESIGN
DYNAMIC POWER
CG vs NOCG CG vs AUTO
TOP.f -74.86% -69.06%
TOP.p -71.30% -63.75%
TOP.p vsTOP.f -13.75% -14.39%
NOCG = without clock gating implementation
AUTO = with the synthesizer automatic register-level clock gating implementation
CG = with the proposed high-level clock gating implementation
DESIGN # of LRs
NOCG AREA
[μm2]
CG AREA
[μm2]
CG vs NOCG
TOP.f 9 135819 136076 +0.19%
TOP.p 13 124026 124579 +0.25%
TOP.p vsTOP.f +44.44% -8.68% -8.45% +31.58%
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau19
65. OUTLINE
• Introduction
– Problem statement
– Background
– The power issue
• Automatic Power-Awareness Strategies
– Baseline Multi-Dataflow Composer
– Static Power: Structural Optimization
– Dynamic Power: Behavior Optimization
• Performance Assessment
– Design Under Test
– Structural Evaluation
– Behavior Evaluation
• Final Remarks and Future Directions
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau20
66. FINAL REMARKS AND FUTURE
DIRECTIONS
• Power consumption management is a challenging issue
in modern embedded system designs
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau21
67. FINAL REMARKS AND FUTURE
DIRECTIONS
• Power consumption management is a challenging issue
in modern embedded system designs
• The Multi-Dataflow Composer aims at:
– Implementing coarse-grained multi-functional devices
– Providing efficient power-aware architectures
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau21
68. FINAL REMARKS AND FUTURE
DIRECTIONS
• Power consumption management is a challenging issue
in modern embedded system designs
• The Multi-Dataflow Composer aims at:
– Implementing coarse-grained multi-functional devices
– Providing efficient power-aware architectures
• MDC now integrates high-level power aware strategies
reducing both static and dynamic power consumption
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau21
69. FINAL REMARKS AND FUTURE
DIRECTIONS
• Power consumption management is a challenging issue
in modern embedded system designs
• The Multi-Dataflow Composer aims at:
– Implementing coarse-grained multi-functional devices
– Providing efficient power-aware architectures
• MDC now integrates high-level power aware strategies
reducing both static and dynamic power consumption
• Future developments
– Power gating on different logic regions
– Improvements in the estimation models
– Heuristic for the profiler design space exploration
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau21
70. The research leading to these results has received funding from:
• the Region of Sardinia L.R.7/2007
under grant agreement CRP-18324
[RPCT Project].
• the Region of Sardinia, Young
Researchers Grant, POR Sardegna FSE
2007-2013, L.R.7/2007 “Promotion of
the scientific research and
technological innovation in Sardinia”
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau22
ACKNOWLEDGEMENTS
71. Università degli Studi di Cagliari
DIEE – Dept. of Electrical and Electronics Eng.
EOLAB - Microelectronics and Bioeng. Lab.
2014 IEEE International Workshop on gnal rocessing ystems
October 20 – 22 2014, Belfast, UK
72. Read full article
• IEEE Xplore Digital Library
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb
er=6986104&tag=1
• RPCT ProjectWebsite:
http://sites.unica.it/rpct/references/
73. Reference
• @INPROCEEDINGS{SAU_SIPS2014,
author={F. Palumbo and C. Sau and L. Raffo},
booktitle={2014 IEEE Workshop on Signal
Processing Systems (SiPS)},
title={Power-awarness in coarse-grained
reconfigurable designs: A dataflow based
strategy},
year={2014},
pages={1-6},
doi={10.1109/SiPS.2014.6986104} }
BibTex