Design and simulation of a non pipelined multi cycle 16 bit risc educational processor using verilog hdl

INTERNATIONAL JOURNAL OF ELECTRONICS AND
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 9, September (2014), pp. 14-23 © IAEME
COMMUNICATION ENGINEERING TECHNOLOGY (IJECET)

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 9, September (2014), pp. 14-23
© IAEME: http://www.iaeme.com/IJECET.asp
Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
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IJECET
© I A E M E
DESIGN AND SIMULATION OF A NON-PIPELINED, MULTI- CYCLE 16
BIT RISC EDUCATIONAL PROCESSOR USING VERILOG HDL
Qazi Raza Abdul Quadir[1], Arif Rasool[2], Manan Mushtaq[3], YasirBhat[4]
Department of Electronics Communication Engineering, National Institute of Technology,
Srinagar, India
ABSTRACT
This paper presents the approach to design and simulate a 16 bit RISC processor using
Verilog HDL and is based on the SAYEH architecture (Simple Architecture Yet Enough Hardware)
which is a non pipelined architecture. The multi cycle part includes there set, fetch, decode,
load/store and haltcycles for carrying out one complete process. In this paper the structure and
working of Instruction Set Architecture, Datapath and Controller modules are explained along with
individual submodules. Also the simulation results in ModelSim and RTL layout in XilinxISE of
main modules are shown.
Keywords: Educational Processor, HDL Processor, Processor Architecture, Sayehprocessor,
Verilog Processor.
1. INTRODUCTION
RISC stands for “Reduced Instruction Set Computer” and its main difference from CISCis its
simplicity while others being fewer instruction sets, faster for simple computations, less transistors
required etc. When it was seen that most of the computations did not require the load/store from the
memory, the advantage of RISC to such operations was clear[1][2]. Here we will discuss a special
RISC processor based on SAYEH architecture (Simple Architecture Yet Enough Hardware) which
as the name suggests tends to develop enough operations with the simplest minimum architecture
possible. This approach does not use pipelining structure to attain simplicity and can be developed in
both single and multi-cycleforms[3]. One of the exhaustive approach towards understanding processor
architecture through HDL is SAYEH developed by Professor ZainalabedinNavabi[4].The processor
possesses minimum hardware with enough operations possible on that hardware. The aim of the
paper is to discuss, design and verify a customizable processor which is simple yet exhaustive
enough to be taught in engineering and technical institutions. This paper will specify the design
architecture and verify the working of a multi cycle verilog processor. Verilog is selected because of
its simplicity[5]. It will also discuss the working of the submodules. Thus the main motive of this

International Journal of Electronics and Communication Engineering Technology (IJECET), ISSN 0976 –

project is to create an educational custom processor which can be customized by interested parties
using its architectural skeleton and which can be taught to interested students using Hardware
Descriptive Languages. Most of the educational institutions in the world teach microprocessors and
their architecture through assembly language programming. There they are taught about a pre
designed processor like Intel 8085 with all the simple processes that lead to the understanding of the
computer micro architecture[6]. The assembly codes, instructions and registers are predefined and
cannot be altered. But what if the students were given a canvas where they could tinker with a simple
processor skeleton and develop application specific instructions and alter the register structures and
transfer logic. Would that not be more productive and innovative method to approach the lesson on
computer architecture? Definitely, this approach would lead to curiosity and innovative spirit in the
students and would give birth to a whole new set of ideas aggrandizing the already available
processor ideas.
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2. HEADINGS
1. Introduction
2. Headings
3. Architecture
3.1 Processor Architecture layout.
3.2 Instruction Set Architecture.
4. Designing the Processor
4.1 Addressing Unit.
4.2 Status Register, Window Pointer and Instruction Register.
4.3 Register File.
4.4 ALU and Controller.
5. Simulation Results
5.1 Addressing Unit.
5.2 ALU.
5.3 Register File.
5.4 Controller.
5.5 Testing MVI and ADD.
6. RTL Schematics of ALU and Controller
7. Conclusion and Future Work
8. Acknowledgements
3. ARCHITECTURE
It has a register file that is used for data processing instructions. The CPU has a 16-bit data
bus and a 16-bit address bus, also a 16-bit Instruction Set Architecture (ISA). Figure below shows
the interface signals:
Fig 1: Interface signals


When the memory instructions are executed, the processor issues ReadMem or WriteMem
signals to the memory. The components that are used by its instructions include the standard registers
such as the program counter, instruction register, ALU and status register. In addition, this processor
has a Register File forming registers R0, R1, R2 and R3 as well as a Window pointer that defines R0
to R3 within the register file.
3.1 Processor Architecture Layout
PC: Program counter, 16-bits.
R0, R1, R2, R3: General purpose registers, 16-bits, the general purpose registers form a window of
4 in a register file of 64 registers.
WP: Windows Pointer, 6-bits.
IR: Instruction Register, 16-bits.
ALU: The ALU can add, subtract and multiply its inputs.
Z flag: Becomes 1 when the ALU output is 0.
C flag: Becomes 1 when the ALU has a carry output.
Fig 2: Processor Architecture[3]
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3.2 Instruction Set Architecture
The general format of 16-bit instruction as shown in figure, have 8-bit Immediate field. The
OPCODE field is a 4-bit code that specifies the type of instruction. The Left and Right fields are
2-bit codes selecting R0 through R3 registers in the Register File for source and/or destination of an


instruction. Usually, Left is used for destination and Right for source. The Immediate field is used
for immediate data, or is used for the second instruction OPCODE extension.
Fig 3: Instruction Set Register[3]
This processor has a total of 18 instructions as shown in figure. Instructions that use the
Destination and Source fields (designated by D and S in the table of instruction set) have an
OPCODE that is limited to 4-bits. Instructions that do not require specification of source and
destination registers use these fields as OPCODE extensions. In the instructions set, addressed
locations in the memory are indicated by enclosing the address in a set of parenthesis.
TABLE – Instruction Set[3]
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4. DESIGNING THE PROCESSOR
4.1 Addressing Unit
It consists of Program Counter and Addressing Logic Unit. The program counter is used as a
16 bit address storing register. Reset PC signal from Controller to Address Logic circuit resets value
of PC to 0000H. According to the control signal to Address logic, the output address is either
incremented by 1 or made to jump by a 8 bit value from IR[7:0] or by a 16 bit value from RFright
(from right selected register in Register File). The updated output address is stored back as a new
value to PC creating a feedback. The output [15:0]Address is put on Databus using a buffer,
controlled by ‘Address_on_Databus’ control signal, from where it is then sent to the External
Memory.


Fig 4: Addressing Unit consisting of Program Counter and Address Logic Unit
4.2 Status register, Window pointer and Instruction Register
Status or Flag Register (SR), is designed as a Carry and Zero bit storing module. It takes previous
value of Cout from ALUout as input and sends it as new Cin to ALU. It sets Zero flag to 1 when
ALUout = 0. It monitors the ALUout and the contents are updated when SRload control signal from
controller = 1. Window Pointer is a 6 bit register which takes its input from lower 6 bits of
Instruction Register and adds them to previous value stored when WPadd control signal = 1. These
bits are then sent to Register File as Base address. Wpreset sets value of base address to RF as
000000b. Instruction Register is a 16 bit register which takes its input from Databus and updates
itself when IRload control signal = 1. IR bits are sent to Controller(Decode),Address Unit(Immediate
Jump), Opndbus(then to ALU),Window Pointer and Register File.
Fig 5: Instruction, Status(Flag) and Window Pointer Registers
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4.3 Register File
The Register File has 64 * 16 bit registers which are selected by window pointer and IR[11:8]
in a window of 4 registers(because the maximum difference between Laddress and Raddess can
be{0011} a distance of 4 registers; like selecting 2 stories out of 4 ).Left Register (sent to ALU)
and Right Register(sent to ALU or AU{for jump}) are selected as RF[Laddress] and RF[Raddress]
where Laddress= Base(from WP) + IR[11:10] and Raddress = Base + IR[9:8].To write into RF,
RFLwrite control signal = 1. When RFLwrite control = 0, data is automatically read from RF to left
and right outputs as shown in Figure.


Figure 6: Register File
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4.4 ALU and Controller
The Arithmetic Logic Unit module is able to perform – Pass, add, sub, bitwise and, bitwise or,
not, multiply immediate. It interacts with Status register to get the current status of flags from
previous computation, gets control signals from controller and sends output to Databus when control
signal ALUout_on_Databus =1.The Controller takes the Instruction from IR and decodes it and
sends appropriate control signals to the Datapath Module. Datapath also includes a 16 bit Databus,
16 bit Address bus,8 bit operand bus(Immediate) and buffers controlled by controller. The whole
processor is actually an amalgamate of Datapath and Controller. External Memory is designed as an
array of 1024 * 16 bit array of registers and it used to load instructions and data or store data. The
Top final module may be considered as the combination of Processor and External Memory.
Fig 7: Arithmetic Unit and Controller Unit


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5. SIMULATION RESULTS
5.1 Addressing Unit
Fig 8: Addressing Unit waveform
5.2 ALU
Fig 9: ALU waveform
5.3 Register File
Fig 10: Register File waveform


21
5.4 Controller
Fig 11: Controller waveform
5.5 Testing MVI (move immediate) and ADD instructions[7]
Fig 12: Testing mvi and add waveforms
Fig 13: Register File values after Fig 14: Register File values after
updating R0 and R1 running add instructions


22
6. RTL SCHEMATICS
Fig 15: ALU RTL Fig 16: Controller RTL
7. CONCLUSIONS AND FUTURE WORK
The complete procedure of designing and simulating the processor has been outlaid in this
paper. This processor can further be redesigned for adding various analog and digital inputs and
algorithm modules which can then be used for robotic sensor boards and other embedded
applications. This processor can further be commercially used in educational institutions at
engineering and technical levels and can be integrated in the semester course syllabus. This HDL
approach to processor design would ignite the creative spirit among students to model or modify
existing architectures, thus actively learning the micro architectures. Many other processor cores can
be designed once learning and developing the design of a simple primitive core. Such approach is
limited to simple processors for students will not be able to develop complex processor architectures
and functions. But, nonetheless, this approach to study is one of the most creative and enjoyable
ways to learn microprocessor architectures.
8. ACKNOWLEDGEMENT
We would like to sincerely thank our HOD professor G.M. Rather, ECE dept., NIT Srinagar
who guided us through this project. Also we would like to thank Professor Najeebud Din, ECE dept.,
NIT Srinagar for his timely advices and guidance through the project process.


23
REFERENCES

[1] Carl Hamacher, ZvonkoVranesic and SafwatZaky, Computer Organization (Tata McGraw
Hill, 5thedition,2011).
[2] Morris Mano, Digital Logic and Computer Design (Pearson Publications, 1979)
[3] ZainalabedinNavabi, Embedded Core Design with FPGA, 4 (McGraw Hill, 2007).
[4] ZainalabedinNavabi, “Verilog Digital System Design”, second edition, McGraw Hill,
Chapter 8.
[5] Samir Palnitkar, Verilog HDL – A guide to Digital design and Synthesis (Pearson
Publications, Second edition, 2013).
[6] Ramesh Gaonkar, Microprocessor Architecture, Programming and Applications with the
8085 (Penram international Publishing, 5th edition, 2000).
[7] AlirezaHaghdoost, ASIC Design of Sayeh Processor using TSMC 0.25 um technology
(Advanced Logic Design Report, Shahed University, Spring 2008).
[8] Bharat Kumar Potipireddi and Dr. Abhijit Asati, “Automated HDL Generation of Two’s
Complement Wallace Multiplier with Parallel Prefix Adders”, International Journal of
Electronics and Communication Engineering Technology (IJECET), Volume 4, Issue 3,
2013, pp. 256 - 269, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.
[9] R.Kathiresan, M.Thangavel, K.Rathinakumar and S.Maragadharaj, “Analysis of Different
Bit Carry Look Ahead Adder using Verilog Code”, International Journal of Electronics
and Communication Engineering Technology (IJECET), Volume 4, Issue 4, 2013,
pp. 214 - 220, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.

Design and simulation of a non pipelined multi cycle 16 bit risc educational processor using verilog hdl

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Design and simulation of a non pipelined multi cycle 16 bit risc educational processor using verilog hdl