International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN   INTERNATIONAL JOURNAL OF ...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
Upcoming SlideShare
Loading in...5
×

Cs cmos a low-noise logic family for mixed signal

325

Published on

Published in: Technology, Business
2 Comments
0 Likes
Statistics
Notes
  • Mediafire Download : http://www.mediafire.com/download/crbbeor4xcdkarc
       Reply 
    Are you sure you want to  Yes  No
    Your message goes here
  • Mediafire Download : http://www.mediafire.com/download/7co8ti89fp7of5c
       Reply 
    Are you sure you want to  Yes  No
    Your message goes here
  • Be the first to like this

No Downloads
Views
Total Views
325
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
11
Comments
2
Likes
0
Embeds 0
No embeds

No notes for slide

Cs cmos a low-noise logic family for mixed signal

  1. 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN INTERNATIONAL JOURNAL OF ELECTRONICS AND 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMECOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 180-190 IJECET© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI) ©IAEMEwww.jifactor.com CS-CMOS: A LOW-NOISE LOGIC FAMILY FOR MIXED SIGNAL SOCS Aswathy G Nair1, Gopakumar M G2 1 Student,M.Tech(VLSI& Embedded Systems), Mangalam,Ettumanoor,India 2 Asst. Professor, Deptt. Of ECE, Mangalam, Ettumanoor, India ABSTRACT Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. Existing logic families that minimize switching-noise generation, Such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a new logic family called the current-steering CMOS (CS-CMOS) obtained by a simple modification keeping the core CMOS structure in tact to preserve its most attractive features. This family not only reduces the switching noise by a factor of ten but also delivers five times higher speed than CSL and CBL for the same power consumption. A comparison with existing alternative circuits shows that, for the same supply voltage and the same power consumption, the new circuits have smaller area and lower delay. Keywords: Current-balanced logic (CBL), Current-steering CMOS (CS-CMOS), current steering logic, Mixed signal system-on-chip (SoC), Power supply noise. 1. INTRODUCTION VLSI systems-on-chip (SoCs) use CMOS digital-logic circuits because they consume very low power, have high packing density and are easy to design. Most of the power consumed by CMOS gates is due to displacement currents drawn during state-transitions for charging and discharging wire and device capacitances. These increase linearly with the operating frequency and flow through the power supply wires, ground lines, parasitic inductances and capacitances causing ringing and voltage drop. This is the dominant source of substrate noise. Injection of this noise into sensitive analog circuits can cause serious impairments in their performance. Typical examples are increased jitter in voltage-controlled oscillators and reduction in the dynamic range of analog-to-digital converters, etc. 180
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME In mixed signal integrated circuits, there is a digital sector that generates switchingnoise and an analog sector to which the noise is coupled via the substrate, which is shared bythe two sectors. The noise coupling can be reduced, to some extent, by careful layout androuting. Further noise reduction is necessary, and this is the purpose of new low-noise logicfamilies, that are expected to generate less noise into the substrate than conventional CMOSdigital circuits. The most interesting of the new families, due to their simpler structure, arecurrent-steering logic (CSL) and current-balanced logic (CBL). Reduced noise in CSL andCBL circuits is obtained by having an ideally constant supply current. Due to non-idealeffects, the supply current still has spikes associated with the output voltage transitions, buttheir amplitude is reduced by one to two orders of magnitude with respect to CMOS.However, the substrate noise depends on the time derivative of the supply current, and not onthe amplitude of its variations; furthermore, there are other sources of substrate noise, inaddition to the supply current. Variation. Thus, to evaluate the effective improvementobtained with CSL or CBL it is necessary to consider the actual substrate noise.2. SUBSTRATE NOISE IN MIXED-SIGNAL CIRCUITS In mixed-signal integrated circuits, the digital sector and the analog sector share acommon substrate. In Fig. 1 we represent one transistor of the digital sector and one transistorof the analog sector. In a lumped element equivalent circuit the substrate is modeled by asingle “substrate node” connected to the other nodes in the digital and analog sectors byparasitic resistances and capacitances, some of which are shown in Fig. 1 (the resistancesshown would ideally be short circuits, and the capacitances would be open circuits). This single-node approach was originally adopted for dual layersubstrates (thin lightly doped, high resistivity epitaxial layer grown on top of a thick, heavilydoped, low resistivity bulk layer) used in digital technologies. It has been shown that thisapproach is also applicable to single-layer homogeneous substrates. In and the resultsobtained assuming a single-node substrate representation, for both low-resistivity and high- 181
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEresistivity substrates, do not differ substantially from the results obtained using a moreconventional simulation procedure (boundary element method). In dual-layer substrates, thesubstrate node corresponds physically to the heavily doped bulk layer, which behaves as asingle node. In single-layer substrates, the substrate node has meaning only for modelingpurposes. One of the terminals of the external voltage supply is the “ground,” i.e., thecommon reference to all signals, digital and analog. The connection to the supply voltage hasinductance and resistance, but only the inductance is included in Fig. 1, since the effect of theresistance can be neglected. The substrate noise is the voltage between the substrate node andthe ground terminal. The substrate noise originated by the switching of the digital cells hastwo main sources, which are referred to here as supply noise and capacitive noise.Supply noise—The supply current spikes that occur during the state transition of the digitalcells are translated into a voltage, L dIDD/dt which influences the substrate node voltage.This increases with the supply inductance and with the steepness of the current spikes.Capacitive noise—the voltage steps at the nodes of the digital cells are coupled to thesubstrate node through the parasitic capacitances. An additional source of substrate noise is impact ionization, which may besignificant in advanced technologies with a very thin oxide under the gate. The substratenoise voltage affects the analog cells due to the body effect and due to the capacitive couplingto the transistor terminals. This effect increases with the coupling areas (capacitances) and thesteepness of the voltage variation. The supply noise can reach hundreds of mill volts, and hasbeen regarded as a major cause of performance degradation in mixed-signal circuits.3. LOW-NOISE LOGIC FAMILIES The common principle of the low-noise logic families that have been proposed for usein mixed-signal circuits is to have a supply current that is ideally constant. Due to non-idealeffects, it still has switching spikes, but their amplitude is strongly reduced, with respect toCMOS digital circuits. In the first families that were proposed the constant supply current isobtained by having the connection to the power supply through a current source. These low-noise families include source-coupled logic folded source-coupled logic nMOS CBL, andCSL. Some of these families have limited practical interest, due to their complicatedstructure, with a large number of devices and terminals, which leads to large area and powerdissipation and also to difficult routing.4. PREVIOUS WORKS: CURRENT-STEERING LOGIC (CSL) & CURRENTBALANCED LOGIC (CBL) Current-steering logic (CSL) and current-balanced logic (CBL) are logicfamilies that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits4.1 CSL (current-steering logic) The most interesting of these families is CSL, since CSL circuits are much simpler.The structure of a CSL gate is shown in Fig. 2(a), where the nMOS logic block is the samethat would be used between the output and ground in an nMOS gate or in a CMOS gate. Thesupply current IDD is steered to ground through the nMOS block when this is in the lowresistance state (output low); otherwise it is sank through the diode connected transistor M3 182
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME(output high). The special case of the CSL inverter is shown in Fig. 2(b), where the nMOSblock is reduced to transistor M1, and the current source is realized by transistor M2 with aconstant bias voltage VB. These limitations can be overcome by using a different principle to obtain a constantsupply current, a current equalizer transistor is used instead of a current source, thus leadingto a different family, CBL.4.2 CBL (current balanced logic) In mixed-signal (i.e., analog–digital) integrated circuits, the noise generated in thedigital section affects the performance of the analog section. An important source of noise isthe supply current spikes during logic transitions. To avoid these, the current-steering logic(CSL) family has been proposed. By using a current source, the supply current IDD is ideallyconstant. In practice, supply current spikes still exist, but their amplitude is reduced by up totwo orders of magnitude with respect to conventional CMOS logic circuits. In this paper wepropose the new current balanced logic family (CBL), which has advantages with respect tothe existing CSL family. The new circuits achieve ideally constant supply current by using a differentprinciple. They may be regarded as pseudo- NMOS circuits to which transistor M3 has beenadded. The objective is that, during logic transitions, the variation of iD3 compensates (orbalances and, hence, the designation current balanced Logic) the variation of iD2 183
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME We find that perfect compensation can be obtained, thus making iD3 + iD2 =IDD constant, if transistors M2 and M3 are matchedVtn = Vtp = VtK3 = K2 = Kwhere Vtn and Vtp are the threshold voltages of the NMOS and PMOS transistors,respectively,with the usual meaning for µ (mobility), Cox (gate oxide capacitance), and W/L (aspectratio).5. POPOSED WORKS: CURRENT STEERING CMOS (CS-CMOS) The problem of switching noise is dealt in three parts: noise generation, itspropagation through the substrate, and injection in to analog circuits. The focus here is tominimize the generation of switching noise and keeping the impulse current local to where itis generated. Among the existing logic families that use this approach are current steeringlogic (CSL) and current balanced logic (CBL). Both of these families reduce noise becausethey draw a constant-current from the supply. But the power consumption is higher than thatof the equivalent CMOS implementation.5.1 CS-CMOS LOGIC5.1.1 Static Transfer Characteristics CS-CMOS is obtained by a simple current-steering modification to the standardCMOS family. As in a CMOS inverter, a pair of complimentary transistors (M1-M2)connected in series forms the core of the proposed CS-CMOS inverter, as shown in Fig.5.Since CMOS gates do not draw any appreciable current in their static states, constant-current 184
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEoperation requires additional paths for the d-c bias current to flow. A pair of complimentarytransistors(M3,M4) is added in parallel for this purpose. A P-channel transistor M5 sources aconstant-current IB to each gate. When is VIN HIGH M1 is OFF and M2 is ON. The output node voltage VOUTis LOW turning M3 ON and IB flows in M3. Note that minimum output LOWvoltage(VOL) for CS-CMOS is same as in CMOS. This is not so for the other single-endedratioed logic families such as CSL and CBL. When is VIN low the output node is HIGH,M4conducts and IB is steered into it. Assuming the square-law model for the transistors,maximum output voltage(VOH) can be computed as …….(1) Figure 5. CS-CMOS inverter In the above equation µ represents the carrier mobility, COX is the oxidecapacitance per unit-area, W represents the width and , the L length of the transistor. To havean appreciable overdrive voltage (VDSAT) for a given current, minimum-width devices arechosen for M3 and M4 Such a choice causes minimal loading and hence does not appreciablyaffect the speed of the inverter. The node X with the capacitor in Fig. 5.acts like a local power supply for the CMOSinverter M1-M2. If VX>VT1+VT2 , the inverter (M1-M2) operates like a regular CMOScircuit in which there is an input voltage range for which both M1 and M2 will conductsimultaneously. When this happens a part of IB flows through this path between the node Xand ground. For VX<VT1+VT2 , as VIN increases from LOW to HIGH,M1 will shut OFFbefore M2 turns ON and for decreasing VIN, M2 will shut OFF before turns M1 ON. Theideal choice is to make VX= VT1+VT2. If the threshold voltages of are chosen to be equal tothose of M3-M4 , this criterion cannot be met. This is because the magnitude of VX is thegate-source voltage of M3 or M4 given by (1). But if the threshold voltages of M1-M2 arechosen to be smaller than those of M3-M4 a reduction in hysteresis can be achieved. Thusthe threshold voltages for M1 and M2 are chosen such that VT1+VT2=VT4+VDSAT4. 185
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME DC transfer-characteristics of the inverter shownFig.6..Consider the output pull-uptransition. Initially, when VIN is HIGH, VOT is LOW and M3 carries the bias current IB .As VIN decreases M1 starts conducting. Now M1-M3 forms a current-biased p-channeldifferential- pair with M2 acting as an active- load. Let the incremental d-c trans conductanceof the pair gmd be and the output-conductance due to M1 and M2 in parallel, .Routine small-signal Analysis ,givesHere the lower-case symbols represent incremental quantities. Equation (2) indicates the presence of positive feedback in the CS-CMOS inverter.When we consider M2 as an active load of the differential pair, it is easy to identify thecircuit as a Schmidt-trigger containing positive feedback via the output of the inverter and thenode X . Initially as VIN is HIGH, gmd is small as M1 is OFF. Furthermore g0 is large sinceM2 operates in its triode region. Hence the incremental gain A is <<1. As VIN decreases, M1begins to conduct and decreases causing the gain to increase. A>=1 leads to regeneration andswitching. Thus the presence of positive feedback causes high gain during the transitions (seeFig. 6). Such a high gain does not happen in the other logic families having no feedback. 186
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME5.1.2 Dynamic Characteristics The speed of low noise logic families is limited by the bias current IB. In CS-CMOSthe additional capacitor CD added at the node X (see Fig. 6) acts as a decoupling capacitor.Itsupplies most of the charge required to pull up the load-capacitance. Although the currentsupplied from the power supply is fixed, the capacitor CD makes it operate virtually likeirregular CMOS circuit. The size of the CD for CS-CMOS gates is chosen as follows. For anallowable change at the power supply node (vx) during the pull-up transition, the valueofrequired can be estimated as …….(3) where is the load CL capacitance consisting of the wire and device capacitancesat the output node. Restricting the number of fan-outs of a gate can keep the size of CDsufficiently large and yet keep the size of the CS-CMOS gate manageable. For both CSL andCBL gates the pull-up rise-time and delay are controlled by the bias current, but the voltageacross the capacitor CD in CS-CMOS provides a quadratic current similar to that in standardCMOS. A key reason for the widespread use of digital CMOS is its, very low powerconsumption. However, low noise implementations like CSL and CBL consume an order ofmagnitude higher power . CS-CMOS attempts to bridge this gap by using the capacitor CDwhich provides most of the charge during the pull-up operation. This boosts the performanceof CS-CMOS substantially. The charge lost by CD during the pull-up is replenished by thebias current . The required bias current can thus be estimated as ...................(4) For CSL and CS-CMOS inverters the bias current is adjusted by changing thevoltage VBIAS . For CBL inverters the current is adjusted by varying the supply voltage. Itcan be observed that the CS-CMOS inverters can achieve less than 1 ns delay for biascurrents greater than 1 A.5.2 Current Supply Spikes Displacement current pulses flowing through the inductances of ground wires causesnoise spikes known as ground bounce. Noise is also injected into the substrate from thesource and drain nodes of the MOS devices during transitions. This is known as capacitivenoise coupling to the substrate. Yet another noise source is due to impact ionization. CSL,CBL and CS-CMOS gates have minimal displacement currents in the power-supply linebecause of the constant-current operation. Thus capacitive coupling into the powersupply/substrate is the dominant source of noise injection for these logic families .Theparasitic capacitances associated with the CS-CMOS inverter are shown in Fig. 7. These are 187
  9. 9. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEMEthe CCS (the drain-well capacitance of the PMOS transistor M5) and the capacitor CD. Whena step input is applied to the inverter a displacement current I is supplied from the node X topull up the output node X. A fraction of this current Isup is supplied from power supplythrough the parasitic capacitance CCS but most of it is delivered by CD. Fig. 7. Parasitic capacitances in a CS-CMOS inverter used to estimate the fraction of current flowing into the power supply. This fraction is estimated as ......(5) This fraction can be reduced either by increasing the value CD of or by decreasingthe value of CCS. The value of CD is chosen based on the load capacitance. CCS dependson the size of the transistor M5.6. COMPARISON OF CBL, CSL WITH CS-CMOS TABLE:1 INVERTER NO OF POWER DELAY(ns) PDP(10^-12 EDP(10^- TRANSISTORS W-S) 21 W-S^2) CBL 3 0.263mw 0.860 0.22618 0.1945 CSL 3 0.117mw 1.69 0.1973 0.334163 CS-CMOS 5 53.039µw 0.48 0.025584 0.0122823 188
  10. 10. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME7. EXPERIMENTAL RESULTS The noise reduction provided by low-noise logic cells has been assessed simply byconsidering the amplitude of the supply current variation. This, however, is very insufficient,since it ignores capacitive noise, and it is not even a rigorous indicator of supply noise, whichdepends on LdIDD/dt. What really matters is the substrate voltage (Fig. 1), and this will beused here to compare the noise performance of CSL, CBL, and conventional CMOS. In this section the inverters are designed using CBL,CSL,and CS-CMOS, existinglogic families like CSL ,CBL and new logic family like CS-CMOS compared in terms powerconsumption ,delay and noise.The 0.18µm technology parameters provided by predictivetechnology are used at 1.8V. The decoupling capacitor CD is the value 0.01pF are used,resulting average power consumption is observed. Calculating energy delay product based on the measured propagation delay (seeTABLE:1) show that the CS-CMOS consumes much lower power than the CSL especially atlower bias currents. Using larger would improve energy-delay product as well. CS-CMOS and CSL families utilize a fixed IB variation in supply do not affect theirperformance as much as in CMOS implementations. The supply current varies with channellength modulation of the current source device. As the propagation delay is linearlydependent on bias current for both the families, a small variation was observed inmeasurements as well. Using larger channel length devices for the Current sources wouldreduce this variation but will need higher voltage headroom7. CONCLUSION We present a new low-noise logic family called CS-CMOS for noise reduction inmixed-signal integrated-systems containing both DSP as well as sensitive analog circuitssuch as phase-lock loops and data converters in a single chip of silicon. The new family isobtained by a simple current-steering modification to the standard CMOS logic preservingmost of the attractive features of CMOS. The well-known constant-current enables asubstantial reduction of switching noise. Extensive simulations and measurementsdemonstrate the speed and power advantages of this family over previously proposed logicfamilies namely CSL and CBL.8. REFERENCES[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low power CMOS digita1design,”IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992.[2] J. M. Rabaey, A. Chandrakasan, and B. Nikolic’, Digital Integrated Circuits: A DesignPerspective, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003.[3] H.-T. Ng and D. J. Allstot, “CMOS current steering logic for low voltage mixed-signalcircuits,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 5, no. 3, pp. 301–308, Sep.1997.[4] Substrate Noise Coupling in Mixed Signal ICs, S. Donnay and G. Gielen, Eds. Dordrecht:Kluwer, 2003.[5] K. Iniewski, Wireless Technologies: Circuits, Systems and Devices. Boca Raton, FL:CRC Press, 2008, ch. 20.[6] D. Leenaerts and P. de Vreede, “Influence of substrate noise on RF performance,” inProc. Eur. Solid-State Circuits Conf., Sep. 2000, pp. 300–304. 189
  11. 11. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME[7] A. Taparia and T. R. Viswanathan, “Low-power short-channel singleended current-steered CMOS logic-gate for mixed-signal systems,” in IEEE Int. Symp. Circuits Syst.,Seattle, WA, 2008.[8] E. Albuquerque et al., “A new low-noise logic family for mixed-signal integratedcircuits,” IEEE Trans. Circuits Syst. I Fundam. Theory Appl., vol. 46, no. 12, pp. 1498–1500,Dec. 1999.[9] M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, no. 10, pp. 1181–1187, Oct.1992.[10] M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, “Power-delay-area noise margintradeoffs in positive-feedback MOS current-mode logic,” IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 54, no. 9, pp. 1916–1928, Sep. 2007.[11] T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar,“Total power optimization by simultaneous dual-Vt allocation and device sizing in highperformance microprocessors,” in Design Autom. Conf., 2002, pp. 486–491.[12] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-StateCircuits, vol. 24, no. 1, pp. 62–70, Feb. 1989.[13] D Bryan, “The ISCAS85 benchmark circuits and netlist format,” North Carolina StateUniversity, Raleigh, NC, 1985.[14] S. Kiaei, D. J. Allstot, K. Hansen, and N. K. Verghese, “Noise considerations formixedsignal RF IC transceivers,” ACMJ.Wireless Networks, vol. 4, pp. 41–53, Jan. 1998.[15] R. J. Baker, CMOS Mixed-Signal Circuit Design. New Delhi, India: Wiley, 2008[16] Dhanisha N. Kapadia and Priyesh P. Gandhi, “Design and Simulation of High SpeedCMOS Differential Current Sensing Comparator in 0.35 µm and 0.25µm 1 Technologies”,International journal of Electronics and Communication Engineering & Technology(IJECET), Volume 3, Issue 3, 2012, pp. 147 - 152, ISSN Print: 0976- 6464, ISSN Online:0976 –6472.[16] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low PowerDesign Techniques of CMOS Digital Circuits” International journal of Electronics andCommunication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012,pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. 190

×