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논리회로 설계실험 담당교수 : 전재욱 담당조교 : 석민식, 송지호
2
1 Analog & digital Sub. Contents. 1.1 Analog & Digital 1.2 Analog 1.3 Digital 3
1.1 Analog & Digital 4 Analog Digital V V T T 0 0
1.2 Analog 5 Input Signal Output Signal 양적인 비례 관계
1.3 Digital 6 Input Signal Output Signal 논리적인 비례 관계
2 Binary digit operation Sub. Contents. 2.1 Binary System 2.2 Boolean Algebra 2.3 Venn Diagram 7
2.1 Binary System ,[object Object],0과 1로 이루어진 수 표기법 : 10001001(2) ,[object Object],8 2 65 32   … 1 2 16   … 0 2 128 64 32 16   8   4   2  1 1000001 2 08   … 0 0   1   0   0    0   0   0  1 Binary : 2 04   … 0 2 02   … 0 01   … 0
2.2 Boolean Algebra  Logical Sum : + ► A + B = Y  0 + 0 = 0  0 + 1 = 1  1 + 1 = 1  Logical Product : • ► A • B = Y  0 • 0 = 0  0 • 1 = 0  1 • 1 = 1  Logical Not : /, ‾,n,` ► A ( /A, nA, A`) = Y  0 = 1  1 = 0 9 Truth Table
2.2 Boolean Algebra – Single Variable  AND   X • 0 = 0   X • 1 = X   X • 0 = 0   X • X = 0  NOT   X = X  OR   X + 0 = X   X + 1 = 1   X + X = X   X + X = 1 10
2.2 Boolean Algebra – Multi Variable ,[object Object], X + Y = Y + X  X • Y = Y • X ,[object Object],X + (Y + Z) = (X + Y) + Z = X + Y + Z X(Y • Z) = X • Y • Z = XYZ ,[object Object],X(Y+Z) = X • Y + X • Z = XY + XZ (X + W)(Y + Z) = X • Y + X • Z + W • Y + W • Z = XY + XZ + WY + WZ ,[object Object],X + XY = X X + XY = X + Y 11
2.3 Venn Diagram 12 XY XY XY
2.4 De-Morgan Law 13 A + B = A • B A • B = A + B
3 Gate symbol Sub. Contents. 3.1 Buffer & NOT Gate 3.2 AND & NAND Gate 3.3 OR & NOR Gate 3.4 XOR & ExOR Gate 3.5 Relativity Theorem 14
3.1 Buffer & NOT Gate 15 NOT Gate Buffer Input Output Input Output
3.1 Buffer & NOT Gate                          - Analog Not Gate Circuit 16 B = 0 C Output Input B E B = 1
3.2 AND & NAND Gate 17 AND Gate NAND Gate Input A Input A Output Output Input B Input B
3.2 AND & NAND Gate                         - Analog AND Gate Circuit 18 B C => C E B E < TR > < Switch > Input A Input B Output
3.3 OR & NOR Gate 19 OR Gate NOR Gate Input A Input A Output Output Input B Input B
3.3 OR & NOR Gate                           - Analog OR Gate Circuit 20 Input A Input B Output
3.4 XOR & ExOR Gate 21 ExOR(XOR) Gate ExNORGate Input A Input A Output Output Input B Input B A ⊙ B = Y A   B = Y
3.5 Relativity Theorem A + B = B + A A+(B+C) = (A+B)+C A(B+C) = A•B+A•C A+0=A A+1=1 A+A=A A+A=1 A=A A+B=A•B A+A•B=A A+A•B=A+B A•B=B•A A(B•C)=(A•B)C A+B•C=(A+B)(A+C) A•1=A A•0=0 A•A=A A•A=0 A=A A•B=A+B A(A+B)=A A(A+B)=A•B 22
4 Combinational Logic Circuit Sub. Contents. 4.1 Combinational Logic 4.2 Half-Adder 4.3 Full-Adder 4.4 Half-Subtracter 4.5 Full-Subtracter 4.6 Subtraction 4.7 Adder-Subtracter 23
4.1 Combinational Logic 24 Input A Input B Output Input C Input D (A+B) (CD) = Output
4.2 Half-Adder 25 Input A SUM Input B CARRY (A    B) = SUM A • B = CARRY
4.2 Half-Adder 26    0 +0 00    1 +0 01    0 +1 01    1 +1 11 Half Adder Input A SUM Input B CARRY Half Adder Half Adder Half Adder Half Adder Half Adder Half Adder Half Adder 0010011 +1000001 1010010 CARRY ?
4.3 Full-Adder 27 SUM Input A Half Adder Half Adder Input B CARRY Input C
4.3 Full-Adder 28 Input A SUM Input B Carry Carry Input
4.3 Full-Adder 29 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 SUM1 SUM2 SUM3 SUM4 SUM5 SUM6 SUM7 SUM8 CARRY Full Adder Full Adder Full Adder Full Adder Full Adder Full Adder Full Adder Half Adder 10010011 +10010001 100100100
4.4 Half-Subtracter 30 Input A Data Half Subtracter (HS) Input B 1 -1 00 1 -0 01 0 -1 11 0 -0 00 Borrow Input A SUM Input B Borrow
4.5 Full-Subtracter 31 Data Input A HS HS Input B Borrow Input C
4.5 Full-Subtracter 32 Input A Data Input B Borrow Borrow Input
4.5 Full-Subtracter 33 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 D1 D2	 D3 D4 D5 D6 D7 D8 Borrow FS FS FS FS FS FS FS HS 10011001 -01000001 101011000
4.6 Subtraction 34 10011001 -01000001 ? One’s complement Two’s complement 10111111 10111110 10011001 +10111111 101011000 10011001 = 153 01000001 = 65 153 - 65 = 88 88
4.7 Adder-Subtracter 35 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 Sel FA FA FA FA FA FA FA FA D1 D2	 D3 D4 D5 D6 D7 D8 10011001 +10111111 001011000 10011001 -01000001 ? Plus & Minus Code
36 End of Page

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논리회로 설계실험 논리회로 설계 실험

  • 1. 논리회로 설계실험 담당교수 : 전재욱 담당조교 : 석민식, 송지호
  • 2. 2
  • 3. 1 Analog & digital Sub. Contents. 1.1 Analog & Digital 1.2 Analog 1.3 Digital 3
  • 4. 1.1 Analog & Digital 4 Analog Digital V V T T 0 0
  • 5. 1.2 Analog 5 Input Signal Output Signal 양적인 비례 관계
  • 6. 1.3 Digital 6 Input Signal Output Signal 논리적인 비례 관계
  • 7. 2 Binary digit operation Sub. Contents. 2.1 Binary System 2.2 Boolean Algebra 2.3 Venn Diagram 7
  • 8.
  • 9. 2.2 Boolean Algebra Logical Sum : + ► A + B = Y 0 + 0 = 0 0 + 1 = 1 1 + 1 = 1 Logical Product : • ► A • B = Y 0 • 0 = 0 0 • 1 = 0 1 • 1 = 1 Logical Not : /, ‾,n,` ► A ( /A, nA, A`) = Y 0 = 1 1 = 0 9 Truth Table
  • 10. 2.2 Boolean Algebra – Single Variable AND X • 0 = 0 X • 1 = X X • 0 = 0 X • X = 0 NOT X = X OR X + 0 = X X + 1 = 1 X + X = X X + X = 1 10
  • 11.
  • 12. 2.3 Venn Diagram 12 XY XY XY
  • 13. 2.4 De-Morgan Law 13 A + B = A • B A • B = A + B
  • 14. 3 Gate symbol Sub. Contents. 3.1 Buffer & NOT Gate 3.2 AND & NAND Gate 3.3 OR & NOR Gate 3.4 XOR & ExOR Gate 3.5 Relativity Theorem 14
  • 15. 3.1 Buffer & NOT Gate 15 NOT Gate Buffer Input Output Input Output
  • 16. 3.1 Buffer & NOT Gate - Analog Not Gate Circuit 16 B = 0 C Output Input B E B = 1
  • 17. 3.2 AND & NAND Gate 17 AND Gate NAND Gate Input A Input A Output Output Input B Input B
  • 18. 3.2 AND & NAND Gate - Analog AND Gate Circuit 18 B C => C E B E < TR > < Switch > Input A Input B Output
  • 19. 3.3 OR & NOR Gate 19 OR Gate NOR Gate Input A Input A Output Output Input B Input B
  • 20. 3.3 OR & NOR Gate - Analog OR Gate Circuit 20 Input A Input B Output
  • 21. 3.4 XOR & ExOR Gate 21 ExOR(XOR) Gate ExNORGate Input A Input A Output Output Input B Input B A ⊙ B = Y A B = Y
  • 22. 3.5 Relativity Theorem A + B = B + A A+(B+C) = (A+B)+C A(B+C) = A•B+A•C A+0=A A+1=1 A+A=A A+A=1 A=A A+B=A•B A+A•B=A A+A•B=A+B A•B=B•A A(B•C)=(A•B)C A+B•C=(A+B)(A+C) A•1=A A•0=0 A•A=A A•A=0 A=A A•B=A+B A(A+B)=A A(A+B)=A•B 22
  • 23. 4 Combinational Logic Circuit Sub. Contents. 4.1 Combinational Logic 4.2 Half-Adder 4.3 Full-Adder 4.4 Half-Subtracter 4.5 Full-Subtracter 4.6 Subtraction 4.7 Adder-Subtracter 23
  • 24. 4.1 Combinational Logic 24 Input A Input B Output Input C Input D (A+B) (CD) = Output
  • 25. 4.2 Half-Adder 25 Input A SUM Input B CARRY (A B) = SUM A • B = CARRY
  • 26. 4.2 Half-Adder 26 0 +0 00 1 +0 01 0 +1 01 1 +1 11 Half Adder Input A SUM Input B CARRY Half Adder Half Adder Half Adder Half Adder Half Adder Half Adder Half Adder 0010011 +1000001 1010010 CARRY ?
  • 27. 4.3 Full-Adder 27 SUM Input A Half Adder Half Adder Input B CARRY Input C
  • 28. 4.3 Full-Adder 28 Input A SUM Input B Carry Carry Input
  • 29. 4.3 Full-Adder 29 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 SUM1 SUM2 SUM3 SUM4 SUM5 SUM6 SUM7 SUM8 CARRY Full Adder Full Adder Full Adder Full Adder Full Adder Full Adder Full Adder Half Adder 10010011 +10010001 100100100
  • 30. 4.4 Half-Subtracter 30 Input A Data Half Subtracter (HS) Input B 1 -1 00 1 -0 01 0 -1 11 0 -0 00 Borrow Input A SUM Input B Borrow
  • 31. 4.5 Full-Subtracter 31 Data Input A HS HS Input B Borrow Input C
  • 32. 4.5 Full-Subtracter 32 Input A Data Input B Borrow Borrow Input
  • 33. 4.5 Full-Subtracter 33 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 D1 D2 D3 D4 D5 D6 D7 D8 Borrow FS FS FS FS FS FS FS HS 10011001 -01000001 101011000
  • 34. 4.6 Subtraction 34 10011001 -01000001 ? One’s complement Two’s complement 10111111 10111110 10011001 +10111111 101011000 10011001 = 153 01000001 = 65 153 - 65 = 88 88
  • 35. 4.7 Adder-Subtracter 35 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 Sel FA FA FA FA FA FA FA FA D1 D2 D3 D4 D5 D6 D7 D8 10011001 +10111111 001011000 10011001 -01000001 ? Plus & Minus Code
  • 36. 36 End of Page