Giannakas____icecs2010
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RF to DC conversion / RF Harvesting
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Giannakas____icecs2010
- 1. A 2.45GHz Power Harvesting Circuit In 90nm CMOS G.Giannakas, F.Plessas, G.Nassopoulos, G.Stamoulis T4L – E.4 Paper #423 Department of Computer & Communication Engineering, University of Thessaly, Volos, Greece
- 8. General Cascaded Topology (N=4)
- 10. Floating Gate (FG) nMOS
- 11. 1a. Proposed Dickson VD- pseudo FG And in Cadence …
- 12. 1b. Proposed Dickson VD- pseudo FG
- 13. 2. Proposed GCCR – pseudo FG
- 14. Output Voltage Limiter W/L = 1um / 100nm
- 16. 2 . Bests of 1-stage Rectifiers, at Load 1M Ω Proposed VD-FG GCCR-ZVT GCCR-LVT Back-Gated VD Vin rec=250mV 16
- 17. 3a . Different 1-stage Rectifiers PMOS - VD Proposed VD-FG,best VCE VD-ZVT: Check the Leakage after 2us GCCR-ZVT faster performance, no leakage, small ripple! NVC-LVT Simple VD-RFMOS Back-Gate and LVT VD Vin rec=250mV 17
- 18. * Fab. Offers only n-ZVT 3b. ~5 476 1021 5.0 388 469 13. Proposed VD (FG-8) ~5 400 918 5.1 302 480 12. Proposed VD (FG-1) -- -- -- >10 58 253 11. VD RF Fet >9 280 974 >9 137 423 10. VD Back-g. LVt >9 240 820 >9 124 392 9. VD n-LVt .76 1100 1363 0.4 405 420 8. GCCR n-ZVt -- -- -- 9 207 406 7. GCCR Back-g. LVt 8 412 932 2.2 266 409 6. Proposed GCCR LVt 8 350 850 >10 186 375 5. GCCR LVt -- -- -- .094 263 301 4. NVC RF Fet 6 515 1598 .082 256 291 3. NVC LVt -- -- -- .076 244 277 2. NVC Back-g. LVt 6 560 1504 .380 264 302 1. NVC nZVt, pLVt * Delay (us) V dc , 1MΩ (mV) V dc (mV) Delay (us) V dc , 1MΩ (mV) V dc (mV) Topology (CMOS) 4-stages ( V in rec =250mV) 1-stage Rectifiers ( V in rec =250mV)
- 19. 4 . 20 stages GCCR-ZVT rectifier and the performance of Limiter
- 20. 5. Performance Summary (20-stages GCCR-ZVT) -19.73 29.21 14.68 1.25 60.4 2.55 107 1 V in rec is the voltage at the input of the rectifier (after the boosting network) 2 Due to Q L , V in rec is divided by 3.28 to calculate the total PCE. -6.34 49.00 41.33 9.80 75.0 15.0 500 -10.77 40.17 40.49 5.82 68.3 8.20 300 -12.35 37.80 24.59 3.78 67.5 6.75 250 -20.03 26.80 12.32 1.07 58.8 2.35 100 -23.93 21.60 8.00 0.57 45.5 1.25 66 Sens. (dBm) VCE % PCE 2 % V out , (V) VCE % V out (V) V in rec 1 (mV) With Resistive Load R L =1MΩ Without Resistive Load
Editor's Notes
- Thank you Mr chairman. I am very pleased to present our work on the RF power harvesting area, with conversion of RF power, by a rectification mechanism, to a DC power, capable to drive other stages and components. A new circuit is implemented in 90nm (ninety nanometers) CMOS at 2.45GHz (two point fourtyfive gigahertz) – in ISM (industrial, scientific, medical) band of RFIDs – (radio frequency identification transpoders) and I’ll be talking about this improvement.
- It’s a design novelty based on voltage threshold reduction by a pseudo -Floating Gate (FG) modified basic rectifier cell. Generally diodes or diode-connected MOS transistors are used to implement rectification from RF to DC power as nonlinear devices. The efficiency of rectification mainly is evaluated by Power and Voltage Conversion Efficiency (usually named as PCE and VCE respectively). The above Voltage threshold reduction method reduces the inherent diode/MOS transistor’s forward-bias voltage drop which affects positively the overall power efficiency and so on the delivered dc voltage to the following modules.
- The basic rectifier’s structure is composed commonly by the antenna which receives the RF power, the resonant-matching tank which plays a dual role, as for voltage boosting at resonance at the specific frequency of operation, accordingly to the Quality factor Q, as to inductively compensate (with L-match) the input impedance of rectifier that follows. Then we have the main rectifier with a diode connected MOS transistor that plays the role of rectification. In our approach we focused more on matching than tuning to 2.45GHz, to achieve large loaded Quality factor of the boosting circuit and avoid impedance mismatch.
- If Vout is the input voltage of the rectifier (at the output of the boosting network) which turns on the MOS (diode connected or switch) transistors and makes effective the rectification of RF power, then, by taking into account the free-space path losses (FSPL) for the specific application (with values, Gt = Gr = 0dBi, QLoaded = 3.28, Rs = 50Ω, λ = 0.123m, Pt = 0.5W) we derive a simple hyperbolic function between distance d and the voltage at the input of rectifier , for fast calculations, via this plot. For example at a distance of 1m we have 227mV at the output of boosting network and this voltage is responsible for turning on of MOS diode connected transistors as we mentioned before. In this case the received power will be equal to 48 μ Watt and this is a very low power situation. The loaded quality factor Q L of this network, under working conditions, was found to be approximately equal to 3.28 and we use this value from so on. The transmitted power Pt was taken only 500mW according to the European regulations ( from ETSI - European Telecommunications Standards Institute ) of RFID transpoders at 2.45GHz. Of course the ISM band allows larger Transmitted power (4W indoor for example) but we are focused specifically only at RFID region.
- Amongst a lot of combinations and topologies we distinguish three practical circuits, with an excellence in efficiency as rectifiers. The oldest and predominant topology has been introduced by J. Dickson as a Voltage Doubler, for DC-DC conversion and is the most frequently and efficiently used in literature. A voltage doubler consists of a dc-level shifter (formed by M1, C1) and a peak detector (formed by M2, C2) and suffers from voltage drop caused by Voltage threshold and the channel resistance of the MOSFETs. It derives from charge pumps or DC-DC voltage converters area, where a two-phase clock were used to control the charge transferring between capacitors. Now the RF+ and RF- signals plays the role of this 2-opposite phase clock and the old connections of CLKpos(+) and CLKneg(-) of DC-DC charge pumps are now RF+, RF- respectively.
- Another common architecture is the Gate Cross Coupled Rectifier (GCCR), where two diode connected MOS and two switching MOS trans. are used. This is a modified version of the bridge full wave rectifier, but lower voltage is required to turn the MOS fully on due to the only one voltage drop in every half period. In the case of full wave bridge rectifier we have double voltage drop in every half period because 4 diodes are used there, two per semi-period. We use this topology as for a cascaded rectifier (of 20 stages) for the production of 1.2V that needed by analog blocks in RFID tags (it’s well known that Digital Blocks demands 1V or less) as for the production of a dc voltage (that we call VFG) for the proposed pseudo -floating gate rectifier. It seems that has not only good efficiency, but also fast response and small Voltage ripple against others.
- A third finally topology, is the fully cross coupled structure named as negative voltage converter (NVC) or H-bridge or 4-transistor cell in which cross coupled n- and p-MOS transistors are used. A drawback of this topology is the reverse flow, without blocking, of current when Voutdc exceeds Vin . In this topology, in contrast to others with diode MOS, no threshold voltage drop exists because the transistors act as switches. Anyway a negligible drop occurs due to the small on resistance rds of MOSFETs switches and due to reverse currents that may exist. The bulk connections in this figure, are used to avoid parasitic bipolar latch-up and leakage currents, so NMOS bulk is connected to earth (as lower potential) and PMOS to the highest potential (here is output connected).
- Generally, a DC-DC converter is transformed to a RF-DC converter of N stages, by connecting the VLOW input of the 1st stage to the ground. A cascaded system, can be formed by series connection of several similar basic cells, for the last two topologies (GCCR, NVC) and almost similarly for the Dickson’s, where capacitors to the RF+ and RF- paths must be added to avoid reverse current flow and to control the build-up of large dc output voltage. Off course capacitors must be neglected in the case of Cascaded Voltage Doublers, because Dickson’s Topology has already two capacitors in each basic cell. The operation is then similar like a charge pump (CP) voltage multiplier or charge transfer switch (CTS) device (from the area of DC-DC converters) and we can obtain large dc outputs capable to drive other analog or digital blocks.
- In passive tags no battery exists. Due to the lack of power supply, the reduction of dead zone of rectifier has to be done in these low power and voltages, by techniques that they don’t need additional power at the difficult start up of rectifier. Nowadays, although length size ( L ) continuously decreases, Vth doesn’t scale down with the same rate. Threshold Vth is the gate to source voltage which accumulates enough charge into the gate to sustain the depletion region. If we consider the MOS transistors as rectifiers, is clear that a reduced threshold voltage is of crucial meaning for their opening. The extremely low (or even zero) Vth MOS transistors suffer from increased leakage current and for this, their efficiency is very poor, especially if they have been used in all stages of a cascaded rectifier. Here a trade off exists between the need of small Vth to handle very low voltages and the need of good closing of MOS switches, which can be improved by large Vth. When the transistor has very small threshold its reverse blocking capability vanishes, because MOS is always on in sub-threshold region or weak inversion for such low RF voltages almost equal to Voltage threshold and large current occurs in the reverse direction. Typically the option of multiple threshold voltages is realized by adjusting the thickness of the gate oxide ( tox ) or the doping profile in the channel, which complicates fabrication process and requires higher cost. Alternatively, Vth can be controlled by the bias voltage at the body (back-gate) terminal . A forward bias on the bulk–source junction ( VBS >0) will cause a Vth reduction , due to the reverse body effect as shown in Figure. The bulk driven threshold reduction (or backgated, or second-gated MOS Vth reduction) is defined by the common potential of source and bulk (so Bulk and Source must be permanently connected).
- Another technique uses Floating Gate transistors (FG) which imitate the operation of depletion mode transistors. Usually, a (second) control gate is used, which is responsible for the charge transferring control. This is achieved by hot carrier injection through gate oxide or FN (Fowler-Nordheim) tunneling through this control gate. The Vth of these FG-MOSFETs can be set after or during fabrication to a specific value, according to the amount of charge that has been injected to their control gate. However, generally FGMOS transistors are not even as an option in nowadays processes. May be this is (if we forget cost) because in nanometric (<100nm) lengths the gate oxide is very thin (few (20-60) angstroms) and a measurable gate current through the SiO2 silicon oxide exists due to lack of high impedance . So, gates can’t store charge that needed in this threshold reduction method. Another disadvantage of this method is the need of extra circuitry and usually of a battery for generation of the necessary bias or clocks. Obviously for passive RFIDs this is impossible.
- According to the Dickson’s basic VD cell and the basic cell of gate cross connected rectifier - GCCR, we introduce a modified basic cell the pseudo-FG with the addition of two MOS diode connected transistors and two capacitors at the drain-gate connection path as is depicted here. The signal VFG that is essential for the reduction of threshold, can be produced by one efficient stage of a NVC or a GCCR basic cell using zero Vth (ZVT) MOSFETs. A voltage is inserted in the drain-gate path of the diode connected M1, M2 and if VFG = Vth , then Vs = Vd . Thus the threshold voltage of the transistors M1, M2 is reduced accordingly to the value of VFG . This approach improves VCE and reduces time delay (settling time) and ripple.
- Off course our solution is quasi-static and not dynamically optimized due to the small dynamic performance of VFG variation for different RF input voltages. So the number of stages of ZVT rectifier basic cells which forms the voltage VFG, depends on the RF voltage level…
- Anyway, the charge is trapped between gate (oxide is an isolator) and drain without a discharging path due to the placing of a MOS capacitor there. So the voltage bias across Gate oxide and MOS capacitor is almost fixed. Also our solution can be used only in the case of diode connected MOS, so NVC rectifier which has 4 MOS switches has no improvement by this approach but only by the use of ZVT or LVT MOSFETs that fabrication offers.
- Of course, using the previous options in near-field (small distances), a voltage limiter must me employed at the output of the circuit which produces the FG signal, to avoid the appearance of a large voltage in drain-gate connection and hence the increase of Vth . In the voltage limiter, the two NMOS diode connected transistors act as a “zener” diode. As soon as VRF exceeds the sum of the voltage thresholds of the two NMOS transistors, current starts flowing through R . When V R > V th,PMOS then the PMOS turns on and additional current flows through the PMOS, to reduce the increase in the output voltage and protect the following modules. This limiter is also used at the output of a 20-stages ZVT GCCR rectifier we use.
- A series of simulations (mainly transient response) have been performed to investigate the performance of previously reported rectifiers compared with the proposed one. Initially, three different 1-stage rectifier topologies, the GCCR, the NVC and the VD have been simulated, for various threshold voltages Vth (e.g. RFMOS: n/420mV, p/-350mV, LVT: n/320mV, p/-260mV, nZVT: -10mV, back-gated). The proposed topology VD - FG achieves the best voltage conversion efficiency (VCE = 96% and 93.8%) especially when the FG signal is generated by a NVC-nZVT topology rather than a GCCR-ZVT . Between all the VD topologies (Fig.), the use of a back-gate LVT, results in a fine VCE equal to 84.6%, the use of a simple RFMOS results in a VCE equal to 50.6% and the use of a LVT results in a VCE equal to 78.4%.
- The second proposed topology, the GCCR-FG, achieves a slightly better VCE than the back-gate GCCR, while the GCCR-ZVT achieves the best one. If a 1MΩ load exists, the proposed VD achieves the best performance between the VDs when is driven (FG signal) by the GCCR-ZVT. This is also true for the 4-stage rectifier.
- In a last report of our 1stage rectifiers we can focus at the best time response and the minimum time delay of GCCR-ZVT without any leakage, and the best VCE of out proposed VD-FG when the FG signal is produced by 1 stage of a GCCR-ZVT cell. Also we must check and the case of VD with ZVT MOS which suffers from large leakage currents after 2us something expected for ZVT transistors with small or even zero threshold. The main reason for the bad generally performance of zero Vth MOS transistors, is due to the rapid leakage of reverse current when a transistor had to be 100% turned off.
- In this table, we must focus at numbers 6,12,13 where the performance of our proposed rectifiers is obvious for 1 stage rectifier, especially in the case of VD-FG when FG signal is driven by number 1 NVC (nZVT,pLVT) cell for 1stage rectifier, and when FG is driven from number 8 GCCR-ZVT cell in the case of 4-stage rectifier. Our proposed GCCR-LVT has slightly better performance than the backgated one (numbers 6 and 7) while the best of GCCR is that with ZVT MOS (n.8) and without any leakage currents as we mentioned before! It should be noted that all these topologies have been designed and simulated using the same process and conditions without use of values from papers or other works with relative similarity.
- Finally, a real case rectification circuit is presented, able to generate a dc voltage of 1.25V by an extremely low RF input. A VD-ZVT 20-stages rectifier had slightly better performance than other schemes but after some time (μs), according to our research, the Vdc drops out, due to large leakage currents. The NVC-nZVT rectifier (20-stages again) had a similar problem. The main reason is possibly because of the use 2 NMOS switches (of zero Vth ) and the fact that when the one is closed the other is not 100% opened and vice-versa. Only the GCCR-ZVT cell doesn’t suffer from this drawback, so this topology has been used in the proposed 20-stages rectifier .
- Our efforts were focused on achieving a large VCE rather than a large PCE so our MOS have small dimensions (W and L). To generate an output voltage of 1.2V, an input voltage of 180mV is needed when RL =200kΩ and PCE=23.91%, or 135mV when RL = 500kΩ and PCE=17%. It should be noted that Power and Voltage Conversion Efficiency (PCE, VCE) are determined by these equations where N is number of cascaded stages and QL the loaded quality factor (resonator and rectifier). For an input power of -19.73dBm, the proposed rectifier achieves a PCE 14.68% at a load 1ΜΩ and that means a voltage 107mV in the input of rectifier or 32.62mV in the input of resonator or boosting circuit or a range distance of 2.12m according to our real case assumptions, so our design is more efficient if compared to previously reported works, especially when taking into account, the transmitted (eirp) power, the frequency of operation (FSPL), the antenna gains and radiation resistance Rs , and finally the load RL . So, with the aid of the proposed technique of threshold reduction, better performance is achieved using CMOS compatible fabrication procedures without additional cost or masks.