Presentation by Andreas Schleicher Tackling the School Absenteeism Crisis 30 ...
Huffman data compression-decompression
1. An Efficient Test Vector Compression Scheme
Using Selective Huffman Coding
Under the guidance of Prof.Aarthi
Presented By
Dipu P
12MVD0060
Venketa Ramesh E 12MVD0062
HarshaVardhan B 12MVD0063
2. INTRODUCTION:
A SOC based design provide several design challenges
These chips are composed of several reusable intellectual
property (IP) cores
The volume of test data for a SOC is growing rapidly as IP
cores become more complex
Extreme challenges to current tools and methodologies
3. 1/2
In present days the complexity of SOC is keep on
increasing, so for testing those IC’s requires huge cost
Various factors of ATE are limitations to a testing technique
and methodology
Various techniques available for reducing the test data
They are BIST and Test Data Compression
4. 1/3
•
Various methods
i) code based schemes
ii) Linear-decompression based schemes
iii) Broad cast based schemes
• Code Based Schemes
1) Fixed to Fixed
2) Fixed to Variable
3) Variable to fixed
4) Variable to Variable
7. 3/4
Feed the Test File.
Divide in to set of four bits.
Sorting the 4-bit block descending order of their
occurrence(frequency).
Select the most frequently occurring bit sets.
(Those having High Frequency).
Huffman Coding For the Selected Set.
Set MSB=1 for the Selected encoded bits.
Set MSB=0 for unselected bit sets.
Zero tag indicate no need of decompression .
17. 2/2
Total no of bits=240
Compressed bits for Huffman=178
Compressed bits for Huffman=194
18. CONCLUSION
Importance of compression and decompression in testing field.
Huffman Compression-Decompression
Selective Huffman Compression-Decompression
Simple-Decoder with Lesser Logic Elements.
Results indicate that the proposed scheme can provide test
data compression nearly equal to that of an optimum
Huffman code with much less area overhead for the
decoder.
19. REFERENCES
[1] Xrysovalantis Kavousianos, Emmanouil Kalligeros, and Dimitris Nikolos” Optimal Selective
Huffman Coding for Test-Data Compression “IEEE TRANSACTIONS ON COMPUTERS,
VOL. 56, NO. 8, AUGUST 2007
[2] Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, and Nur A. ToubaAn “Efficient Test Vector
Compression Scheme Using Selective Huffman Coding” IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSJUNE 2003.
[3] J. Aerts and E. J. Marinissen, “Scan chain design for test time reduction
in core-based ICs,” in Proc. Int. Test Conf., 1998, pp. 448–457.
[4] I. Bayraktaroglu and A. Orailoglu, “Test volume and application time reduction through scan
chain
concealment,” in Proc. Design Automation Conf., 2001, pp. 151–155.
[5] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing For Digital, Memory, And
MixedSignal VLSI Circuits. Norwell, MA Kluwer, 2000.
[6] Ji-Han Jiang*, Chin-Chen Chang*, and Tung-Shou Chen” An Efficient Huffman Decoding
Method
Based onPattern Partition and Look-up Table”
[7] Kinjal A. Bhavsar” Analysis of Test Data Compression Techniques Based on Complementary
Huffman Coding” International Journal of Engineering Science and Technology (IJEST)
