2. Qualification
Laurea in Ingegneria Elettronica 1996
110 cum laude
MSc Honour
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3. Competence areas
ASIC Design: Front End
RTL and Gate Level Simulation: VHDL, Verilog with Mentor Modelsim, Cadence
Verilog XL, NC Sim, NC Verilog
Linting: Synopsys Leda, Cadence HAL
ASIC design: Back End (Standard Cell)
Synthesis: Synopsys Design Compiler
Static Timing Analysis: Synopsys PrimeTime
DFT: Synopsys DCXP and TetraMax
Formal Verification: Synopsys Formality, Cadence Verplex LEC
Place & Route: Cadence SoC Encounter, training for Compass Automation back-
end suite (mid 1997)
ASIC design: Back End (Full Custom, Digital IC)
Layout, DRC, LVS with Cadence tool chain (Composer-Spectre-Virtuoso-Diva)
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4. Competence areas
Verification Strategy set-up: transaction based, self checking
test cases with output logging (optional input command parser)
Functional Verification: Synopsys SDH WorkBench, VERA Test
bench Generator
Code Coverage Analysis: TransEDA VnCover and Mentor
Graphics Modelsim
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5. Competence areas
ASIC-FPGA conversion, FPGA prototyping, lab testing
FPGA Design: complete design flow with Altera, Xilinx and Actel
Synthesis: FPGA Complier II, Synplycity Synplify, Leonardo Spectrum,
Xilinx XST, Altera QuartusII
Place & Route tools: Altera QuartusII and MaxPlusII, Actel Libero, Xilinx
M1/ISE.
Scripting: PERL, sed, awk, TCL (for Synopsys/Cadence tool
chain)
Embedded Systems: good understanding of processes, tools,
and of Real Time Oses.
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6. Design Domains
Telecom: E1,T1,SDH-STM1/SONET-STS3,OC3
Datacom: 10/100 Ethernet MAC
Audio: AES3 -Audio Engineering Standard 3-
Multi-media: I2C, SPI
ARM microprocessors, AMBA AHB bus
8051 family, SFR bus
Freescale (PowerPC) MPC5554 MCU
Avionics: DO-254, ARINC429
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