This is an overview of the short course to be taught by Kamal Karimanal at the 2013 ECTC conference (May 28th).

1. Kamal Karimanal
Cielution LLC
Thermal and Mechanical Simulation
Techniques - An Introductory Course
for 3D IC Enablement Professionals
A Sneak Peek
(c) Cielution LLC

2. Intended Audience
Thermal and Mechanical Simulation Experts with
interest applicability to 3D IC Technology
Engineering Professionals engaged in enabling 3D
IC products
System on Chip (SOC) Architects and design
professionals interested in Thermo-Mechanically
aware methodology implementation
Customer support / supply chain technical interface
professionals who are interested in collaborative
Engineering.
(c) Cielution LLC

3. Motivation for Thermo-Mechanical Simulation
3D IC roadmap has introduces brand new
Thermal and Mechanical challenges.
Test Chip & Test vehicle programs effective, but
expensive
• May not offer information for root cause identification
Thermo Mechanical modeling is an effective filter
before finalizing test vehicle design and testing
plans.
Hence, knowledge about Engineering Simulation
tools, methodologies and capabilities will
empower modeling professionals as well as
other technologists enabling 3D IC technology.
(c) Cielution LLC

4. (c) Cielution LLC
Temperature Distribution on the chips

5. (c) Cielution LLC
Temperature Distribution on the chips
Temperature increased by 16% due to hot spot proximity

6. CielSpot: High Level Workflow
(c) Cielution LLC
CielSpot™
Stack Info
Package
Info
Material Properties
Solve in
Commercial
Thermal Solver
Access to Model in the commercial solver’s native format
Automated Geometry,
Meshing & Problem Setup
Intelligent Solver Controls
Automated Thermal Snapshots
& Temperature data
Compact Thermal
Model

7. Demo of CielSpot CTM for Quick
Estimation of Temperature
Distribution
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8. Validation Results
FEA (ANSYS) Prediction of Temperature
Distribution on Memory-I
CielSpot-CTM Prediction of
Temperature Distribution on Memory-I
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9. CielSpot CTM Validation
Predicted Temperature Rise_vs. Error
-1.50%
-1.00%
-0.50%
0.00%
0.50%
1.00%
1.50%
50 55 60 65 70 75
Predicted Temperature
Error%
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10. Mechanical Stress Modeling of
3D ICs
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11. 3D Assembly Flow I: D2D, Chip Stack First, CUF
(c) Cielution LLC
Step 1: Mem Stack to Logic
(@ reflow Temperature 230 C)
Step 2: Capillary Underfill
Step 3: Chip Stack to Substrate
(@ reflow Temperature 230 C)
Step 4: Capillary Underfill Step 5: Overmolding or Lid Attach

12. Underfilling Options
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Capillary Underfill (CUF)
No Flow Underfill
Molded Underfill (Vacuum Assist)
Copper Nails + Thermo
Compression
No Need to Underfill

13. Flow I & Flow II substrate warpage on attach to Chip
stack, overmolding & Cool down
(c) Cielution LLC
T=20 Deg C results
No Warpage at attach temperature since intrinsic stresses at attach
were not considered

14. -100
0
100
200
300
400
500
0 5000 10000 15000 20000 25000 30000 35000 40000
Chart Title
Logic_die_warpage_after_stack_attach Substrate_warpage_after_stack_attach
Sub_warpage_after_full_assembly
Flow I Consolidated Room Temperature Warpage
Evolution
(c) Cielution LLC
T=20 Deg C results

15. Thermo-Mechanical Model Supply Chain Gaps?
Materials Characterization
Characterization
• Materials
• Failure Metrics & Criteria
Underfill Characterization
needs:
• Non Linear Material
Properties
o Modulus, CTE, Poisson
’s Ratio
o Temperature
dependence
o Viscoelasticity?
(c) Cielution LLC
0
1
2
3
4
5
6
7
8
9
0 50 100 150 200
RelaxationModulus(GPa)
Temperature (Deg C)
5 sec
120 Sec
Tg
Tg
Park & Feger
ECTC, 2008
Huang et al., Electronic
Materials &
Packaging, 2002

16. CielMech™ for Thermo-
Mechanical Modeling
Automation
(c) Cielution LLC

17. Stress Drop off in the vicinity of TSV
(c) Cielution LLC
0.00E+00
5.00E+07
1.00E+08
1.50E+08
2.00E+08
2.50E+08
3.00E+08
0.00E+00 5.00E-06 1.00E-05 1.50E-05 2.00E-05 2.50E-05 3.00E-05 3.50E-05
AxialStress(Pa)
Radial Distance from TSV periphery
Chart Title
5 um Dia
10 um Dia Via

18. % Mobility Change Plot from FEA
(c) Cielution LLC
n-type (electron Carriers)
100 Plane
6

19. Failure Modes
Barrier/Liner Delamination
• Ryu et al. StressInduced
Delamination Of Through Silicon
Via Structures, AIP, conference
Low K and Metal Failure Due
to Copper Pumpout
• Vogel et al, Nonlinear copper
behavior of TSV for 3D-IC-
integration and cracking risks
during BEoL-built-up
(c) Cielution LLC
Shear mode
Liner/Barrier Delamination

20. Why Fracture Mechanics?
Stress at any location is only an indicator of load
transferred.
It doesn’t tell us if the material will fail under a
given stress level
• So, a somewhat justifiable use of stress estimate are
as follows:
o for apple to apple comparison of the maximum stresses as
a function of on design and process parameters
o Ensuring equivalent stresses to be below Yield stress
(assuming yield as the critical criteria)
• So long as singularity and mesh dependence effects
are eliminated in the stress estimates being
compared.
Fracture mechanics modeling addresses these
issues
(c) Cielution LLC

21. Questions? Comments?
Kamal Karimanal
kamal@cielution.com
Only a sneak peek…
Register to ECTC 2013 PDC to attend the full Course:
http://www.ectc.net/program/63ECTC-FINAL.pdf
(c) Cielution LLC