✅ Contenido:
Introduction
AVR Architecture
➡️ Acquisition
➡️ Identification
➡️ Control Design
ARM Architecture
➡️ GPIO Control
Automation Solutions
➡️ Industrial Shields
FPGA Architecture vs Hardware Design
➡️ Behavioral Signal Processing with Machine Learning Based on FPGA
➡️ More FPGA projects
➡️ On going jobs
Future Work
⭐ For more information visit our blog:
https://vasanza.blogspot.com/
2. Topics
• Introduction
• AVR Architecture
• Acquisition
• Identification
• Control Design
• ARM Architecture
• GPIO Control
• Automation Solutions
• Industrial Shields
• FPGA Architecture vs Hardware Design
• Behavioral Signal Processing with Machine Learning Based on FPGA
• More FPGA projects
• On going jobs
• Future Work
Industrial Automation and Internet of Things
Based on Open-Source Hardware
24. FPGA Architecture
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html
25. FPGA Architecture
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html
26. FPGA Architecture
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html
27. Field Programmable Gate Arrays (FPGAs)
FPGA Architecture
Configurable Design (MSI)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html
28. FPGA Architecture
Configurable Design (Soft-processor NIOS II)
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
29. FPGA Architecture
Hard-processor vs Software-processor
Arreglos de puertas lógicas programable
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
30. DE10NANO - Terasic
Arquitectura H/S Processor - Cyclone V
NIOS II
processor
FPGA Architecture
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
31. FPGA Architecture
Ejemplo: Runtime CPU ARM Architecture
515 ms
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
32. FPGA Architecture
Ejemplo: Runtime NIOSIIx2 Multiprocessor System
* Es 2,076 veces más rápido
248 ms
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
33. Behavioral Signal Processing with Machine Learning Based on FPGA
FPGA Architecture
Asanza V., Sanchez G., Cajo R., Peláez E. (2021) Behavioral Signal Processing with Machine Learning Based on
FPGA. In: Botto-Tobar M., Zamora W., Larrea Plúa J., Bazurto Roldan J., Santamaría Philco A. (eds) Systems
and Information Sciences. ICCIS 2020. Advances in Intelligent Systems and Computing, vol 1273. Springer,
Cham. https://doi.org/10.1007/978-3-030-59194-6_17
34. Behavioral Signal Processing with Machine Learning Based on FPGA
Overview of our proposed architecture
Results obtained while testing different ser of neurons in
Hidden Layer
Resources used by FPGA
FPGA Architecture
Asanza V., Sanchez G., Cajo R., Peláez E. (2021) Behavioral Signal Processing with Machine Learning Based on
FPGA. In: Botto-Tobar M., Zamora W., Larrea Plúa J., Bazurto Roldan J., Santamaría Philco A. (eds) Systems
and Information Sciences. ICCIS 2020. Advances in Intelligent Systems and Computing, vol 1273. Springer,
Cham. https://doi.org/10.1007/978-3-030-59194-6_17
35. V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory usage embedded in FPGA," 2020
International Conference on Applied Electronics (AE), Pilsen, Czech Republic, 2020, pp. 1-4, doi:
10.23919/AE49394.2020.9232863.
Monitoring of system memory usage embedded in FPGA
Comparison in Usage of memory vs. Time Comparison of memory usage
Representation of communication between FPGA and HPS
More FPGA projects
36. C. Cedeño Z., J. Cordova-Garcia, V. Asanza A., R. Ponguillo and L. Muñoz M., "k-NN-Based EMG Recognition for Gestures
Communication with Limited Hardware Resources," 2019 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced &
Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City
Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI), Leicester, United Kingdom, 2019, pp. 812-817.
k-NN-Based EMG Recognition for Gestures Communication with Limited Hardware Resources
More FPGA projects
37. Innovate FPGA 2019: Artificial Intelligence at the Edge!
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS027
Artificial Neural Network based EMG recognition for gesture communication
More FPGA projects
38. Innovate FPGA 2019: Artificial Intelligence at the Edge!
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS027
Artificial Neural Network based EMG recognition for gesture communication
More FPGA projects
39. EMG Signal Processing with Clustering Algorithms for motor gesture Tasks
Asanza, V., Peláez, E., Loayza, F., Mesa, I., Díaz, J., & Valarezo, E. (2018, October). EMG Signal Processing with
Clustering Algorithms for motor gesture Tasks. In 2018 IEEE Third Ecuador Technical Chapters Meeting (ETCM) (pp. 1-
6). IEEE
https://www.myo.com/
More FPGA projects
43. Energy Meter (Pzem-004t)
Características:
1. Rango de voltaje: 80-260V AC
2. Rango de lecturas: 0-9999.99kwh
3. Resolución de voltaje: 0.1V
4. Rango de corriente: 0-100A
5. Resolución de corriente: 0.001A
6. Rango de potencia: 0-23kw
7. Resolución de potencia: 0.1W
8. Frecuencia: 45-65Hz
9. Dimesiones: 9*6.05*2.3cm
10. Certificaciones: CE, FCC BV
11. Comunicación: TTL
Future Work
51. Future Work
Bansal, S., & Kumar, D. (2020). IoT Ecosystem: A Survey on Devices, Gateways, Operating Systems,
Middleware and Communication. International Journal of Wireless Information Networks, 1-25.
52. Víctor Asanza
Mail: vasanza@espol.edu.ec
Facultad de Ingeniería en Electricidad y Computación, FIEC
Escuela Superior Politécnica del Litoral, ESPOL
Campus Gustavo Galindo Km 30.5 Vía Perimetral, P.O. Box 09-01-5863
090150 Guayaquil, Ecuador
For more information