In this project work, I have tried to design and implement a Fractional Unsigned Binary Divider which is capable of calculating the quotient as well as the remainder, through Addition-Comparison Algorithm. The remainder is further processed to give the final division result in floating-point decimal format which can be displayed in 7-segment display.

1. NAME – SUPRATIK MONDAL
ENROLLMENT NUMBER – 510719009
DEPARTMENT – Electronics and Telecommunication Engineering
YEAR OF STUDY – 3rd Year
Indian Institute of Engineering Science and Technology, Shibpur, Howrah - 711103

2. INTRODUCTION
In this project, an Fractional Unsigned Binary Divider has been designed. This Divider is capable of finding out the
Remainder beside the Quotient. This Remainder is further processed to find out the actual result of the division. Here,
basically the result will come in floating numbers (two places after fraction point)which can be displayed in 7-segment
display. The result after division is represented as 16-bit BCD format, where first 8-bit is for integer part (4-bit for each
first and second digit) and last 8-bit is for fractional part (4-bit for each first and second place digits). The whole
algorithm has been designed and simulated with Verilog Language and it is implemented in a FPGA board.

3. HARDWARE ARCHITECTURE OF THE ALGORITHM
The below diagram shows the system hierarchy of the whole Fractional Unsigned Binary Divider.

4. The below diagram shows the block diagram representation of the 4-bit Fractional Unsigned Binary Divider and
also its sub-modules.

5. The below diagram shows the Block diagram for the Binary Divider (mentioned in the previous diagram).

6. NOTE:
It is to be mentioned that in the above figure, “n” is 4. Also, it is a 4-bit Divider and we are displaying two digits each for
integer and fractional part, so, we are converting into 8-bit BCD. For different values of “n” the dimensions of the BCD
will change accordingly.
Mathematical Analysis of Time of Division (TOD)
From the above diagrams, it is quite clear that the whole process will start on triggering the “Start Of Division (SOD)”
pin and end by giving an acknowledgement at “End Of Division (EOD)” pin. After starting the process the whole
design will take few iteration cycle and will give the final result. So, if we keep the divisor fixed and increase the
dividend, then the TOD will increase.
Supposing that “A” is dividend and “B” is divisor:
So,
Case-I: (Zero-Remainder Division)
B will increment like – B, 2B, 3B, ………………… nB, such that nB is equals to A. So, the TOD will be (n-1)𝐓𝐜𝐥𝐤.
Case-II: (Non-Zero Remainder Division)
B will increment like – B, 2B, 3B, ……………….. nB, such that nB is greater than A. So, the TOD will be n𝐓𝐜𝐥𝐤.
So, it is clear from the above equations that as “A” increases, then “B” will have to take more iterations two be equal or
greater than “A” and will increase the TOD.

7. HARDWARE RESOURCE UTILIZATION
The whole algorithm has been implemented in “Artix-7 (xc7a35tcpg236-1)” FPGA board. The hardware resource utilization
table and power utilization is given below:
Resource Utilization Available Utilization (%)
Look-up Table (LUT) 114 20800 0.55
Flip-Flop (FF) 39 41600 0.09
I/O 28 106 26.42
POWER CONSUMPTION
Type of Power Consumption Power Consumed (Watt)
Dynamic Power 8.856
Device Dynamic Power 0.124
Total Power 8.98