FREQUENCY COUNTERS AND TIME-INTERVAL MEASUREMENTS.pdf

CHAPTER 10
FREQUENCY COUNTERS
AND TIME-INTERVAL
MEASUREMENTS
10-1 SIMPLE FREQUENCY COUNTER
Standards of time and frequency (time and frequency being essentially the same
standard) are unique in that they may be transmitted by radio from one location
to another without the actual movement of the standard. Therefore, it is possible
to have traceability to the primary standard without difficulty. Additionally, the
primary standard is related to the structure of matter, and primary standards
can be easily duplicated throughout the world to allow high-accuracy measure-
ments anywhere. Because of the relative ease with which frequency and time
can be measured to great accuracies, electronics systems have developed around
this capability. Consider, as an example, the tolerance expected of radio-trans-
mission equipment. The spectrum required by a voice-modulated two-way radio
transmitter using frequency modulation is on the order of 1 5 kHz. This implies
that if the frequency of the transmitter carrier could be held to absolute precision
a communications channel could be assigned every 15 kHz and make the most
efficient use of the radio spectrum. Because accurate measurement techniques
are available and standards can be made available, the communications channels
are assigned every 20 kHz in the UHF (450 MHz) band. This requires a carrier
frequency accuracy and stability of only 5 kHz, which is approximately 0.001
per cent, which is easily achieved with modern frequency control and measure-
ment techniques.
Although relatively stable frequency standards have been available for
many years, precise frequency measurement has not always been an easy mea-
surement task. Early frequency measurement required precision standards, fre-
325

326 Frequency Counters and Time-Interval Measurements Chap. 10
quency comparators and interpolation oscillators, as well as a lot of operator
skill. This came to an abrupt end with the introduction of digital logic and the
development of the frequency counter.
Figure 10-1 shows the block diagram of a simple frequency counter. Al-
Display
Memory
Strobe
Input
Input
Signal Processor Decade
1
—
Counters
Reset
1
Time Base 1
Figure 10-1 Basic block diagram of a frequency counter.
though referred to as "simple," this basic counter is capable of great precision
if the parts are constructed properly. The frequency counter operates on the
principle of gating the input frequency into the counter for a predetermined
time. As an example, if an unknown frequency were gated into the counter for
an exact 1 second (s), the number of counts allowed into the counter would be
precisely the frequency of the input. The term gated stems from the fact that
an AND or an OR gate is used to allow the unknown input into the counter
to be accumulated. Figure 10-2 shows the waveforms associated with this action.
This example shows an AND gate; however, an OR gate could be used in a
similar circuit. A positive-going pulse having a period of exactly 1 s is applied
to one input of the AND gate. As long as the 1-s pulse is a logic 1, the output
of the AND gate is the same as the unknown input. When the 1-s pulse returns
to logic 0, the output of the AND gate is zero. Thus, exactly 1 s of unknown
input pulses is allowed at the output of the AND gate. It is necessary to count
these pulses and display the result.
^ Jinjijijiririr^
Gate |~ |
output _TLnjijirTJirir^^
(Figure 10-2 Waveforms associated with the gating function of a frequency counter.

Sec. 10-1 Simple Frequency Counter 327
If the gate is open for exactly 1 s, the count accumulated is equal to the
average frequency of the unknown input in hertz (Hz). If, as an example, the
gate was open for 10 s, the accumulated count would be the average frequency
in 0.1 Hz. Likewise, if the gate were open for 0.1 s, the count would be the
average frequency in tens of hertz. When a frequency counter has more than
one gate time interval available, the decimal point of the display is switched
with the gate time selector switch to correct the frequency display.
10-1.1 Display Counters
The actual counting circuits are, in practice, constructed from integrated
circuit counters, but it is constructive to understand the internal operation of a
digital counter.
The heart of a frequency counter is the decade counter, which can be
constructed from four flip-flops and an AND gate, as shown in Fig. 10-3. This
Outputs
Input
J Q
c
K
Figure 10-3 Ripple binary coded decimal counter.
form of decade counter is called a ripple counter owing to the fact that the
clock of one flip-flop is derived from the output of the previous flip-flop, which
requires that the clock pulses ripple through the counter from the first stage to
the last stage. The last stage, however, derives its clock from the first stage,
which reduces the propagation delay to a certain degree.
A superior method of constructing a counter is to use a synchronous
counter. This circuit, shown in Fig. 10-4, requires that all the flip-flop clocks
be connected together, which greatly reduces the propagation delay and allows
higher counting speeds.
The output of the decade counter follows the sequence shown in Fig.
10-5 and is called binary coded decimal (BCD), which implies that the normal
binary code is used except that each digit is defined only for values between 0
and 9. As an example, the decimal number 138 is 0001 0111 1000 in BCD.
Each BCD counter allows one decade of counting and thus the BCD
counters must be cascaded. For example, three cascaded BCD counters are

Clock Counter State
u c Q
D A
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
IO 0 0 0 0
Figure 10-5 Binary coded decimal count-
0 ing sequence.
required to count from 0 to 999. There are two methods of cascading BCD
counters, ripple cascading and synchronous. Ripple cascading is usually reserved
for ripple counters and, unfortunately, makes the slow ripple counter even slower.
With the exception of low-frequency counters, the ripple counter is not used in
serious frequency-measuring equipment. The ripple connection requires the last
output of the least significant counter to drive the clock input of the next more
significant counter, as shown in Fig. 10-6. The clock input to the next stage
must respond to the negative edge of the clock as the last bit, which has a binary
weight of 8, goes low at the transition from 9 to 0.
A B C D
Clock
A B C D
Clock
A B C D
Clock
Figure 10-6 Cascading ripple counters.
The synchronous counter has a terminal count or carry output for the
purpose of cascading counters, as shown in Fig. 10-7. This output goes to a
logic 1 after the clock that changes the state of the counter to 9. This output
is used to enable the following counter to be incremented on the next clock
pulse. This insures that the state of the next counter is coincident with the clock
and preserves the synchronous counter operation when the counters are cascaded.
When more than two counters are cascaded, the requirement for any one counter
to change state is that all of the less significant counters must be at 9. Some
integrated-circuit counters have internal cascading logic that propagates the
PE A B C D TC
Clock
PE A B C D ye
Clock
p E A B C D TC
Clock
Figure 10-7 Cascaded synchronous counters.

330 Frequency Counters and Time- Interval Measurements Chap. 10
"nine" state from the least significant digit through all the intervening counters
to the most significant digit. When there is a large number of cascaded counters,
the delay can limit the count frequency of the counter. Therefore, other tech-
niques called look ahead or carry forward are used to reduce the amount of
propagation delay.
The BCD information available at the output of the counter must be
converted to some form of visible display. The conversion depends on the type
of display desired. For example, conversion from BCD to the very popular seven-
segment display requires a single, inexpensive integrated circuit. Figure 10-8
shows a 4-bit counter including the seven-segment code conversion.
Counter
7490
Decoder/Driver
7447 Display
Clock a
A
b
B
c
d
C
D
e
f
g
Figure 10-8 Block diagram of a decade counter interfaced with a seven-segment
display.
It is desirable in a frequency counter to display the count continuously.
Since the counter is reset to zero and allowed to count during the gate period,
during this time the output of the counter is constantly changing. The output
of the counter cannot be displayed during this period as it would appear as a
meaningless blur. Therefore, the count at the end of the measurement period is
stored in a simple memory and displayed during the next counting period, after
which the next count is stored in the memory and displayed. This memory is
required to store only 4 bits, the entire BCD word, for each decade of the counter
and is typically a simple 4-bit latch, which consists of four D-type flip-flops all
clocked together, with each flip-flop storing 1 bit of data.
Digital logic usually cannot supply the required current for driving a
display. Even those displays that require minimal amounts of current, such as
liquid crystals, require special signals, which are not readily available from the
decoder output. Therefore, a display driver is included between the decade
counter and the displays.
For counters requiring a large number of digits, typically 10 or more, there
are various techniques to reduce the required hardware, one of which is shown
in Fig. 10-9. This technique is called display multiplexing and reduces the number
of drivers and decoders required to implement large counters. In this example
a common decoder and driver are shared between all the display digits. A
multiplexer selects the BCD data from one of the latches and routes these data
to the input of the seven-segment decoder. The decoded seven-segment infor-
mation is applied to the proper display. The entire process is driven by an

Scan
Counter
Scan
Oscillator
Digit Driver
Clock
Displays
Figure 10-9 Block diagram of a multiplexed display used in a frequency counter.
oscillator and a counter called the scan oscillator and counter. When this process
is done at a rapid rate, the display appears constant to the eye. It would seem
that the inclusion of the multiplexer, scan oscillator, and multiplexed display
drivers is hardly worth the aggravation to save a few simple decoders. However,
this technique has significant advantages when the frequency counter circuits
are integrated into a single silicon chip.
Consider, as an example, a 10-digit frequency counter. This scale of fre-
quency counter could be integrated onto a single silicon chip except that 70
outputs would be required for the readouts alone if they are of the seven-segment

type. Add to this the power and ground, a time-base input, and other inputs
required for the frequency counter and the net result is 80 or more pins, which
does not allow for inexpensive packaging. The readout output could be multi-
plexed with seven outputs for the segments and a 4-bit binary output for selecting
each digit, which results in only 1 1 output pins for the display interface. Adding
the other required pins results in a package size that can be handled with
conventional packaging technology.
(10-1.2 Time Base
The sequence of events within the frequency counter is controlled by the
time base, which must provide the timing for the following events: resetting the
counter, opening the count gate, closing the count gate, and storing the counted
frequency in the latch. The resetting of the counter and storing of the count are
not critical events as long as they occur before and after the gate period,
respectively. The opening and closing of the count gate, on the other hand,
determine the accuracy of the frequency counter and are very critical in its
timing.
Since the accuracy of the frequency counter depends directly on the ac-
curacy of the time-base signals, the time base is driven from an accurate crystal-
controlled oscillator. This element of the time base is typically a temperature-
compensated crystal oscillator operating at several megahertz. A crystal oven
could be used to supply a similar accuracy, except that the oven requires a
relatively long period after the initial application of power, up to 24 hours, to
stabilize. The temperature-compensated oscillator does not require the appli-
cation of power to provide the correct frequency and is available for use im-
mediately after power-on. Figure 10-10 shows a simplified diagram of a
Varactor
Diode
RFC
i
Oscillator
—RF Oul
o
Temperature
Sensor
(Thermistor)
Figure 10-10 Block diagram of a temperature-compensated crystal oscillator.
Correction
Network
temperature-compensated cry stal oscillator. A conventional crystal oscillator is
used as the basic building block of the compensated oscillator, except that a
varactor diode is placed across the crystal. The varactor allows the frequency
of the oscillator to be changed by minute amounts. The crystal oscillator fre-
quency error is characterized over the desired operating temperature, and the
error characteristic is stored in the correction network. This can either be a

digital storage technique or an analog circuit with nonlinear characteristics. The
ambient temperature is fed to the correction network, which adjusts the oscillator
frequency by varying the varactor voltage as a function of temperature.
Aside from the temperature variation of frequency of a crystal oscillator,
quartz crystals tend to age and change frequency over a period of time. This
undesired frequency change can be reduced by special crystal fabrication tech-
niques, but it still can be as high as 5 X 10
" 7
parts per year. This must be
compensated for by periodic recalibration.
Many temperature-compensated crystal oscillators have the capability of
being electronically adjusted. If the frequency counter has a standard frequency
output that can be compared to one of the available broadcast frequency stand-
ards, the frequency of the time-base oscillator in a frequency counter can be set
to within 1 part in 10
9
.
Three outputs are required from the time base: a reset pulse, the gating
pulse, and a strobe pulse, in that order. Figure 10-11 shows a simple circuit for
generating the three required pulses without overlap. The crystal oscillator is
divided by powers of ten, as the period of the frequency of the crystal is much
shorter than the desired gate time. The final digital divider is a 4-bit binary
counter that has 16 states. The zero state of the counter is decoded to provide
the reset pulse for the frequency counter. The 2 state is decoded to provide the
gate open pulse. The 1 state was not used so as to provide a delay after the
4-bit
Binary
Counter
10 Hz
100Hz-
1 Hz
1 sec
0. 1 sec
0 .01 sec
°pen Gate
—n
L
Reset
-_J~"|__ Close gate
|_J~~ Store
Figure 10-11 Logic diagram of a time base for a frequency counter.

reset pulse to allow the counters to be fully recovered from the reset. The gate
remains open for exactly 10 clock pulses, and thus the 12 state of the counter
is decoded to provide the gate close pulse. The 13 state of the counter is not
decoded so as to provide a delay period before the counter is stored in the latch
during the 14 state. The 15 state is not decoded and provides the necessary
nonoverlap between the store and reset pulses, which occur immediately after
the 15 state of the counter.
It is important that the propagation delay from the input clock to the
edges of the open and close pulses be the same for each so that the gate is
exactly equal to the correct number of clock pulses. This requires fast logic and
careful design.
Most frequency counters have several available gate time intervals that
can be selected by a switch. As shown in Fig. 10-11, the input of the binary
counter can be selected from a choice of 1 Hz, 10 Hz, 100 Hz, and 1 kHz.
These frequencies provide gate times of 10, 1, 0.1, and 0.01 s, respectively.
10-1.3 Input Signal Processing
The unknown frequency input is not guaranteed to be of the correct logic
level to drive the frequency counter, and a processing circuit is required. Typ-
ically, this is an amplifier to increase the signal level, an attenuator to adjust
for variations in input amplitudes, and a comparator so that the slow risetime
of the input waveforms can be reduced to provide reliable operation of the
internal logic circuits. A schematic diagram of a typical frequency counter input
circuit is shown in Fig. 10-12. Amplitudes of a few millivolts can be used to
trigger the frequency counter using this circuit.
Comparator
—WA
Amplifier
I
VWV
To Counter
Input
©
H
Figure 10-12 Input circuits for a simple frequency counter.

10-1.4 Period Measurement .
* ^^ '
'
If two input signals were substituted for the open and close gate signals,
and one of the internal clock signals, that is, one of the available frequencies
that are powers of 10 Hz, is supplied to the count gate, the time interval between
the two input signals could be measured. The arrangement of this period mea-
suring is shown in Fig. 10-13. The input signals must be processed in the same
fashion as the count input signal, and the same circuit can be used for period
measurement. A second identical circuit will have to be supplied for the period
measurement.
Signal A
Signal B-
Input
Signal
Processor
IS
Start
1
—
Input
Signal
Processor
1
IS Stop
Counter
Resolution
1 ms
o
00fxs
1 mHz
lO/zs
I00 kHz 10 kHz I kHz
From Time Base
Figure 10-13 Circuit arrangement for making period measurements.
Another period measurement can be made using a single input. This would
be useful for determining the period of pulses and other signals. In this mode
of operation, the gating signal is the input, and the internal frequency clocks
are used as timing sources. To measure the period of a pulse waveform, it is
necessary to open the count gate at the rising edge of the pulse and to close the
gate at the falling edge of the pulse. In the case of a negative-going pulse, this
procedure would be reversed, that is, opening the gate on the negative edge and
closing the gate at the positive edge. If the risetimes and falltimes of the input
pulse are short, compared to the resolution of the period measurement, the
actual trigger point is not critical. A sophisticated frequency counter will have
independent control over the voltage level of both the rising and falling edges,
as shown in Fig. 10-14. Although this results in the most flexible and accurate
measurements, this type of frequency counter requires operator skill and a
method of viewing the trigger points, such as an oscilloscope. Because most
period measurements involve pulses with fast rise- and falltimes, a simple al-

Open
Frequency Counters and Time-Interval Measurements Chap. 10
Vref
SI
Figure 10-14 Frequency counter input circuits showing the ability to set rising and
falling edges individually.
I
WW-
+ 5 V
B _L
©
Out
5 V
© 0 V r r
+ 2.5 V
—
s
2.5 V
5 V
0 V
Figure 10-15 Zero-crossing detector for a frequency counter and the associated
waveforms.

Sec. 10-2 Measurement Errors 337
ternative is to ac couple the input signal and open and close the count gate at
the zero crossings of the ac-coupled signal. Figure 10-15 shows a typical pulse
waveform input and the resulting trigger points after ac coupling.
One very important period measurement is the period measurement to
determine frequency. This measurement is not made from rising edge to falling
edge but from a point in an input cycle to the same point in the next cycle,
which is the period of the input signal. In this case, the gate is to be opened at
a point of the input waveform and closed at precisely the same point in the next
cycle. This is accomplished in the following fashion. The input signal is ac
coupled, and a zero crossing detector triggers a flip-flop. The following zero
crossing is of the opposite slope and does not trigger the flip-flop. The next zero
crossing, however, occurs after a time period equal to the period of the input
waveform and toggles the flip-flop, which provides a gate time exactly equal to
the period of the input waveform, as shown in Fig. 10-16.
J Q
c
K
To frequency
Counter
Figure 10-16 Input circuit configuration for measuring the period of a waveform.
The typical laboratory counter, such as that shown in Fig. 10-17, has both
input period measurement and independent control of risetime and falltime
triggering selectable from a front-panel switch.
10-2 MEASUREMENT ERRORS
10-2.1 Gating Error
Frequency and time measurements made by an electronic counter are
subject to several inaccuracies inherent in the instrument itself. One very common
instrumental error is the gating error, which occurs whenever frequency and
period measurements are made. For frequency measurement the main gate is
opened and closed by the oscillator output pulse. This allows the input signal
to pass through the gate and be counted by the decade counters. The gating
pulse is not synchronized with the input signal; they are, in fact, two totally
unrelated signals.

Figure 10-17 Microprocessor-controlled computing counter (courtesy of Racal-Dana
Instruments, Inc.).
In Fig. 10-18 the gating interval is indicated by waveform (c). Waveforms
(a) and (b) represent the input signal in different phase relationships with respect
to the gating signal. Clearly, in one case, six pulses will be counted; in the other
case, only five pulses are allowed to pass through the gate. We have therefore
a ± 1 count ambiguity in the measurement. In measuring low frequencies, the
gating error may have an appreciable effect on the results. Take, for example,
the case where a frequency of 10 Hz is to be measured and the gating time
equals 1 s (a reasonable assumption). The decade counters would indicate a
count of 10 ± 1 count, an inaccuracy of 10 per cent. Period measurements are
therefore to be preferred over frequency measurements at the lower frequencies.
The dividing line between frequency and period measurements may be
determined as follows: Let
fc
= crystal (or clock) frequency of the instrument
fx
= frequency of the unknown input signal
w JuuuLrui_rLJo_n_
« _n_JtTLJuiJuua_n_
w / N
r« Gate Open »•{
Figure 10-18 Gating error.

Sec. 10-2 Measurement Errors 339
In a period measurement the number of pulses counted equals
f,
NP
= J
i (10-1)
In a frequency measurement with a 1-s gate time the number of pulses counted
is
Nf
= fx (10-2)
The crossover frequency (f0) at which Np
= Nf is
7 = L or fQ
= yjf
c (10-3)
Jo
Signals with a frequency lower than f0 should therefore be measured in the
"period" mode; signals of frequencies above f0 should be measured in the "fre-
quency" mode in order to minimize the effect of the ± 1 count gating error.
The accuracy degradation at f0 caused by the ± 1 count gating error is 100/
yjf
c
per cent.
10-2.2 Time-base Error
Inaccuracies in the time base also cause errors in the measurement. In
frequency measurements the time base determines the opening and closing of
the signal gate, and it provides the pulses to be counted. Time-base errors consist
of oscillator calibration errors, short-term crystal stability errors, and long-term
crystal stability errors.
Several methods of crystal calibration are in common use. One of the
simplest calibration techniques is to zero-beat the crystal oscillator against the
standard frequency transmitted by a standards radio station, such as WWV.
This method gives reliable results with accuracy on the order of 1 part in 10
6
,
which corresponds to 1 cycle of a 1-MHz crystal oscillator. If the zero-beating
is done with visual (rather than audible) means, for example, by using an
oscilloscope, the calibration accuracy can usually be improved to 1 part in 10
7
.
Several very low frequency (VLF) radio stations cover the North American
continent with precise signals in the 16-20-kHz range. Low-frequency receivers
are available with automatic servo-controlled tuning that can be slaved to the
signal of one of these stations. The error between the local crystal oscillator and
the incoming signal can then be recorded on a strip-chart recorder. A simplified
diagram of this procedure is given in Fig. 10-19. Improved calibration accuracy
can be obtained by using VLF stations rather than HF stations because the
transmission paths for very low frequencies is shorter than for high-frequency
transmissions.
Short-term crystal stability errors are caused by momentary frequency
variations due to voltage transients, shock and vibration, cycling of the crystal
oven, electrical interference, etc. These errors can be minimized by taking fre-

Receiver
Frequency
Multiplier
Phase or
Time Error
Phase
Detector
Local
Frequency
Source
To Recorder
OServomotor
or Manual
Adjustment
Figure 10-19 Calibration of a local frequency source.
quency measurements over long gate times (10 s to 100 s) and multiple-period-
average measurements. A reasonable figure for short-term stability of a standard
crystal-oven combination is on the order of 1 or 2 parts in 10
7
.
Long-term stability errors are the more subtle contributors to the inaccuracy
of a frequency or time measurement. Long-term stability is a function of aging
and deterioration of the crystal. As the crystal is temperature-cycled and kept
in continuous oscillation, internal stresses induced during manufacture are re-
lieved, and minute particles adhering to the surface are shed reducing its thick-
ness. Generally, these phenomena will cause an increase in the oscillator
frequency.
A typical curve of frequency change versus time is shown in Fig. 10-20.
The initial rate of change of crystal frequency may be on the order of 1 part in
10
6
per day. This rate will decrease, provided that the crystal is maintained at
its operating temperature, normally about 50° to 60°C, with ultimate stabilities
of 1 part in 10
9
. If, however, the instrument containing the crystal is unplugged
from the power source for a period of time sufficient to allow the crystal to cool
appreciably, a new slope of aging will ensue when the instrument is put back
into operation. It is possible that the actual frequency of oscillation after cool
Initial Slope
Time
(Weeks)
Figure 10-20 Frequency change versus time for an oven-controlled crystal.

Sec. 10-3 Extending the Frequency Range of the Counter 341
off will vary by several cycles and that the original frequency will not again be
reached unless calibration is done.
To show the effect of long-term stability on the absolute accuracy of the
measurement, assume that the oscillator was calibrated to within 1 part in 10
9
and that a long-term stability of 1 part in 10
8
per day was reached. Assume
further that calibration was done 60 days ago. The guaranteed accuracy at this
time is then 1 X 1(T
9
+ 60 X 10~ 8
= 6.01 X 10~ 7
, or 6 parts in 10
7
. It can
be seen therefore that maximum absolute accuracy can be achieved only if an
exact calibration is performed a relatively short time before the measurement is
taken.
10-2.3 Trigger Level Error (j6W^n
In time-interval and period measurements the signal gate is opened and
closed by the input signal. The accuracy with which the gate is opened and
closed is a function of the trigger level error. In the usual application the input
signal is amplified and shaped, and then it is applied to a Schmitt trigger circuit
that supplies the gate with its control pulses. Usually the input signal contains
a certain amount of unwanted components or noise, which is amplified along
with the signal. The time at which triggering of the Schmitt circuit occurs is a
function of the input signal amplification and of its signal-to-noise ratio. In
general, we can say that trigger time errors are reduced with large signal am-
plitudes and fast risetimes.
Maximum accuracy can be obtained if the following suggestions are fol-
lowed:
(a) The effect of the one-count gating error can be minimized by making
frequency measurements above y[f
c and period measurements below
yjf
ci where f is the clock frequency of the counter.
(b) Since long-term stability has a cumulative effect, the accuracy of mea-
surement is mostly a function of the time since the last calibration
against a primary or secondary standard.
(c) The accuracy of time measurements is greatly affected by the slope of
the incoming signal controlling the signal gate. Large signal amplitude
and fast risetime assure maximum accuracy.
1 0-3 EXTENDING THE FREQUENCY RANGE OF THE
COUNTER
Using the fastest logic and the most sophisticated carry circuits, the simple
frequency counter shown in Fig. 10-1 is limited to about 100-MHz counting
speed. To increase the frequency range of the counter, several techniques can
be used. One technique is to use a prescaler as shown in Fig. 10-21. A prescaler

342 p Frequency Counters and Time- Interval Measurements Chap. 10
^, 1MHz-IOMHz
41
IO-IOO MHz > -10
Frequency
Counter
Figure 10-21 Using a prescaler to extend the range of a frequency counter.
is a fast digital counter that, typically, divides the input frequency by 10. The
prescaler does not drive a display, is not gated, nor are the output data strobed
into the storage latch. Therefore, the propagation delay of the prescaler is not
important as long as the prescaler can operate at the desired frequency. If a
divide-by- 10 prescaler were used ahead of a 10-MHz counter, the counter fre-
quency would be increased by a factor of 10 and the system would be capable
of counting to 100 MHz. Prescalers are available for frequencies up to 1 GHz
with divisions of 10 or 100, which can extend the range of the example 10-MHz
counter to 1 GHz.
There is a penalty to be paid for the use of the prescaler. The resolution
of the frequency counter is reduced by the same factor as the prescaler. As an
example, if a 10-MHz counter were used with a prescaler, the frequency displayed
would be multiplied by 10, all the digits including the least significant. This
implies that if the counter had a resolution of 1 Hz, which is the value of the
last digit, when multiplied by 10 the resolution would be reduced to 10 Hz.
This can be overcome by simply using a longer time base and restoring the
resolution. This can become a practical problem if the prescaler has a large
division and very accurate frequency measurements are to be made. For example,
if the divide-by- 100 prescaler were used to extend the frequency range of the
10-MHz counter to 1 GHz, and a measurement of 1-Hz resolution were desired,
the gate time would be 100 s, which could be a significant problem. Typically,
frequency measurements with resolution of better than 1 kHz at 1 Ghz are rare.
The prescaler, as effective as it can be, is limited to frequencies below
about 1.5 GHz with the current state of technology. For making frequency
counter measurements at higher frequencies, heterodyning techniques are used.
Figure 10-22 shows a heterodyning converter for a frequency counter. This
Input Signal
100 MHz
Harmonic
Generator
Tuned
Cavity
Low -pass
Filter
To
Counter

Figure 10-22 Manually tuned heterodyning frequency converter for extending the
frequency range of frequency counters.

Sec. 10-3 Extending the Frequency Range of the Counter 343
converter is used with a 50-MHz counter, which requires that the converter
reduce the input frequency to 50 MHz or less, which it does with mixing
frequencies every 100 MHz. Because both the sum and the differences are used,
the converter frequency never exceeds 50 MHz. A 100-MHz source, which is
derived from the frequency counter's time base, feeds a harmonic generator
using a step recovery diode. The step recovery diode has a unique reverse recovery
characteristic in that it stops conducting very abruptly, which generates har-
monics of the driving waveform to several gigahertz. The harmonic content of
the diode generator extends well into the 5-GHz region. Harmonics from the
fundamental at 100 MHz to 5 GHz are selected by a tuned cavity that tunes
one of the harmonics. It is necessary to know which of the 50 harmonics is
being tuned, and a calibrated dial is provided as a tuning meter to peak the
desired signal. The setting of the harmonic tuner dial does not affect the accuracy
of the measurement unless the incorrect harmonic is tuned. The 50 harmonics
represent a 2 per cent resolution, which can be easily achieved with a mechanical
assembly.
The selected harmonic is mixed with the input and the difference is filtered,
amplified, and fed to the counter. Because there is a harmonic available every
100 MHz, the input signal is never more than 50 MHz from one of the harmonics.
To select the correct harmonic, the input frequency must be known to within
10 MHz or so, which can be done with another measurement technique such
as a wavemeter or spectrum analyzer.
Since either the sum or difference between the selected harmonic and the
input signal may be counted, the operator is required to make the necessary
calculations to determine the actual frequency. This involves adding or sub-
tracting, depending on whether the sum or difference is counted, the harmonic
frequency that is read from the harmonic tuner dial.
Modern frequency counters are capable of tuning the harmonic and making
the necessary calculation automatically. Figure 10-23 shows a block diagram of
an automatic heterodyning unit for converting frequencies up to 4 GHz to
extend the range of a 500-MHz counter. A 100-MHz signal from the frequency
counter is multiplied using a bipolar transistor frequency multiplier to 500 MHz.
This signal is amplified and used to drive a step recovery diode frequency
multiplier. The output of the step recovery diode multiplier is filtered to recover
signals at 1,000 MHz and 1.5, 2, 2.5, 3.0, and 3.5 GHz.
The input signal is fed to an amplifier, which feeds the mixer and a level
detector. When the presence of an input signal is detected with the level detector,
the six possible mixing frequencies, that is, 1, 1.5, 2, 2.5, 3, and 3.5 GHz, are
electronically sequenced in ascending order, while the presence of an output
signal below 500 MHz is determined by a level detector at the mixer output.
When it has been determined that a difference exists below 500 MHz, the selected
mixing frequency is transmitted to the frequency counter and added to the
counted frequency. Because there is a mixing frequency every 500 MHz, and
these frequencies are sequenced from the lowest to the highest, the first detection

344 Frequency Counters and Time-Interval Measurements Chap. 10,
1 GHz
Harmonic
Generator
r+- x5
IOO MHz
from
Frequency
Counter
1.5 GHz
2.0 GHz
a
Switch
2.5 GHz
3.0 GHz
3.5 GHz
Input
500 MHz 4 GHz
Level
Detector
Figure 10-23 Automatic heterodyning unit for extending the frequency range of
frequency counters to 4 GHz.
of an output from the mixer less than 500 MHz represents the difference between
the input frequency and the selected mixing frequency. It is possible to obtain
an output using the next-higher mixing frequency, but this is avoided by selecting
the first mixing frequency to supply an output below 500 MHz.
It is informative to calculate the effects on the accuracy of both the pre-
scaler and the heterodyning methods of frequency extension.
For the case of the prescaler, assuming that the prescaler does not miss
counts, and this is generally true, the output frequency is simply the input
frequency divided by N, the prescaler ratio. The displayed frequency is the input
frequency to the counter times the gate time, which is
displayed frequency
fin
N
(10-4)
Because N is a constant, the accuracy of the display is simply a function of t,
the gate time. Thus, the accuracy of the counter with a prescaler is exactly the
same as the accuracy of the counter without a prescaler.
Consider the case when using the heterodyning frequency converter where
the mixing signal is derived from the same clock as is used to derive the time
base within the counter. The gate time is an integer number of cycles of the
time-base clock, or
gate time = ? (10-5)
Jc

Sec. 10-4 Automatic and Computing Counters 345
where Q is the division of the time base and fc is the time-base clock frequency.
The mixing frequency in the converter is derived from the same source, and the
output frequency of the converter is
A = A' ± Nfc (10-6)
wherefm is the frequency into the counter, fj is the frequency into the converter,
and N is the multiplication between the internal time-base clock and the het-
erodyning signal.
The displayed frequency of the counter is the input frequency of the counter
times the gate time, which is
displayed frequency = fm
(|)
= *t£. + QN (10-7)
The relationship between the actual input frequency and the displayed frequency
is a function of fc only, as the second term of relationship (10-7), QN, is a
constant.
Therefore, neither the heterodyning nor the prescaling method of increasing
the frequency range of a counter affects the accuracy.
10-4 AUTOMATIC AND COMPUTING COUNTERS
The frequency counter, being an intensely digital machine, is an excellent can-
didate for automating and computerizing. One excellent measurement that can
be handled by a calculating counter is the measurement of low frequencies with
accuracy. One significant problem with the frequency counter is the measurement
of low frequencies. If a signal of less than 1 Hz was to be measured with a
resolution of 0.01 Hz, the time required would be 100 s if the conventional gate-
controlled counter were used. An alternative measurement technique is to mea-
sure the period of the input waveform and calculate the frequency from the
relationship:
frequency = —
—- (10-8)
period
The time required to display the frequency is the period of the unknown
input plus the computation time. For the example of a frequency on the order
of 1 Hz, the period is 1 s, while the computation time is on the order of 1 ms
or less. Essentially, the frequency of any waveform can be measured within the
time of one period plus a small increase for the computation. However, the
determination of frequency from a single period measurement has a statistical
probability of error that is very great. A second frequency calculation made
from a second period measurement would improve the probability of error, while
a third calculation would further improve the error. The calculating frequency

counter would continue to make frequency calculations from the period of the
input as long as the input were present and display the arithmetic mean of the
calculations.
Not only are low-frequency measurements improved from the calculating
ability of a frequency counter; the measurement of pulsed carriers can be im-
proved by the calculating counter. It is often necessary to determine the frequency
of bursts of energy that do not last for long periods of time. As an example,
consider a 1-jlls burst of a 1-GHz carrier. To measure the frequency of the burst,
only 1,000 complete cycles are available that can be counted. The frequency
counter has an ambiguity of + or — one count which in this case represents
an error of 1 part in 1,000, or 0.1 per cent. If the accuracy of the measurement
is to be better than this, more than one burst has to be counted and ultimately
used for the frequency calculation. The calculating frequency counter can make
several measurements, average the result of each measurement, and display a
statistically determined frequency.
In the section on frequency counter accuracy, it was discussed that there
is a point where measuring the period of an input with a certain clock frequency
produces improved accuracy over the measurement of the input frequency for
a fixed gate time. A block diagram of an automated frequency counter with the
capability of automatically making period or input frequency measurement and
then performing the necessary mathematics to display the correct frequency is
shown in Fig. 10-24. In this counter, rather than a conventional gate, there are
two gated counters. One counter is used to accumulate the input frequency,
while the second counter accumulates a precision clock. Both counters are gated
Input
Matched
Gates
Gate
Time
Base
Precision
Clock
>-
A
Counter
> B
Counter
Computer
van
Period/Frequency
Display
Figure 10-24 Precision computing counter using dual counters.

Chap. 10 Problems 347
simultaneously, such that the number of input cycles has been accumulated in
counter A while a precision clock, or the elapsed time is accumulated in counter
B. The frequency of the input can be determined from the following relationship:
count in A
input frequency = :
(10-9)
count in B
J
The opening and closing of the gate are controlled from either the input
signal or the internal precision clock. Essentially, if the gate is controlled by
the internal clock a conventional frequency measurement will be made, and if
the gate is controlled by the input signal, a period measurement is being made.
As previously explained, the frequency where the accuracy changes from a period
measurement to a frequency measurement is (fc )
l/2
, wherefc is the clock frequency
from which the time base is derived and the clock used for the period mea-
surement. In this example the precision clock used for the period measurement
is 500 MHz, which places the changeover point at 22 MHz. From the setting
of the input switches, which can select the number of significant digits and the
resolution, the automatic frequency counter will select the method of measure-
ment.
REFERENCES
1. Prensky, Sol D., and Castellucis, Richard L., Electronic Instrumentation, 3rd ed.
Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1982.
2. Tocci, Ronald J., Digital Systems: Principles and Applications, chaps. 4, 5, and 7.
Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1980.
PROBLEMS
1. A frequency counter capable of measuring an unknown frequency to within 1 Hz
by measuring frequency rather than period would require what minimum gate time?
(2} To what accuracy can a frequency counter determine an unknown frequency of 450
kHz, using a 1-s time base and a time-base accuracy of 0.01 per cent?
3. How many displays (total decades) should a frequency counter have if its accuracy
and resolution are to be 0.001 per cent?
(5plf the internal time base of a frequency counter is 10.000 MHz, what frequency
range is best measured by a period measurement, and what frequency range is best
measured by a conventional frequency measurement?
5. What effects on accuracy, resolution, etc., does the addition of a fixed modulus
prescaler have on a frequency counter?
^pWhat method can be used to increase the frequency range of a frequency counter?
How can this be achieved without degrading the accuracy of the counter?r
7. What problems are associated with the measurement of pulsed signals? ^4

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