1. Avinash Muchala
Phone: +91-9951791222 E-mail: avinashmuchala@gmail.com
Objective:
To obtain challenging position that enables me to fully utilize my skills, potential and abilities in an organization that
offers professional growth while being highly competent, innovative and flexible.
Education:
Master of Technology in VLSI May 2015
Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad Aggregate: 82%
Bachelor of Technology in Electronics and Communication Engineering May 2012
JNTU Anantapur, A.P Aggregate:73%
Intermediate Public Examination May 2008
Nalanda Junior College, A.P Aggregate:93%
Secondary School Examination May 2006
Sarada English Medium High School, A.P Aggregate:83%
Technical Skills:
HDVL -System Verilog.
HDL -Verilog.
Programming Languages -C, C++, Core Java.
Methodologies -Open Verification Methodology(OVM), Universal Verification Methodology (UVM)
Tools -Questasim.
Scripting -Perl.
Experience Details:
In total of 4 months of experience. Currently working as Intern in DeepThought Technologies, Hyderabad since Feb
2016.
Project Details:
1) Verification of Simple Memory using Genetic Algorithm in SystemVerilog
Tools used: Questasim
Description: Genetic Algorithm is an evolutionary algorithm that generates outputs based on previous outputs.
Genetic algorithm performs mainly three operations. They are selection, crossover, and mutation. Initially selection
process randomly selects some test patterns and crossover exchanges a part of data between different test patterns.
Mutation process inverts one of the bit of test pattern. By using transfer function we can eliminate some of test
patterns and the remaining are allowed to produce next generation test patterns. This process goes on until we get the
optimized results.
2) Verificationof GMII Interface in SystemVerilog (OVM)
Tools used: Questasim
Description: The GMII provides 8- bit wide data path between 100Mbps PHY and MAC sub-layer. It consists of a
stimulus generator that generates packets. Driver and Monitor which act as transactors for the DUT and a Checker
which compares the actual and expected transactions.
3)Verification of FIFO in UVM
Tools used: Questasim
Description: FIFO is designed with 8-bit wide and 16-bit depth by using read enable and write enable as control
signals.The output of FIFO may be either in empty, partial or full state based on control signals.
4) Design of AXI4-Lite Interface
Tools used: QuestaSim
Description: AXI (Advanced Extensible Interface) is the third generation of AMBA interface, targeted at high
performance, high clock frequency system designs. It has separate address/control and data phases which support
unaligned data transfers using byte strobes and burst based transactions with only start address issued.

2. Scholastic Achievements:
 Written a blog for design : http://designusingverilog.blogspot.in
Personal Details:
Name
Father’s Name
Gender
Marital Status
Nationality
Date of Birth
Hobbies
Languages Known
Permanent Address
: Avinash muchala
: Malakonda reddy
: Male
: Single
: Indian
: 12th
March, 1991
: Listening to Music, Playing chess
: Telugu, English, Hindi
: 8/a, Avanthinagar thota,
P R nagar, Erragadda,
Hyderabad- 500018