Tocci ch 3 5 boolean algebra, logic gates, combinational circuits, f fs, - related circuits

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Chapter 3
Logic Gates and Boolean Algebra
Mathematics of the Logic

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De Morgan’s Theorem

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De Morgan’s Theorem

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De Morgan’s Theorem

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Sum of Products and Products of Sums
Implications of De Morgan’s Theorem

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Sum of Products and Products of Sums
Implications of De Morgan’s Theorem

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Implications of De Morgan’s Theorem

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Universality of NAND Gates and NOR Gates

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Universality of NAND Gates and NOR Gates

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Universality of NAND Gates and NOR Gates

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Alternate Logic Gate representations

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Realizing the AND Function with NOR Gates
f A B 
f f
 A B 
 A B 

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Logic Symbol Interpretation
Active High
Outputs
Active High
Inputs
Active Low
Outputs
Active Low
Inputs

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NOR Gates and NAND Gates

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Example: Realize the following function in sum-of-products form, using only
two-input NAND gates
Solution

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Chapter 4
Combinational Logic Circuits

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Sum of Products and Product of Sums
Sum of Products:
F= x'yz + xy'z + xyz' + xyz
Product of Sums:
F= (x+y+z) • (x+y+z') • (x+y'+z) • (x'+y+z)
Simplification
:

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Parity Generator and Checker

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Parity Generator and Checker

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Parity Generator and Checker

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Exclusive OR and Exclusive NOR Circuits
The XOR (Exclusive OR) Gate

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Enable/Disable Circuits

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Programmable Logic Devices

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FLIP FLOPS AND RELATED
DEVICES

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Introduction
General Digital System

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Latches and Flip Flops
Latch : All Level Sensitive Control
Bistable Circuits
Exactly 2
Complementary
Outputs
Flip Flop: An Edge Sensitive Control

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NAND GATE LATCH

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Dominant?
0
0
0
1
1
NAND Latch
0 Dominant
1
01
Forbidden

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Alternate Representation

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R
S
Debouncing Circuit
R
S

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Alternate Representation

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SC NOR Latch
Dominant?1 Dominant
1 0
10
0 0
01
Forbidden

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NOR Gate Latch

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SC NOR Latch

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Enabled SC Latch

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Enabled SC Latch

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CLOCK SIGNALS AND
CLOCKED FLIP-FLOPS

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Clock Signals

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Flip-Flops

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Description of a Flip-Flop
Truth (Characteristic) Table
Lists how the state changes at the active clock edge

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Description of a Flip-Flop
Characteristic Equation
The Boolean equation derived from the characteristic table
𝑄 𝑛+1 = 𝑆 + 𝑅𝑄 𝑛

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Description of a Flip-Flop
State Diagram

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Description of a Flip-Flop
Excitation Table
input required to produce each output transition

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CLOCKED SC FLIP-FLOP

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SC Flip Flop

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SC Flip Flop

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SC Flip Flop

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SC Flip Flop Truth Table
S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
C/C Equation 1n nQ S RQ  

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SC Flip Flop State Diagram

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SC Flip Flop Logic Symbol

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SC Flip Flop Excitation Table

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Edge Detector
Positive Edge Detector

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Edge Detector
Positive Edge Detector

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Edge Detector
0
1
0
0
0
Positive Edge Detector

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Edge Detector
1
1
1
0
0 1
Positive Edge Detector

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Edge Detector
1
1
1
1
0 1
Positive Edge Detector

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Edge Detector
1
0
1
1
0 1
Positive Edge Detector

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Edge Detector
1
0
1
0
0 1
Positive Edge Detector

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Edge Detector
Negative Edge Detector

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Edge Detector
Negative Edge Detector

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Edge Detector
Negative Edge Detector

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D LATCH

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D Latch

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Enabled D Latch

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Enabled D Latch

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D Flip Flop

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CLOCKED D FLIP-FLOP

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D Flip Flop
S
R

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D Flip Flop

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D Flip Flop

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D Flip Flop Synchronizer

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CLOCKED JK FLIP FLOP

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Clocked JK Flip Flop

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Clocked JK Flip Flop

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JK Flip Flop Internal Circuitry

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JK Flip Flop

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JK Flip Flop

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JK Flip Flop Truth Table

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JK Flip Flop Truth Table
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
1n n nQ kQ JQ  JK Flip Flop C/C Equation

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JK Flip Flop State Diagram

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JK Flip Flop Excitation Table

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JK Flip Flop From D FF

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JK Flip Flop Timing Diagrams

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T FLIP FLOP

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T Flip Flop
𝑄 𝑛+1 = 𝑇 𝑄 + 𝑇𝑄 = 𝑇 ⊕ 𝑄

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T Flip Flop

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T Flip Flop

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T Flip Flop

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ASYNCHRONOUS INPUTS

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D Flip Flop

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D Flip Flop

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D Flip Flop

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Asynchronous Inputs

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Asynchronous Inputs

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SR Asynchronous Inputs

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JK Flip Flop

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JK Flip Flop

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FLIP-FLOP TIMING
CONSIDERATIONS

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Flip Flop Timing Considerations
Setup Time

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Flip Flop Timing Considerations
Hold Time

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Flip Flop Timing Considerations
D
tpd
tset-up
thold
C
Q
invalid

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Flip Flop Timing Considerations
Propagation Delay

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Flip Flop Timing Considerations
Clock Pulse High and Low
Asynchronous Pulse Width

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Flip Flop Timing Considerations
Clock Pulse High and Low Times
The Minimum required Times

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Flip Flop Timing Considerations
Asynchronous Active Pulse Width

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Flip Flop Timing Considerations
Asynchronous Active Pulse Width
The Minimum required Pre or Clr times

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Flip Flop Timing Considerations
Clock Transition Times:
Max, for the technology

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Flip Flop Timing Considerations
Setup time ts The time required that the input must be held before the active clock edge for
proper operation. For a typical flip-flop, ts is around 20 ns.
Hold time th The time required that the input must be held after the active clock edge for proper
operation. For most flip-flops, this is 0 ns meaning inputs need not be held beyond the active
clock signal.
TpLH Propagation delay from clock trigger point to the low-to-high Q output swing. A typical
TpLH for a flip-flop is around 20 ns.
TpHL Propagation delay from clock trigger point to the high-to-low Q output swing. A typical
TpLH for a flip-flop is around 20 ns.
[max Maximum frequency allowed at the clock input. Any frequency above this limit will
result in unreliable performance. Can vary greatly.
tw(L) Clock pulse width (low), the minimum width (in nanoseconds) that is allowed at the clock
input during the low level for reliable operation.
tw(H) Clock pulse width (high), the minimum width (in nanoseconds) that is allowed at the
clock input during the high level for reliable operation. Preset or clear pulse width Also given
by tw(L) , the minimum width (in nanoseconds) of the low pulse at the preset or clear inputs.

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Flip Flop Timing Considerations

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POTENTIAL TIMING
PROBLEM IN FF CIRCUITS

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Potential Timing Problem in FF Circuits

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01
1 1
1
1
Potential Timing Problem in FF Circuits

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01
Potential Timing Problem in FF Circuits

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01
Potential Timing Problem in FF Circuits

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01
0 0 0
0
Potential Timing Problem in FF Circuits

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10
0 0 0
0
Potential Timing Problem in FF Circuits

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FLIP-FLOP APPLICATIONS

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Flip Flop Applications
Examples:
1. Counting
2. Storing binary data
3. Transferring binary data between locations
Sequential circuits: the output follows a predetermined sequence
of states, with each clock pulse.

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FLIP-FLOP
SYNCHRONIZATION

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Flip Flop Synchronization

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Flip Flop Synchronization

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DETECTING AN INPUT
SEQUENCE

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Detecting an Input Sequence

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DATA STORAGE AND
TRANSFER

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Data Storage and Transfer
Synchronous Data Transfer

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Data Storage and Transfer
Asynchronous Data Transfer

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Data Storage and Transfer
Parallel Data Transfer

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SERIAL DATA TRANSFER:
SHIFT REGISTERS

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Serial Data Transfer: Shift Registers

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Serial Data Transfer: Shift Registers

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Serial Data Transfer: Shift Registers

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Serial Data Transfer: Shift Registers

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FREQUENCY DIVISION AND
COUNTING

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Frequency Division and Counting

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Frequency Division and Counting

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MICROCOMPUTER
APPLICATION

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Microprocessor Transferring Binary
Data To An External Register

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SCHMITT-TRIGGER DEVICES

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Schmitt Trigger Devices

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Schmitt Trigger Devices

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Schmitt Trigger Inverter

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Schmitt Trigger Inverter

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Schmitt Trigger Inverter
+ve Feedback

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Schmitt Trigger Inverter
1
1 2
o
R
v
R R

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Schmitt Trigger Inverter
THV
  0I THV V V V    

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Schmitt Trigger Inverter
  0I TLV V V V    
TLV

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Schmitt Trigger Inverter

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Schmitt Trigger Inverter
THV
  0I THV V V V    

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Schmitt Trigger Inverter
  0I TLV V V V    
TLV

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Schmitt Trigger Inverter

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Schmitt Trigger

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ONE-SHOT (MONOSTABLE
MULTIVIBRATOR)

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Monostable Multivibrators:
1. Nonretriggerable One Shot
2. Retriggerable One Shot
One Shot

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Nonretriggerable One Shot

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Retriggerable One Shot

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Retriggerable One Shot

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ANALYZING SEQUENTIAL
CIRCUITS

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Analyzing Sequential Circuits

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Analyzing Sequential Circuits

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CLOCK GENERATOR
CIRCUITS

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Clock Generator Circuits
Schmitt Trigger Inverter

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Clock Generator Circuits

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Clock Generator Circuits

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TROUBLESHOOTING FLIP-
FLOP CIRCUITS

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Clock Skew

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Clock Skew

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SEQUENTIAL CIRCUITS
USING HDL

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Sequential Circuits Using HDL

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Sequential Circuits Using HDL
The logic of a behavioral description of an S-R latch

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EDGE-TRIGGERED DEVICES

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HDL CIRCUITS WITH
MULTIPLE COMPONENTS

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END

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APPENDICES

174. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1899/21/2020
Product of Sums
Writing the Product-Of-Sums Boolean reduction for a K-map:
1. Group of 0s.
2. Binary representation.
3. Complement.
4. Convert to a sum-term.
5. Repeat for other groups.
6. And all results.

175. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1909/21/2020
Simplify
Minterms and Maxterms
Minterms Maxterms

176. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1919/21/2020
Minterms and Maxterms
F = xy'z + xyz' + yz
= x'yz + xy'z + xyz' + xyz
F(x, y, z) = m3 + m5 + m6 + m7
F(x, y, z) = Σ(3, 5, 6, 7)
To get Product of Sums:
1. Invert the equation.
2. Reduce it to sum-of-products.
3. Invert it again.

177. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1929/21/2020
Simplifying Logic Circuits
• Using Boolean Algebra Theorem
• Using Karnaugh Map

178. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1939/21/2020
Karnaugh Map Method

179. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1949/21/2020
Karnaugh Map Method

180. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1959/21/2020
Karnaugh Map Method

181. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1969/21/2020
Karnaugh Map Method

182. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1979/21/2020
Karnaugh Map Method

183. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1989/21/2020
Karnaugh Map Method

184. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 1999/21/2020
Parity Method for Error Detection
Data transmission or storage ► Errors
One Parity Bit is added to each group of bits
► ∑ bits is Either even or odd

185. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 2009/21/2020
Parity Method for Error Detection
Ex: C ASCII=1000011
Even Parity: 11000011
Odd Parity: 01000011

186. Copyright  Muhammad A M Islam.SBE202A Logic Gates and Boolean Algebra 2019/21/2020
Parity Method for Error Detection
Detects 1 bit error