The document summarizes the implementation of a regular expression matching hardware accelerator called TiReX. It describes the design choices including using three fetch and decode units to avoid pipeline stalls. It also discusses the challenges of implementing the execution unit to perform multiple character comparisons in parallel and the solution of using multiple comparator clusters. Finally, it provides results on the area utilization and performance compared to a software implementation on an Intel CPU.

1. Alessandro Comodi <alessandro.comodi@mail.polimi.it>
Davide Conficconi <davide.conficconi@mail.polimi.it>
TiReX
Courses@NECST, XOHW: Project Implementation
21st June, 2017 @ Seminar Room, DEIB

2. Design Choice 2
Implementation of a naive pattern matching
algorithm

3. 3
Implementation of a naive pattern matching
algorithm
Design Choice

4. 4Components implementation
Single component
design
Unit tests

5. 5Architecture Implementation

6. 6Architecture Implementation
Fetch & Decode Unit
Pipeline flush
Challenges
Instruction reload
Clock cycle loss

7. 7Architecture Implementation
Fetch & Decode Unit
Solution
Three F/D Units

8. 8Architecture Implementation
Execution
Unit
Challenge
Multiple character
comparison

9. Multiple comparator clusters
9Architecture Implementation
Execution
Unit
Intermediate results
analysis
Solution
Challenge

10. Engine component that outputs
a global match signal
10Architecture Implementation
Execution
Unit
Solution

11. 11Architecture Implementation
Data synchronization
Control Path
Parenthesis and Kleene
Operators
Challenges

12. 12Architecture Implementation
Control Path
Solutions
Direct link with Data Buffer
Implementation of a Stack
Buffer

13. AXI4 Lite
Peripheral
Wrapper
13Core Interface
TiReX
Core
An AXI4 Peripheral Wrapper handles the interface
between the core and the external architecture
BRAM

14. 14Block Design
TiReX IP Core
BRA
M

15. 15Results
Area
Utilization
Performance
*
VC-707 Board Slice LUTs Slice Reg. F7 Muxes F8 Muxes
LUT as
Logic
LUT as FF
Pairs
Available 303600 607200 75900 75900 303600 303600
TiReX
1757
[0.57%]
1590
[0.26%]
265
[0.35%]
114
[0.15%]
1757
[0.57%]
310
[0.1%]
Regular Expression
Time Flex
(intel i7 2.80Ghz)
Time TiReX
(100 MHz)
Speedup
ACCGTGGA 271 us 39,9 us 6,79x
(TTTT)+CT 121 us 81,35 us 1,48x
(CAGT)|(GGGG)|(TTGG)TGCA(C|G)+ 263 us 173,835 us 1,51x
* Dimension of the test file: 16 KB

16. Thank you for the attention!
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16
Davide Conficconi
<davide.conficconi@mail.polimi.it>
Alessandro Comodi
<alessandro.comodi@mail.polimi.it>
TiReX team <tirexatnecst@gmail.com>