The microprocessor OMAP 3430 contains a dual-core architecture consisting on an ARM Cortex-A8 (General-Purpose Processor) and a DSP C64x (as an Image-Video-Audio Accelerator).
The dspbridge is a kernel driver for the OMAP3 architecture. It provides a interface to control and communicate with the DSP, enabling parallel processing in embedded devices.
This talk will be about how to build a system with the dspbridge driver and how to use it for multimedia applications.
The document introduces the Desktop NanoBoard NB2DSK01, its daughter boards, and peripheral boards. The NanoBoard allows for flexible system design through plug-in daughter boards and peripheral boards. It has features like a touch screen, speakers, USB connectivity, and JTAG programming. Daughter boards host FPGA devices and peripheral boards add extra functions. Multiple NanoBoards can be chained together for larger designs.
Engineers may be missing what their company actually wants when deciding whether to build or buy testing solutions. Intellitech's pre-engineered SystemBIST software makes testing easier by simplifying tasks, allowing engineers without extensive system knowledge to create complex testing strategies. The software also allows downloading PCB-specific tests to integrated circuits, reducing development timelines and costs compared to traditional embedded software approaches.
Embest DevKit8000 Evaluation Kit includes the DevKit8000 OMAP 3530 evaluation board and all necessary accessories to help users start their design of multimedia applications.
Interface has developed an Advance File Graphics Server (AFGS) for a major avionics OEM that provides functionality equivalent to a Class III Electronic Flight Bag (EFB). The unit will be certified to RTCA DO-160D for environmental conditions and to RTCA DO-254 and RTCA DO-178B Level B for functionality. The AFGS employs a high-end Pentium® M processor with ARINC 429, Ethernet, RS-422, and USB interfaces, and accepts up to four external video sources of NTSC, S-Video, or PAL formats. The AFGS provides both rendered video images and multiplexed video sources to the aircraft's existing display units.
Honeywell has released a new digital video codec called the HUSS-E1/D1 that uses H.264 encoding for clear video monitoring. It can present smoother real-time video even with limited bandwidth through powerful multicast functions. Users can also flexibly switch between and view multiple video feeds on the same screen using powerful virtual matrix software. The codec supports local and remote video storage through USB drives to ensure video is safely stored even if the network fails.
The document describes the TSUMV59XUS, a single-chip solution for analog TV systems that supports TV channels and various multimedia decoding functions. It integrates analog TV demodulation, video and audio decoding, processing, and output into a single chip to reduce costs. Key features include support for analog TV, MPEG-2/4, H.264, RealMedia, AVS, and other video formats as well as audio decoding and advanced sound processing. The chip also includes interfaces such as HDMI, DVI, USB and supports resolutions up to 4K.
This document describes a real-time video and image processing system that combines a Spartan 3 FPGA and DSP array on a SigC641x card. The DSP array can include up to 8 Texas Instruments 1 GHz DSPs with access to various analog and digital video I/O. Video data is preprocessed by the FPGA and DSPs before being sent to the PCI bus or between DSPs. The system provides SD and HD video I/O and is in alpha testing, with production units expected in 3Q08.
The document introduces the Desktop NanoBoard NB2DSK01, its daughter boards, and peripheral boards. The NanoBoard allows for flexible system design through plug-in daughter boards and peripheral boards. It has features like a touch screen, speakers, USB connectivity, and JTAG programming. Daughter boards host FPGA devices and peripheral boards add extra functions. Multiple NanoBoards can be chained together for larger designs.
Engineers may be missing what their company actually wants when deciding whether to build or buy testing solutions. Intellitech's pre-engineered SystemBIST software makes testing easier by simplifying tasks, allowing engineers without extensive system knowledge to create complex testing strategies. The software also allows downloading PCB-specific tests to integrated circuits, reducing development timelines and costs compared to traditional embedded software approaches.
Embest DevKit8000 Evaluation Kit includes the DevKit8000 OMAP 3530 evaluation board and all necessary accessories to help users start their design of multimedia applications.
Interface has developed an Advance File Graphics Server (AFGS) for a major avionics OEM that provides functionality equivalent to a Class III Electronic Flight Bag (EFB). The unit will be certified to RTCA DO-160D for environmental conditions and to RTCA DO-254 and RTCA DO-178B Level B for functionality. The AFGS employs a high-end Pentium® M processor with ARINC 429, Ethernet, RS-422, and USB interfaces, and accepts up to four external video sources of NTSC, S-Video, or PAL formats. The AFGS provides both rendered video images and multiplexed video sources to the aircraft's existing display units.
Honeywell has released a new digital video codec called the HUSS-E1/D1 that uses H.264 encoding for clear video monitoring. It can present smoother real-time video even with limited bandwidth through powerful multicast functions. Users can also flexibly switch between and view multiple video feeds on the same screen using powerful virtual matrix software. The codec supports local and remote video storage through USB drives to ensure video is safely stored even if the network fails.
The document describes the TSUMV59XUS, a single-chip solution for analog TV systems that supports TV channels and various multimedia decoding functions. It integrates analog TV demodulation, video and audio decoding, processing, and output into a single chip to reduce costs. Key features include support for analog TV, MPEG-2/4, H.264, RealMedia, AVS, and other video formats as well as audio decoding and advanced sound processing. The chip also includes interfaces such as HDMI, DVI, USB and supports resolutions up to 4K.
This document describes a real-time video and image processing system that combines a Spartan 3 FPGA and DSP array on a SigC641x card. The DSP array can include up to 8 Texas Instruments 1 GHz DSPs with access to various analog and digital video I/O. Video data is preprocessed by the FPGA and DSPs before being sent to the PCI bus or between DSPs. The system provides SD and HD video I/O and is in alpha testing, with production units expected in 3Q08.
The Radius from NextComputing is a portable computing system designed for professional users who need more powerful and expandable capabilities than a laptop. The Radius has a lightweight briefcase form factor and features an upgradeable architecture that allows users to add expansion cards and increase storage, memory, and processing power. It is intended for applications such as digital media work, testing and measurement, 3D design, engineering, demonstrations, and mobile training systems.
The document provides an overview of the S5L2010 DPF processor. Key details include:
- It is built around an ARM9 core and includes video/audio decoding, display, and peripheral interfaces.
- Main features include support for MPEG video/audio, JPEG decoding, LCD interfaces, memory card interfaces, and timers/PWM outputs.
- It comes in several packages targeting different display types and includes various peripherals and interfaces.
This document summarizes the TechnoTrend S2-3650CI HDTV receiver box. It connects to a PC via USB 2.0 port, allowing HDTV reception on computers. It supports various encryption systems and has a CI slot for pay TV access. Installation and setup are simple - the device is automatically detected and drivers installed. The included software allows viewing live and recorded TV, with an EPG, favorites lists, and timer functions. It receives channels from various satellites but does not support DiSEqC 1.1 switching. Overall it provides an affordable way to get HDTV reception on a PC.
SoftJin provides electronic design automation (EDA) services including outsourced R&D, system design and verification, and design IP. They offer a portfolio of IPs across various domains including video, image, audio processing, communications, and memory controllers. Their services focus on multimedia applications and they provide consulting, IP development and licensing, and system reengineering. Their goal is to provide innovative customized solutions for electronic design and manufacturing.
The document summarizes the TechnoTrend S2-3650CI HDTV receiver box. It connects to a PC via USB 2.0 port and receives HDTV signals from satellites, supporting various encryption systems. Setup and use of the included software is simple. The software provides electronic program guide data, channel scanning/editing functions, and playback/recording capabilities for enjoying HDTV content on a PC. The overall build quality is good and reception/performance was stable based on testing various features of the TechnoTrend receiver box.
This document provides specifications for the DT-V21G11 21-inch multi-format LCD monitor. It supports various video formats including 3G-SDI, dual link HD-SDI, and HDMI. Key features include a full HD 1920x1080 resolution LCD panel, built-in vector scope, waveform monitor and 16-channel audio level meter for monitoring video and audio signals. The monitor is suitable for professional studio applications handling multiple video formats.
The Radius portable system from NextComputing is a lightweight, briefcase-sized system that offers more power than a laptop. It has an expandable and upgradeable architecture that allows users to add expansion cards and easily upgrade storage, memory, and processors. The Radius is designed for professional users who need powerful portable computing for tasks such as digital media work, testing and measurement, 3D design, engineering, demonstrations, and mobile training systems.
The document describes an IP and hybrid set-top box development kit that supports the latest HD standards like H.264 and VC-1. The kit includes an SoC with a powerful CPU, advanced video decoding capabilities, audio processing, and connectivity options. It allows developers to create affordable set-top boxes that deliver high quality HD experiences to customers.
The document describes the Dana Server, a digital audio network appliance with a flexible I/O configuration. It has a 32-bit floating point DSP, analog and digital I/O cards, audio processing plugins, and network control capabilities. The Dana Server is designed to leverage existing IT infrastructure by using Ethernet for both audio and control data transport, providing greater scalability and simplicity for audio distribution applications.
The document provides information on the STi7105, a low-cost advanced HD decoding IC for set-top boxes. It features advanced video and audio decoding, a CPU, memory interface, graphics processing, display outputs, security features, and peripherals. The STi7105 is targeted at next generation HD set-top boxes using cable, satellite, terrestrial, IP, and hybrid networks. Typical applications include DVR cable boxes, IP client boxes, and satellite boxes.
Auto Watchdog SD series mobile dvr offer the economical and reliable in vehicle CCTV solutions for bus, taxi, truck and other vehicles security. D1, H.264, 3G, WIFI and GPS support. CMS also offer the powerful fleet management online. More details on
www.vehicle-dvr.com
The system report summarizes the hardware and software configuration of a Windows XP system. It includes details about the processor, memory, graphics card, sound devices, and installed drivers. A Nvidia GeForce 9400 GT graphics card and Realtek audio devices are listed. The system has 2 GB of RAM and is running Windows XP SP3 in Spanish.
This ppt will help you to do complet study of Sci fuctional block diagram and full details about register used in sci . one sample uart transmit code logic explained briefly.
This document summarizes a student project to create a video signal converter box called "Boxy". The original goal was an customizable box that could convert and duplicate audio/video inputs and outputs. However, difficulties led to a reduced design with HDMI and VGA inputs selectable from a user interface on an LCD screen using buttons. The design uses a Zynq FPGA with video IP blocks and FreeRTOS tasks to handle the user interface.
The TeVii S480 is a twin-tuner PCI Express card for a PC that allows the PC to receive two independent HDTV streams simultaneously. It includes software to control the card's functions and turn the PC into a fully functional DVB-S/S2 TV and PVR system. The card was able to quickly scan channels and receive signals, even weaker ones, without issues. The included software provides robust control and customization of the card's settings and features. Overall, the TeVii S480 is able to transform a PC into a powerful HDTV receiver capable of receiving two channels at once.
The Datavideo HS-550 is a compact, portable mobile video studio contained within a single carrying case. It features a 4-channel video switcher, dual monitor bank, 5-channel intercom system, and optional solid state recorder. The HS-550 allows for mixing of up to 4 composite video cameras or 3 cameras plus 1 VGA/DVI source. It provides multiview display of all sources and a recording solution in a fully-integrated portable package for live production.
The document provides a user manual for the Odyssey7Q+ monitor/recorder, including:
- An overview of its monitoring, recording, and playback capabilities such as Apple ProRes, RAW recording formats, and multistream monitoring/recording.
- Specifications for its display, I/O ports, recording media, and accessories.
- Instructions for setup, menu navigation, recording, playback and more.
Interfacing methods of microcontrollerDiwaker Pant
The document discusses microcontroller interfacing and is presented by Diwaker Pant. It defines interfacing as the transfer of data between microcontrollers and peripherals using buses. Interfacing is needed to connect a microcontroller's computation capabilities to external signals or devices to enable human-computer interaction. Various interfacing methods for microcontrollers like wires, buses, and serial interfaces like I2C and SPI are described. Examples of interfacing microcontrollers to devices like memory and displays are provided. In conclusion, suitable interfacing methods can be used to create human-machine interaction and make technology more user friendly.
This document provides an overview and outline for designing a USB device driver. It discusses USB hardware controllers, the architecture of an embedded USB device including driver components and threads. It describes the USB device driver API including functions for initialization, opening/closing endpoints, reading/writing data, and handling control transfers. The document uses examples to illustrate interrupt handling, enumeration, and data transfer processes involving the USB controller hardware and endpoint FIFOs.
Introduction to Parallel Processing Algorithms in Shared Nothing DatabasesOfir Manor
This document provides an introduction to parallel processing algorithms in shared nothing databases. It discusses scaling databases through a shared nothing architecture where data is sharded across multiple independent nodes. Examples are given of single table processing and join processing across the sharded database. Execution plans are shown for queries involving filtering, aggregation, sorting and joins on single and multiple tables both when the tables are distributed by the same key and different keys.
Massively Parallel Processing with Procedural Python (PyData London 2014)Ian Huston
The Python data ecosystem has grown beyond the confines of single machines to embrace scalability. Here we describe one of our approaches to scaling, which is already being used in production systems. The goal of in-database analytics is to bring the calculations to the data, reducing transport costs and I/O bottlenecks. Using PL/Python we can run parallel queries across terabytes of data using not only pure SQL but also familiar PyData packages such as scikit-learn and nltk. This approach can also be used with PL/R to make use of a wide variety of R packages. We look at examples on Postgres compatible systems such as the Greenplum Database and on Hadoop through Pivotal HAWQ. We will also introduce MADlib, Pivotal’s open source library for scalable in-database machine learning, which uses Python to glue SQL queries to low level C++ functions and is also usable through the PyMADlib package.
The Radius from NextComputing is a portable computing system designed for professional users who need more powerful and expandable capabilities than a laptop. The Radius has a lightweight briefcase form factor and features an upgradeable architecture that allows users to add expansion cards and increase storage, memory, and processing power. It is intended for applications such as digital media work, testing and measurement, 3D design, engineering, demonstrations, and mobile training systems.
The document provides an overview of the S5L2010 DPF processor. Key details include:
- It is built around an ARM9 core and includes video/audio decoding, display, and peripheral interfaces.
- Main features include support for MPEG video/audio, JPEG decoding, LCD interfaces, memory card interfaces, and timers/PWM outputs.
- It comes in several packages targeting different display types and includes various peripherals and interfaces.
This document summarizes the TechnoTrend S2-3650CI HDTV receiver box. It connects to a PC via USB 2.0 port, allowing HDTV reception on computers. It supports various encryption systems and has a CI slot for pay TV access. Installation and setup are simple - the device is automatically detected and drivers installed. The included software allows viewing live and recorded TV, with an EPG, favorites lists, and timer functions. It receives channels from various satellites but does not support DiSEqC 1.1 switching. Overall it provides an affordable way to get HDTV reception on a PC.
SoftJin provides electronic design automation (EDA) services including outsourced R&D, system design and verification, and design IP. They offer a portfolio of IPs across various domains including video, image, audio processing, communications, and memory controllers. Their services focus on multimedia applications and they provide consulting, IP development and licensing, and system reengineering. Their goal is to provide innovative customized solutions for electronic design and manufacturing.
The document summarizes the TechnoTrend S2-3650CI HDTV receiver box. It connects to a PC via USB 2.0 port and receives HDTV signals from satellites, supporting various encryption systems. Setup and use of the included software is simple. The software provides electronic program guide data, channel scanning/editing functions, and playback/recording capabilities for enjoying HDTV content on a PC. The overall build quality is good and reception/performance was stable based on testing various features of the TechnoTrend receiver box.
This document provides specifications for the DT-V21G11 21-inch multi-format LCD monitor. It supports various video formats including 3G-SDI, dual link HD-SDI, and HDMI. Key features include a full HD 1920x1080 resolution LCD panel, built-in vector scope, waveform monitor and 16-channel audio level meter for monitoring video and audio signals. The monitor is suitable for professional studio applications handling multiple video formats.
The Radius portable system from NextComputing is a lightweight, briefcase-sized system that offers more power than a laptop. It has an expandable and upgradeable architecture that allows users to add expansion cards and easily upgrade storage, memory, and processors. The Radius is designed for professional users who need powerful portable computing for tasks such as digital media work, testing and measurement, 3D design, engineering, demonstrations, and mobile training systems.
The document describes an IP and hybrid set-top box development kit that supports the latest HD standards like H.264 and VC-1. The kit includes an SoC with a powerful CPU, advanced video decoding capabilities, audio processing, and connectivity options. It allows developers to create affordable set-top boxes that deliver high quality HD experiences to customers.
The document describes the Dana Server, a digital audio network appliance with a flexible I/O configuration. It has a 32-bit floating point DSP, analog and digital I/O cards, audio processing plugins, and network control capabilities. The Dana Server is designed to leverage existing IT infrastructure by using Ethernet for both audio and control data transport, providing greater scalability and simplicity for audio distribution applications.
The document provides information on the STi7105, a low-cost advanced HD decoding IC for set-top boxes. It features advanced video and audio decoding, a CPU, memory interface, graphics processing, display outputs, security features, and peripherals. The STi7105 is targeted at next generation HD set-top boxes using cable, satellite, terrestrial, IP, and hybrid networks. Typical applications include DVR cable boxes, IP client boxes, and satellite boxes.
Auto Watchdog SD series mobile dvr offer the economical and reliable in vehicle CCTV solutions for bus, taxi, truck and other vehicles security. D1, H.264, 3G, WIFI and GPS support. CMS also offer the powerful fleet management online. More details on
www.vehicle-dvr.com
The system report summarizes the hardware and software configuration of a Windows XP system. It includes details about the processor, memory, graphics card, sound devices, and installed drivers. A Nvidia GeForce 9400 GT graphics card and Realtek audio devices are listed. The system has 2 GB of RAM and is running Windows XP SP3 in Spanish.
This ppt will help you to do complet study of Sci fuctional block diagram and full details about register used in sci . one sample uart transmit code logic explained briefly.
This document summarizes a student project to create a video signal converter box called "Boxy". The original goal was an customizable box that could convert and duplicate audio/video inputs and outputs. However, difficulties led to a reduced design with HDMI and VGA inputs selectable from a user interface on an LCD screen using buttons. The design uses a Zynq FPGA with video IP blocks and FreeRTOS tasks to handle the user interface.
The TeVii S480 is a twin-tuner PCI Express card for a PC that allows the PC to receive two independent HDTV streams simultaneously. It includes software to control the card's functions and turn the PC into a fully functional DVB-S/S2 TV and PVR system. The card was able to quickly scan channels and receive signals, even weaker ones, without issues. The included software provides robust control and customization of the card's settings and features. Overall, the TeVii S480 is able to transform a PC into a powerful HDTV receiver capable of receiving two channels at once.
The Datavideo HS-550 is a compact, portable mobile video studio contained within a single carrying case. It features a 4-channel video switcher, dual monitor bank, 5-channel intercom system, and optional solid state recorder. The HS-550 allows for mixing of up to 4 composite video cameras or 3 cameras plus 1 VGA/DVI source. It provides multiview display of all sources and a recording solution in a fully-integrated portable package for live production.
The document provides a user manual for the Odyssey7Q+ monitor/recorder, including:
- An overview of its monitoring, recording, and playback capabilities such as Apple ProRes, RAW recording formats, and multistream monitoring/recording.
- Specifications for its display, I/O ports, recording media, and accessories.
- Instructions for setup, menu navigation, recording, playback and more.
Interfacing methods of microcontrollerDiwaker Pant
The document discusses microcontroller interfacing and is presented by Diwaker Pant. It defines interfacing as the transfer of data between microcontrollers and peripherals using buses. Interfacing is needed to connect a microcontroller's computation capabilities to external signals or devices to enable human-computer interaction. Various interfacing methods for microcontrollers like wires, buses, and serial interfaces like I2C and SPI are described. Examples of interfacing microcontrollers to devices like memory and displays are provided. In conclusion, suitable interfacing methods can be used to create human-machine interaction and make technology more user friendly.
This document provides an overview and outline for designing a USB device driver. It discusses USB hardware controllers, the architecture of an embedded USB device including driver components and threads. It describes the USB device driver API including functions for initialization, opening/closing endpoints, reading/writing data, and handling control transfers. The document uses examples to illustrate interrupt handling, enumeration, and data transfer processes involving the USB controller hardware and endpoint FIFOs.
Introduction to Parallel Processing Algorithms in Shared Nothing DatabasesOfir Manor
This document provides an introduction to parallel processing algorithms in shared nothing databases. It discusses scaling databases through a shared nothing architecture where data is sharded across multiple independent nodes. Examples are given of single table processing and join processing across the sharded database. Execution plans are shown for queries involving filtering, aggregation, sorting and joins on single and multiple tables both when the tables are distributed by the same key and different keys.
Massively Parallel Processing with Procedural Python (PyData London 2014)Ian Huston
The Python data ecosystem has grown beyond the confines of single machines to embrace scalability. Here we describe one of our approaches to scaling, which is already being used in production systems. The goal of in-database analytics is to bring the calculations to the data, reducing transport costs and I/O bottlenecks. Using PL/Python we can run parallel queries across terabytes of data using not only pure SQL but also familiar PyData packages such as scikit-learn and nltk. This approach can also be used with PL/R to make use of a wide variety of R packages. We look at examples on Postgres compatible systems such as the Greenplum Database and on Hadoop through Pivotal HAWQ. We will also introduce MADlib, Pivotal’s open source library for scalable in-database machine learning, which uses Python to glue SQL queries to low level C++ functions and is also usable through the PyMADlib package.
This document provides an overview of topics to be covered in a database management systems course, including parallel and distributed databases, NoSQL databases, and MapReduce. It discusses parallel databases and different architectures for distributed databases. It introduces several NoSQL databases like Amazon SimpleDB, Google BigTable, and HBase and describes their data models and implementations. It also provides details about MapReduce, including its programming model, implementation, optimizations, and statistics on its usage at Google. The next class meetings will include a mid-term exam, student presentations on assigned topics, and a proposal for each student's final project.
Load Balancing in Parallel and Distributed DatabaseMd. Shamsur Rahim
This document discusses load balancing techniques in distributed database systems. It describes different types of parallelism including inter-query, intra-query, intra-operation, and inter-operation parallelism. It also discusses problems that can occur with parallel execution such as initialization, interference, and skew. The document then focuses on techniques for load balancing within operators and between operators, including adaptive and specialized techniques. It describes how activations, activation queues, and threads can be used to improve load balancing in shared-memory systems.
This document discusses distributed database management systems (DBMS). It covers topics like distributed database design, distributed query processing, and transaction management in a distributed environment. It also discusses parallel DBMS architectures like shared memory, shared disk, and shared nothing and techniques for data partitioning, parallel query processing and optimization in a distributed parallel DBMS.
Data Processing and Aggregation with MongoDB MongoDB
The document discusses data processing and aggregation using MongoDB. It provides an example of using MongoDB's map-reduce functionality to count the most popular pub names in a dataset of UK pub locations and attributes. It shows the map and reduce functions used to tally the name occurrences and outputs the top 10 results. It then demonstrates performing a similar analysis on just the pubs located in central London using MongoDB's aggregation framework pipeline to match, group and sort the results.
Dynamic Scaling: How Apache Flink Adapts to Changing Workloads (at FlinkForwa...Till Rohrmann
This document discusses dynamic scaling in Apache Flink. It describes Flink's approach to dynamically scaling stateful jobs to adapt to changing workloads. Key points include: repartitioning of keyed and non-keyed state when scaling workers, supporting manual rescaling through savepoints and restarts currently, and future work on scaling operators without restarts and implementing automatic scaling policies.
Flink vs. Spark: this is the slide deck of my talk at the 2015 Flink Forward conference in Berlin, Germany, on October 12, 2015. In this talk, we tried to compare Apache Flink vs. Apache Spark with focus on real-time stream processing. Your feedback and comments are much appreciated.
The document discusses parallel databases and their architectures. It introduces parallel databases as systems that seek to improve performance through parallelizing operations like loading data, building indexes, and evaluating queries using multiple CPUs and disks. It describes three main architectures for parallel databases: shared memory, shared disk, and shared nothing. The shared nothing architecture provides linear scale-up and speed-up but is more difficult to program. The document also discusses measuring performance improvements from parallelization through speed-up and scale-up.
GStreamer and SysLink (GStreamer Conference 2011)Igalia
By Víctor Jáquez.
SysLink is a multi-core Inter-Processor Communication (IPC) software stack, pushed by Texas Instrument, where the developers could take advantage of asymmetric multiprocessing with several heterogeneous processors running different instances of operating system, whether Linux or any other flavor of RT OS.
In the realm of the multimedia processing, this mechanism offloads the CPU-intensive (de)codification tasks from the host processor, enhancing the user experience, particularly in embedded devices, where specialized processing units could be stored on SoCs.
This talk will describe the main SysLink components (Linux kernel API, RCM modules, etc.) and how we could map those concepts into GStreamer elements, providing hardware accelerated multimedia, but without the burden of OpenMAX. The target SoC is the OMAP4 using a panda-board.
The Radius portable system from NextComputing is a lightweight, briefcase-sized system that offers more power than a laptop. It has an expandable and upgradeable architecture that allows users to add expansion cards and easily upgrade storage, memory, and processors. The Radius is designed for professional users who need portable computing power for tasks such as digital media work, testing and measurement, 3D design, engineering, demonstrations, and mobile training systems.
Track F- Designing the kiler soc - sonicschiportal
Jack Browne discusses designing system-on-chips (SoCs) to keep pace with innovation. SoC design costs are growing significantly with each new process node. Distributed, heterogeneous architectures with multiple processors and distributed memory and I/O are also increasing complexity. SNAP provides a solution by replacing bus matrices and bridges with a high performance interconnect that eases timing closure and supports performance exploration and validation.
This document provides an overview of UEFI and HP's transition to UEFI for ProLiant servers. Some key points:
- UEFI was created by HP and Intel in the late 1990s to overcome BIOS limitations and support new technologies like large disks and 64-bit processors. It has since become an industry standard supported by all major operating systems.
- HP drove adoption of UEFI and helped establish the UEFI Forum to develop and promote the standard. ProLiant Gen9 servers were the first to default to UEFI boot, moving HP to UEFI Class 2 compliance. Future servers aim for Class 3 (UEFI-only).
- UEFI provides advantages over legacy BIOS like large
This document provides a product roadmap for VXL Instruments covering their zero client, desktop thin client, and desktop hardware solutions from Q2 2013 through Q4 2015. It includes details on their zero client product lines such as the J12-z and F12z series based on ARM and VIA processors respectively. It also outlines their desktop thin client and desktop product portfolio spanning entry-level, mid-range, and high-performance solutions powered by processors including VIA Eden, Intel Baytrail, and AMD Kabini. The roadmap further provides an overview of the company, their manufacturing infrastructure, and operating system support.
- The document provides an overview of the Beagle Board, including its features, community, and typical uses. It discusses booting the board and describes the five phases of the boot process from the ROM loading the bootloader to the kernel loading the root file system. Examples of community projects using the board are also listed.
This is a presentation I gave on impulse at Open Database Camp in Sardegna, Italy last weekend, en then a bit less impulsively at the Inuits igloo.
A word of caution: I included the notes because they contain some extra info, but the presentation was hacked together from several older ones (not all of them my own) so there might be some flukes in there. :)
The document discusses the hardware aspects of PCI and PCIe buses. It covers topics like bus architecture, enumeration, configuration space, interrupts, I/O vs memory mapped I/O. It provides sample output of lspci commands to display bus information in a tree structure and device details. The document is split into two parts - part 1 discusses the hardware details, while part 2 will cover code highlights of a PCI/PCIe driver.
The document discusses Linux video drivers and frameworks. It describes the original frame buffer and console interfaces. It then summarizes the Video For Linux v2 (v4l2) framework, which defines structures like the "Video Device" and mechanisms for video buffer and control management. The v4l2 framework aims to provide a complete and integrated solution for working with video and audio devices.
ELCE 2010 - State Of Multimedia In 2010 Embedded Linux DevicesBenjamin Zores
The document provides an overview of multimedia capabilities and options for embedded Linux devices in 2010. It discusses hardware selection factors for different ARM and MIPS SoCs. It also examines the state of 2D, 3D and video support, including both software and hardware implementations. Finally, it considers underlying operating system choices and application frameworks for developing software on embedded devices.
The document provides a high-level overview of the Olo River digital home platform:
1. The Olo River SoC includes an Intel XScale CPU, video and audio decoding/encoding capabilities, security features, graphics acceleration, memory interfaces, and peripheral interfaces.
2. The Olo Creek development board is a reference design for the Olo River SoC and includes features like memory, PCI/miniPCI slots, smart card interfaces, audio/video I/O, USB, Ethernet, and SATA.
3. The Olo River software architecture includes drivers, libraries and middleware to support features like graphics, audio, streaming media, and interfaces to external devices. Applications can use graphics APIs and
Slides presented at the FlexTiles Workshop at FPL'2014.
Presentation #3: FlexTiles DSP Accelerators
FlexTiles is a heterogeneous many-core platform reconfigurable at run-time developed within an FP7 project.
VPX Profiles To Platforms, SIE Computing Solutionsjillmcolna
The goal of VPX is to provide critical embedded system integrators with a more capable module standard that allows for better exploitation of new technologies, enabling more cost effective end systems. The US Department of Defense and other users are now mandating the implementation of COTS Open Standards like VPX and OpenVPX.
This document summarizes a presentation about Lagopus, an SDN software switch developed by NTT. Some key points:
- Lagopus aims to provide an SDN-aware switch software stack capable of 100Gbps performance, including an OpenFlow agent and extensible configuration data store.
- Existing virtual switches do not provide sufficient performance for carrier networks. Lagopus takes a simplified, modular design compiled using DPDK for high-performance packet processing.
- An FPGA-based 40GbE NIC was developed to offload processing tasks like encryption and packet scheduling for improved performance.
- Evaluation shows Lagopus can achieve wire-rate throughput of 10Gbps and support over 1 million flow
This document provides instructions for setting up and accessing a Raspberry Pi without a monitor or keyboard. It outlines downloading and writing the Raspbian OS image to an SD card using Win32DiskImager. It then explains how to use Advanced IP Scanner or the router's configuration page to find the Raspberry Pi's IP address after connecting it to the network via Ethernet. Finally, it describes establishing an SSH connection to the Raspberry Pi using PuTTY on a PC or the Terminal on a Mac to access the command prompt remotely for initial setup and configuration without needing a monitor or keyboard attached to the Raspberry Pi itself.
This document provides specifications for two ASUS Zenbook Ultrabook models, the UX21 and UX31. It lists the processors, operating systems, dimensions, memory, displays, I/O ports, storage, battery life, and other key specifications of the two models. The UX31 has a larger 13.3 inch screen compared to the 11.6 inch screen of the UX21. Both models are thin and light with quick resume capabilities and long battery life.
The document introduces the Jade family of graphics controllers from Fujitsu, which include the MB86R01, MB86R02, and MB86R03. The controllers feature an ARM926EJ-S CPU, a Coral-class 2D/3D graphics processing unit, and peripheral interfaces. They support up to four simultaneous displays with resolutions up to 1280x768. Development tools and additional resources are also mentioned.
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The DSP/BIOS Bridge - OMAP3
1. The DSP/BIOS Bridge
Víctor Manuel Jáquez Leal
Igalia
06 February 2010
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 1 / 41
2. The TI OMAP3 processor
I The TI OMAP3 processor
P The DSP/BIOS Bridge
Q The ingredients
R Future
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 2 / 41
3. The TI OMAP3 processor
Parallel computing
Serial computing is now dead.
€—r—llel ™omputing @whi™h st—rted more th—n RH ye—rs —goA is —
revolution th—t is now upon us
Programming for serial computing is already dicult
€rogr—mming for p—r—llel ™omputing will only ex—™er˜—te this di0™ulty
por p—r—llelism to su™™eed it must produ™e ˜etter perform—n™eD
e0™ien™y —nd reli—˜ility
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 2 / 41
4. The TI OMAP3 processor
OMAP 3530/20
720 MHz ARM Cortex A8
520 MHz TMS320C64x+ DSP
POWERVR SGX Graphics Accelerator
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 3 / 41
5. The TI OMAP3 processor
Devices and boards using OMAP3
There are a lot!
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 4 / 41
6. The TI OMAP3 processor
The C64x+ DSP
Digital Signal Processor
ƒpe™i—lized mi™ropro™essor
por f—st exe™ution of digit—l sign—l pro™essing
vow power ™onsumption
Digital Signal Processing
we—surement —nd (ltering of ™ontinuous re—lEworld —n—log sign—ls
eudioD videoD spee™hD —re ex—mples of those sign—ls
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 5 / 41
7. The DSP/BIOS Bridge
DSP-GPP parallel computing
Features to control the DSP
Mechanisms to communicate with DSP
Enabling parallel processing for multimedia acceleration
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 6 / 41
8. The DSP/BIOS Bridge
Available drivers
dsp-gateway
heveloped ˜y xoki— for the w—emo snternet „—˜lets
st works on ywe€I —nd ywe€P
st9s produ™tion re—dy
st9s used on the xoki— xVHH —nd xVIH
st follows vinux st—nd—rds —nd it9s ™lose to upstre—m —™™ept—n™e
„here9s ™ode for ywe€Q ˜ut it h—sn9t ˜een thoroughly tested
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 7 / 41
9. The DSP/BIOS Bridge
Available drivers
dsp-bridge
yrigin—lly developed ˜y „s
st still doesn9t meet vinux st—nd—rds —lthough there h—s ˜een — lot of
progress
ynly the e‚w side is —v—il—˜le —s open sour™eY the hƒ€ side is
™ompletely ™losed
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 8 / 41
10. The DSP/BIOS Bridge
Available drivers
dsp-link
e slimmer version of the dspE˜ridge
elso developed ˜y „s
st supports — wide v—riety of devi™es @h—†in™iD ywe€PD ywe€QD et™A
„he kernel driver doesn9t meet the vinux kernel ™oding ™onventions
„he sour™es h—ven9t ˜een su˜mitted for reviewD —nd it is not ™urrently
pl—nned to ˜e merged into upstre—m kernels
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 9 / 41
11. The DSP/BIOS Bridge
DSP/BIOS Bridge
General Architecture
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 10 / 41
12. The DSP/BIOS Bridge
Architecture
It is designed for one GPP and one or more attached DSPs
„he q€€ is ™onsidered the m—ster or host pro™essor
„he —tt—™hed hƒ€s —re pro™essing resour™es th—t ™—n ˜e used ˜y
—ppli™—tions running on the q€€
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 11 / 41
14. The DSP/BIOS Bridge
Architecture
The Bridge supplies a link between a GPP program and a DSP task
The communication link is partitioned into two types:
wess—ging @shortD (xedElength p—™ketsAX por p—ssing ™ontrol —nd st—tus
inform—tion
h—t— stre—ming @multipleD l—rge ˜u'ersAX for stre—ming re—lEtime d—t—
Each sub-link operates independently
A GPP client can specify what inputs and outputs a DSP task uses
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 13 / 41
15. The DSP/BIOS Bridge
GPP Sopftware Architecture
The GPP OS see the DSP just as another peripheral device
root@beagleboard:~# ls -la /dev/DspBridge
crw-rw---- 1 root root 251, 0 Jan 1 2000 /dev/DspBridge
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 14 / 41
16. The DSP/BIOS Bridge
DSP Software Architecture
From the DSP/BIOS perspective, the bridge provides
e devi™eEindependent stre—ming sGy @ƒ„‚wA interf—™e
e mess—ging interf—™e @xyhiA
e ‚esour™e w—n—ger @‚wA ƒerver
The task environment is established by the RM Server
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 15 / 41
18. The DSP/BIOS Bridge
Components (GPP)
Resource Manager
hyn—mi™—lly inst—nti—ting hƒ€ resour™es
wonitoring hƒ€ resour™es
hyn—mi™—lly lo—ding hƒ€ ™ode —s needed
smplementing poli™ies for m—n—ging hƒ€ resour™es
Platform Manager
ƒt—ti™—lly lo—ding — ˜—se ™ode im—ge for the hƒ€
ƒt—rting —nd stopping the hƒ€
smplementing d—t— stre—ming
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 17 / 41
19. The DSP/BIOS Bridge
Components (GPP)
OS adaptation layer
DSP link driver for low level communication
A dynamic conguration database (DCD) stores conguration
information
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 18 / 41
20. The DSP/BIOS Bridge
Components (DSP)
DSP/BIOS communicates with the GPP via the link driver
On top of the DSP/BIOS sits the Resource Manager (RM) Server
hyn—mi™—lly ™re—teD exe™ute —nd destroy hƒ€ pro™essing nodes under
‚esour™e w—n—ger ™ontrol
‚outing mess—ges ˜etween the q€€ —nd individu—l nodes
eltering t—sk priorities
‚esponding to ‚esour™e w—n—ger ™on(gur—tion ™omm—nds
ƒt—tus queries
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 19 / 41
21. The DSP/BIOS Bridge
Components (DSP)
DSP task nodes
„hey —re sep—r—te exe™ution thre—ds running on the hƒ€
„hey implement ™ontrol or sign—l pro™essing —lgorithms
„hey ™ommuni™—te with one —notherD —nd with the q€€
via short xed length messages and/or device-independent stream I/O.
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 20 / 41
22. The DSP/BIOS Bridge
GPP Side interface
Manager
…sed to o˜t—in hƒ€ pro™essor —nd m—nipul—te node ™on(gur—tion
inform—tion
Processor
…sed to m—nipul—te hƒ€ pro™essor o˜je™tsD whi™h represent p—rti™ul—r
hƒ€ su˜systems linked to the q€€
€ro™essor o˜je™ts —re used to ™re—teD exe™ute —nd delete nodes on —
p—rti™ul—r hƒ€ su˜system
es hƒ€Gfsyƒ fridge ™lients m—ke pro™essor e€s ™—llsD the
™orresponding hƒ€ pro™essor will tr—nsition ˜etween — set of
preEde(ned st—tesF
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 21 / 41
23. The DSP/BIOS Bridge
GPP Side interface
Node
…sed to m—nipul—te node o˜je™tsD whi™h represent ™ontrol —nd sign—l
pro™essing elements running on — p—rti™ul—r hƒ€
Stream
…sed to m—nipul—te stre—m o˜je™tsD whi™h represent logi™—l ™h—nnels for
stre—ming d—t— ˜etween the q€€ —nd nodes on — p—rti™ul—r hƒ€
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 22 / 41
24. The DSP/BIOS Bridge
Sequence for nodes controlling
Load the device driver
root@beagleboard:~# lsmod
Module Size Used by
dspbridge 729 0
bridgedriver 187569 1
Load a base image to the DSP
~# cat /etc/modprobe.d/bridgedriver.conf
options bridgedriver base_img=/lib/dsp/baseimage.dof
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 23 / 41
25. The DSP/BIOS Bridge
Sequence for nodes controlling
Open a handle to the DSP/BIOS Bridge device
dsp •h— ndle a dsp•open @ A Y
i f @ dsp •h—n dle ` H A {
p r • e r r @ 4 f — i l e d t o open hƒ€4 A Y
r e t u r n − IY
}
Reserve GPP-side resources for controlling a particular DSP
i f @ 3 d s p • — t t — ™ h @ dsp•h—ndle D H D x…vv D 8p r o ™ A A {
p r • e r r @ 4 dsp — t t — ™ h f — i l e d 4 A Y
r e t a − IY
goto l e — v e Y
}
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 24 / 41
26. The DSP/BIOS Bridge
Sequence for nodes controlling
Allocate DSP node for the selected processor
const dsp•uuid•t u u i d a
{ H xIP—Q™Q™I D H xdHIS D H xIIdR D H x W f D H xTW D
{ H xHH D H x™H D H x R f D H xQ— D H xSW D H x — e } } Y
i f @ 3 d s p • n o d e • — l l o ™ — t e @ dsp•h—ndle D p r o™ D 8u u i d D
x…vv D x…vv D 8node A A {
p r • e r r @ 4 dsp node — l l o ™ — t e f — i l e d 4 A Y
r e t u r n x…vv Y
}
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 25 / 41
27. The DSP/BIOS Bridge
Sequence for nodes controlling
Create the node on the DSP
i f @ 3 dsp•node•™re—te @ dsp•h—ndle D node A A {
p r • e r r @ 4 dsp node ™ r e — t e f — i l e d 4 A Y
r e t u r n x…vv Y
}
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 26 / 41
28. The DSP/BIOS Bridge
Sequence for nodes controlling
Launch the task node into their execute phase
i f @ 3 dsp•node•run @ dsp•h—ndle D node A A {
p r • e r r @ 4 dsp node r u n f — i l e d 4 A Y
return f — l s e Y
}
yn™e the t—sk is runningD the q€€ ™lient ™—n stre—m d—t— ˜u'ers
toGfrom the t—sk —s well —s ex™h—nge short mess—ges with the t—sk
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 27 / 41
29. The DSP/BIOS Bridge
Sequence for nodes controlling
Stream data to/from DSP tasks
„he q€€ ™lient then —llo™—tes d—t— ˜u'ers for the stre—m
If the buer are already pre-allocated, the GPP client can prepare the
buers for the stream
yn™e —llo™—ted —nd prep—red
They can be used to submit buers to a stream
Submitting a data buer to a stream will not block GPP thread
execution.
They can request a buer back from a stream
Requesting a buer back from the stream may cause the GPP thread
to block
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 28 / 41
30. The DSP/BIOS Bridge
Sequence for nodes controlling
Exchange messages with DSP nodes
i f @ 3 dsp•send•mess—ge @ dsp•h—ndle D node D I D H D H A A {
p r • e r r @ 4 dsp node p u t mess—ge f — i l e d 4 A Y
continue Y
}
i f @ dsp•node•get•mess—ge @ dsp•h—ndle D node D8msg D H A A
p r i n t f @ 4 € i n g X s d 7d wsg 7d wem 7d’n4 D
msg F ™md D msg F —rg•I D msg F —rg•P A Y
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 29 / 41
31. The DSP/BIOS Bridge
Sequence for nodes controlling
Terminate DSP nodes
i f @ 3 dsp•node•termin—te @ dsp•h—ndle D node D
8e x i t • s t — t u s A A {
p r • e r r @ 4 dsp node t e r m i n — t e f — i l e d X 7l x 4 D
exit•st—tus AY
return f — l s e Y
}
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 30 / 41
32. The DSP/BIOS Bridge
Sequence for nodes controlling
Delete DSP nodes
i f @ 3 dsp•node•free @ dsp•h—ndle D node A A {
p r • e r r @ 4 dsp node f r e e f — i l e d 4 A Y
return f — l s e Y
}
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 31 / 41
33. The ingredients
The kernel
DSP/BIOS Bridge driver is not in Linus' branch yet
Neither in linux-omap's main branch
httpXGGgitFkernelForgGcpalinuxGkernelGgitGtmlindGlinuxEom—pE
PFTFgitY—ashortlogYharefsGhe—dsGdsp˜ridge
httpXGGdevFom—pzoomForgGcpatidsp˜ridgeGkernelE
dsp˜ridgeFgitY—ashortlogYharefsGhe—dsGdsp˜ridge
httpXGGgitoriousForgG£
felipe™GlinuxEom—pGfelipe™
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 32 / 41
34. The ingredients
The GPP libraries
TI dbapi
httpXGGdevFom—pzoomForgGcpatidsp˜ridgeGusersp—™eE
dsp˜ridgeFgitY—asumm—ry
dsp_bridge
httpXGGgithu˜F™omGfelipe™GgstEdsp
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 33 / 41
35. The ingredients
Applications
Samples
httpXGGgithu˜F™omGfelipe™GdspEdummy
httpXGGgitoriousForgGvj—quezE˜e—gle˜o—rdGdspEs—mples
Applications
httpXGGm—emoFgitoriousForgGm—emoEmultimedi—GdspEtools
httpXGGgithu˜F™omGfelipe™GgstEdsp
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 34 / 41
36. The ingredients
Socket Nodes
Samples
httpXGGdevFom—pzoomForgGcpatidsp˜ridgeGusersp—™eE
dsp˜ridgeFgitY—asumm—ry
Multimedia
€—rt of ypenweˆ
httpsXGGgforgeFtiF™omGgfGproje™tGopenm—xGfrsG
httpXGG™odeFentropyw—veF™omGgitcpaleonor—FgitY—atree
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 35 / 41
37. The ingredients
C64x+ toolchain
Free as beer
Compiler
httpsXGGwwwE
—FtiF™omGdownlo—dsGsds•supportG„sgodegener—tion„oolsGdownlo—dFhtm
DSP/BIOS (libraries)
httpXGGsoftw—reE
dlFtiF™omGdspsGdsps•registered•swGsdo•s˜Gt—rget™ontentG˜iosGindexFhtm
dobuild tools
€—rt of the usersp—™eEdsp˜ridge p—™k—ge
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 36 / 41
38. The ingredients
All together
Marmita
yi re™ipes overl—y
st is — work in progress
ynly tested in the fe—gle˜o—rd @rev fTA
winim—l im—ge @IHw˜A
httpXGGgitoriousForgGvj—quezE˜e—gle˜o—rdGm—rmit—
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 37 / 41
39. The ingredients
Marmita
It's based on Angstrom distribution
Provides recipes for
felipe™9s kernel PFTFQP
DSS2
dspbridge
gstEdsp
dspEtools
dspEs—mples
li˜˜ridge @dsp˜ridge e€sA
li˜omxEti
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 38 / 41
40. Future
OMAP4
DSP/BIOS Bridge will be deprecated :(
syslink is the new thing
ARM M3 1GHz dual core (Ducati)
DSP TMS320C64x (Tesla)
ARM A9 1GHz dual core
http://dev.omapzoom.org/?p=tisyslink/kernel-syslink.git;a=summary
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 39 / 41
41. Future
The trend
More cores
More processing units
More heterogeneity
MORE COMPLEXITY
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 40 / 41
42. Future
Thank you
Questions?
Víctor Manuel Jáquez Leal (Igalia) The DSP/BIOS Bridge 06 February 2010 41 / 41