This document is the solutions manual for the 5th edition of the textbook "Digital Design with an Introduction to the Verilog HDL" by M. Morris Mano and Michael D. Ciletti. It contains the authors' solutions to the problems in each chapter of the textbook. The manual is copyrighted in 2012.
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Collaborators and co editors: Charlie Sims and Connor Healey.
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1.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
1
SOLUTIONS MANUAL
DIGITAL
DESIGN
WITH
AN
INTRODUCTION
TO
THE
VERILOG
HDL
Fifth
Edition
M.
MORRIS
MANO
Professor
Emeritus
California
State
University,
Los
Angeles
MICHAEL
D.
CILETTI
Professor
Emeritus
University
of
Colorado,
Colorado
Springs
rev
02/14/2012
7.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
7
1.26 6,248 9s Comp: 3,751
2421 code: 0011_0111_0101_0001
1s comp c: 1001_1101_1011_0001 (2421 code alternative #1)
6,2482421 0110_0010_0100_1110 (2421 code alternative #2)
1s comp c 1001_1101_1011_0001 Match
8.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
8
1.27 For a deck with 52 cards, we need 6 bits (25
= 32 < 52 < 64 = 26
). Let the msb's select the suit (e.g.,
diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits
select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack,
queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are
used.)
1.28 G (dot) (space) B o o l e
11000111_11101111_01101000_01101110_00100000_11000100_11101111_11100101
1.29 Steve Jobs
1.30 73 F4 E5 76 E5 4A EF 62 73
73: 0_111_0011 s
F4: 1_111_0100 t
E5: 1_110_0101 e
76: 0_111_0110 v
E5: 1_110_0101 e
4A: 0_100_1010 j
EF: 1_110_1111 o
62: 0_110_0010 b
73: 0_111_0011 s
1.31 62 + 32 = 94 printing characters
1.32 bit 6 from the right
1.33 (a) 897 (b) 564 (c) 871 (d) 2,199
1.34 ASCII for decimal digits with even parity:
(0):
00110000
(1):
10110001
(2):
10110010
(3):
00110011
(4):
10110100
(5):
00110101
(6):
00110110
(7):
10110111
(8):
10111000
(9):
00111001
1.35 (a)
a b c
f
g
a
b
c
f
g
1.36
a b
f
g
a
b
f
g
10.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
10
(b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y)
(c) (x + y)'(x' + y') = x'y'(x' + y') = x'y'
(d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y)
(e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0
(f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c')
= c' + b'c' + a'b' = c' + a'b'
2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C'
(b) (x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz =[ (x + y)z' + z] + xy + wz =
= (z + z')(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z
(c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD)
= B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B
(d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D)
= AA' + A'B + A'C'D = A'(B + C'D)
(e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD
2.5 (a)
x y
F
Fsimplified
(b)
x y
F
Fsimplified
(c)
11.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
11
x y z
Fsimplified
F
(d)
B
F
Fsimplified
A 0
(e)
x y z
Fsimplified
F
(f)
12.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
12
x y z
F
Fsimplified
2.6 (a)
A B C
F
Fsimplified
(b)
x y z
F
Fsimplified
(c)
x y
F
Fsimplified
13.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
13
(d)
w x y z
Fsimplified
F
(e)
A B C D
Fsimplified = 0
F
(f)
w x y z
Fsimplified
F
2.7 (a)
A B C D
Fsimplified
F
14.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
14
(b)
w x y z
Fsimplified
F
(c)
A B C D
Fsimplified
F
(d)
A B C D
Fsimplified
F
15.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
15
(e)
A B C D
F
Fsimplified
2.8 F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z')
FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0
F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz
2.9 (a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x'y'
(b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')'
=a'c' + a'b + ab'c
(c) F' = [z + z'(v'w + xy)]' = z'[z'(v'w + xy)]' = z'[z'v'w + xyz']'
= z'[(z'v'w)'(xyz')'] = z'[(z + v + w') +( x' + y' + z)]
= z'z + z'v + z'w' + z'x' + z'y' +z' z = z'(v + w' + x' + y')
2.10 (a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i)
(b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j
2.11 (a) F(x, y, z) = Σ(1, 4, 5, 6, 7)
(b) F(a, b, c) = Σ(0, 2, 3, 7)
x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F
0
1
0
0
1
1
1
1
F = xy + xy' + y'z
a b c
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F
1
0
1
1
0
0
0
1
F = bc + a'c'
2.12 A = 1011_0001
B = 1010_1100
16.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
16
(a) A AND B = 1010_0000
(b) A OR B = 1011_1101
(c) A XOR B = 0001_1101
(d) NOT A = 0100_1110
(e) NOT B = 0101_0011
2.13 (a)
u x y
Y = [(u + x')(y' + z)]
z
(u + x')
(y' + z)
(b)
u x y
Y = (u xor y)' + x
(u xor y)'
x
(c)
u x y
Y = (u'+ x')(y + z')
z
(u'+ x')
(y + z')
(d)
u x y
Y = u(x xor z) + y'
z
u(x xor z)
y'
(e)
u x y
Y = u + yz +uxy
z
u
yz
uxy
(f)
17.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
17
u x y
Y = u + x + x'(u + y')
x'(u + y')
(u + y')
2.14 (a)
x y
F =xy + x'y' + y'z
z
(b)
x y
F = xy + x'y' + y'z
= (x' + y')' + (x + y)' + (y + z')'
z
(c)
x y
F = xy + x'y' + y'z
= [(xy)' (x'y')' (y'z)']'
z
(d)
x y
F = xy + x'y' + y'z
= [(xy)' (x'y')' (y'z)']'
z
18.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
18
(e)
x y
F = xy + x'y' + y'z
= (x' + y')' + (x + y)' + (y + z')'
z
2.15 (a) T1 = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C')
(b) T2 =T1' = A'BC + AB'C' + AB'C + ABC' + ABC
= BC(A' + A) + AB'(C' + C) + AB(C' + C)
= BC + AB' + AB = BC + A(B' + B) = A + BC
(3,5, 6, 7) (0,1, 2, 4)
∑ = Π
T1
= A'B'C' + A'B'C + A'BC'
A'B' A'C'
T1
= A'B' A'C' = A'(B' + C')
T2
= A'BC + AB'C' + AB'C + ABC' + ABC
AC
T2 =AC' + BC + AC = A+ BC
BC
AC'
2.16 (a) F(A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC
= A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC)
= (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC
= B'(C' + C) + B(C' + C) = B' + B = 1
(b) F(x1, x2, x3, ..., xn) = Σmi has 2n
/2 minterms with x1 and 2n
/2 minterms with x'1, which can be factored
and removed as in (a). The remaining 2n-1
product terms will have 2n-1
/2 minterms with x2 and 2n-1
/2
minterms with x'2, which and be factored to remove x2 and x'2. continue this process until the last term is
left and xn + x'n = 1. Alternatively, by induction, F can be written as F = xnG + x'nG with G = 1. So F =
(xn + x'n)G = 1.
23.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
23
(b) (A + B)(C + D)(A' + B + D)
A B C
F
D
(c) (AB + A'B')(CD' + C'D)
B C D
F
A
(d) A + CD + (A + D')(C' + D)
B C D
F
A
2.24 x ⊕ y = x'y + xy' and (x ⊕ y)' = (x + y')(x' + y)
Dual of x'y + xy' = (x' + y)(x + y') = (x ⊕ y)'
2.25 (a) x| y = xy' ≠ y | x = x'y Not commutative
(x | y) | z = xy'z' ≠ x | (y | z) = x(yz')' = xy' + xz Not associative
24.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
24
(b) (x ⊕ y) = xy' + x'y = y ⊕ x = yx' + y'x Commutative
(x ⊕ y) ⊕ z = ∑(1, 2, 4, 7) = x ⊕ (y ⊕ z) Associative
2.26
x y z
L L H
L H H
H L H
H H L
Gate
NAND
(Positive logic)
x y z
0 0 1
0 1 1
1 0 1
1 1 0
NOR
(Negative logic)
x y z
1 1 0
1 0 0
0 1 0
0 0 1
x y z
L L H
L H L
H L L
H H L
Gate
NOR
(Positive logic)
x y z
0 0 1
0 1 0
1 0 0
1 1 0
NAND
(Negative logic)
x y z
1 1 0
1 0 1
0 1 1
0 0 1
2.27 f1 = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c'
f2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c'
a'
b
c'
a'
b
c
a'
b
c
a
b
c
f1
a'
b'
c
a'
b
c
a
b'
c
f2
a'
b'
a'
b
c
a'
b
c'
a
b'
c'
f1
b'
a
b'
c'
f2
a'
c'
a'
b
c
27.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
27
Chapter 3
3.1
F = xy' + x'z'
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1 m3
1
m2
1
m4
1
m5 m7 m6
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1 m3
1
m2
1
m4
1
m5 m7
1
m6
z
0
1
00 01 11 10
y
x
yz
x
1
m0
1
m1
1
m3
1
m2
m4
1
m5 m7 m6
0
1
00 01 11 10
z
y
x
yz
x
m0
1
m1
1
m3
1
m2
m4 m5
1
m7 m6
F = z' + xy'
F = x' + y'z F = x'z + yz + x'y
3.2
z
(a) F = x'y' + xz (b) F = y + x'z
0
1
00 01 11 10
y
x
yz
x
m0
1
m1
1
m3
1
m2
m4
m5
1
m7
1
m6
0
1
00 01 11 10
z
y
x
yz
x
1
m0
1
m1 m3 m2
m4
1
m5
1
m7
m6
F = xy' + x'y F = y + z
0
1
00 01 11 10
z
y
x
yz
x
m0
1
m1
1
m3
1
m2
m4
1
m5
1
m7
1
m6
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3
1
m2
1
m4
1
m5 m7 m6
(c) (d)
28.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
28
F = z' F = x + y z
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1 m3
1
m2
1
m4 m5 m7
1
m6
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3 m2
1
m4
1
m5
1
m7
1
m6
(e) (f)
3.3
(a) F =xy + x'y'z' + x'yz'
F = xy + x' z'
(b) F = x'y' + yz + x'yz'
F = x' + yz
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1 m3
1
m2
m4
m5
1
m7
1
m6
z
0
1
00 01 11 10
y
x
yz
x
1
m0
1
m1
1
m3
1
m2
m4
m5
1
m7
m6
F = x'y + yz' + y'z'
F = = x' y + z'
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1
1
m3
1
m2
1
m4 m5 m7
1
m6
F = x'yz + xy'z' + xy'z
F = x'yz + xy'
0
1
00 01 11 10
z
x
yz
x
m0 m1
1
m3 m2
1
m4
1
m5 m7 m6
(c) (d)
29.
Digital
Design
With
An
Introduction
to
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Verilog
HDL
–
Solution
Manual.
M.
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Copyright
2012,
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rights
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29
3.4
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1 m3 m2
1
m4 m5
1
m7
1
m6
m12 m13
1
m15 m14
m8 m9 m11 m10
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3
1
m2
m4
m5
1
m7
1
m6
(a) F = y (b) F = BCD + A' BD'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3 m2
m4 m5
1
m7 m6
m12
1
m13
1
m15
1
m14
m8 m9
1
m11 m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0 m1
1
m3
1
m2
m4 m5 m7 m6
1
m12
1
m13
1
m15
1
m14
m8 m9 m11 m10
(d) F = w'x'y +wx
(c) F =CD + ABD + ABC
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0 m1 m3 m2
m4 m5 m7 m6
1
m12
1
m13
1
m15 m14
m8 m9
1
m11 m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0 m1 m3 m2
m4 m5 m7 m6
1
m12
1
m13 m15
1
m14
1
m8 m9 m11
1
m10
F = wz' + xy'w
F = wx + wyz
(e)
(f)
30.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
30
3.5
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0
1
m1 m3 m2
1
m4
1
m5 m7
1
m6
1
m12 m13
1
m15
1
m14
m8 m9 m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3
1
m2
m4 m5
1
m7
1
m6
1
m12
1
m13 m15
1
m14
m8 m9 m11 m10
(a) F =xz' + w'y'z+ wxy (b) F = AC' + ABC' + ABD'
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0
1
m1
1
m3 m2
1
m4
1
m5
1
m7
1
m6
m12
1
m13
1
m15 m14
m8
1
m9
1
m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3
1
m2
1
m4
1
m5
1
m7
1
m6
m12
1
m13
1
m15 m14
m8 m9 m11
1
m10
(c) F = z + xw' (d) F =BD + A'B + B' D'
or = BD + B'D' + A'D'
3.6
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3
1
m2
m4
1
m5
1
m7 m6
1
m12
1
m13 m15 m14
1
m8 m9 m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0
1
m1
1
m3 m2
1
m4
1
m5 m7 m6
1
m12
1
m13 m15 m14
m8
1
m9
1
m11
1
m10
(a) F = B' D' +A'BD + ABC' (b) F = xy' +x'z + wx'y
31.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
31
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1 m3 m2
1
m4
1
m5 m7 m6
m12 m13
1
m15 m14
m8
1
m9
1
m11
1
m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1 m3 m2
m4
1
m5
1
m7 m6
m12
1
m13 m15 m14
m8
1
m9 m11 m10
(c) F = A'BC' + B'C'D + ACD + AB'C
(d) F = C'D + A'BD + A'B'C'
3.7
1
1
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1 m3 m2
m4 m5
1
m7
1
m6
1
m12
1
m13 m15
1
m14
1
m8
1
m9 m11
1
m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
m4
1
m5
1
m7 m6
m12 m13
1
m15
1
m14
1
m8 m9
1
m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0 m1 m3 m2
1
m4
1
m5
1
m7
1
m6
m12
1
m13
1
m15 m14
m8 m9 m11 m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0
1
m1
1
m3
1
m2
m4
1
m5
1
m7 m6
m12
1
m13
1
m15 m14
m8 m9
1
m11
1
m10
(a) F = z + x'y (b) F = AD' + C'D + BCD'
(c) F = B'D' + AC + A'BD + CD (or B'C) (d) F = xw' + xz + xy
32.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
32
3.8
(a) F(x, y, z) = Σ(3, 5, 6, 7)
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3 m2
m4
1
m5
1
m7
1
m6
(b) F = Σ(1, 3, 5, 9, 12, 13, 14)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1
1
m3 m2
m4
1
m5 m7 m6
1
m12
1
m13 m15
1
m14
m8
1
m9 m11 m10
(c) F = Σ(0, 1, 2, 3, 11, 12, 14, 15)
00
01
11
10
00 01 11 10
x
y
wx
w
z
1
m0
1
m1
1
m3
1
m2
m4 m5 m7 m6
1
m12
m13
1
m15
1
m14
m8
m9
1
m11
m10
33.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
33
(d) F = Σ(3, 4, 5, 7, 11, 12)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3 m2
1
m4
1
m5
1
m7 m6
1
m12 m13 m15 m14
m8 m9
1
m11 m10
3.9
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0 m1 m3
1
m2
1
m4
1
m5
1
m7
1
m6
m12
1
m13
1
m15 m14
1
m8 m9 m11
1
m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
m4
1
m5
1
m7 m6
m12 m13
1
m15
1
m14
1
m8 m9
1
m11
1
m10
(a) (b)
Essential: xz, x'z' Essential: B'D', AC, A'BD
Non-essential: w'x, w'z' Non-essential: CD, B'C
F = xz + x'z' + (w'x or w'z') F = B'D' + AC + A'BD + (CD OR B'C)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3
1
m2
1
m4
1
m5
1
m7
1
m6
1
m12
1
m13 m15 m14
m8
1
m9
1
m11 m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0
1
m1
1
m3 m2
m4 m5
1
m7
1
m6
1
m12
1
m13
1
m15
1
m14
1
m8
1
m9 m11 m10
(c) (d)
34.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
34
Essential: BC', AC, A'B'D Essential: wy', xy, w'x'z
Non-Essential: A'B
F = BC' + AC + A'B'D F = wy' + xy + w'x'z
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1 m3
1
m2
m4
1
m5
1
m7 m6
m12
1
m13
1
m15 m14
1
m8
1
m9 m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0
1
m1 m3
1
m2
m4
1
m5
1
m7 m6
m12 m13
1
m15 m14
1
m8 m9 m11
1
m10
Essential: BD, B'C', C'D Essential: x'z', w'y'z, xyz
F = BD + B'C' + C'D F = x'z' + w'y'z + xyz
3.10
1
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
m4
1
m5
1
m7 m6
m12 m13
1
m15
1
m14
1
m8 m9
1
m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0 m1 m3
1
m2
m4
1
m5
1
m7 m6
1
m12
1
m13
1
m15
1
m14
1
m8 m9 m11 m10
F = Σ(0, 2, 5, 7, 8, 10, 12, 13, 14, 15) F = Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
Essential: xz, wx, x'z' Essential: AC, B'D', CD, A'BD
F = xz + wx + x'z' F = AC + B'D' + CD + A'BD
(a)
(b)
35.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
35
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1
1
m3 m2
1
m4
1
m5 m7 m6
1
m12
1
m13
1
m15
1
m14
m8 m9
1
m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0
1
m1 m3 m2
1
m4
1
m5
1
m7
1
m6
m12 m13
1
m15
1
m14
m8
1
m9
1
m11 m10
F = Σ(1, 3, 4, 5, 10, 11, 12, 13, 14, 15) F = Σ(0, 1, 4, 5, 6, 7, 9, 11, 14, 15)
Essential: AC, BC', A'B'D Essential: w'y', xy, wx'z
Non-essential: AB, Aʹ′Bʹ′D, Bʹ′CD, Aʹ′Cʹ′D Non-essential: wx, x'y'z, w'wz, w'x'z
F = AC + BCʹ′ + Aʹ′Bʹ′D F = w'y' + xy + wx'z
(c)
(d)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
1
m3 m2
m4 m5
1
m7 m6
m12
1
m13
1
m15 m14
1
m8
1
m9 m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0
1
m1 m3
1
m2
1
m4
1
m5
1
m7
1
m6
m12 m13
1
m15 m14
m8 m9 m11
1
m10
F(A, B, C, D) = S(0, 1, 3, 7 8, 9, 10,13,15) F = S(0, 1, 2, 4, 5, 6, 7, 10, 15)
Essential: B'C', AB'D' Essential: w'y', w'z', xyz, x'yz'
Non-essential: ABD, A'CD, BCD Non-Essential: w'x
F = B'C' + AB'D' +A'CD +ABD F = w'y' + w'z' + xyz + x'yz'
(e) (f)
36.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
36
3.11
(a)
F(w,
x,
y,
z)
=
∑
(0,
1,
2,
5,
8,
10,
13)
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0
1
m1 m3
1
m2
m4
1
m5 m7 m6
m12
1
m13 m15 m14
1
m8 m9 m11
1
m10
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
m0 m1
1
m3 m2
1
m4 m5
1
m7
1
m6
1
m12 m13
1
m15
1
m14
m8
1
m9
1
m11 m10
F
=
x'z'
+
w'x'y'
+
xy'z
F'
=
yz
+
xy
+
xz'
+
wx'z
F
=
(y'
+
z')(x'
+
y')(x'
+
z)(w'
+x
+
z')
37.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
37
3.12 (a)
F = Π(1, 3, 5, 7, 13, 15)
F' = A'D + B'D
F = (A + Dʹ′)(Bʹ′ + Dʹ′)
F = C'D' + AB' + CD'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
0
m1
0
m3 m2
m4
0
m5
0
m7 m6
m12
0
m13
0
m15 m14
m8 m9 m11 m10
(b)
F = Π(1, 3, 6, 9, 11, 12, 14)
F' = B'D + BCD' + ABD'
F = (B + D')(B' + C' + D)(A' + B' + D)
F = BD + B'D' + A'C'D'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
0
m1
0
m3 m2
m4 m5 m7
0
m6
0
m12 m13 m15
0
m14
m8
0
m9
0
m11 m10
38.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
38
3.13
(a) F = x'z' + y'z' + yz' + xy = x'z' + z' + xy = z' + xy
0
1
00 01 11 10
z
y
x
yz
x
1
m0 m1 m3
1
m2
1
m4 m5
1
m7
1
m6
F' = x'z + y'z
F = (x + z')(y + z')
(b) F = ACD' + C'D + AB' + ABCD
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1 m3 m2
m4
1
m5 m7 m6
m12
1
m13
1
m15
1
m14
1
m8
1
m9
1
m11
1
m10
F = AC + AB' + C'D
F' = A'C + A'D' + BC'D'
F = (A + C')(A + D)(B'+C + D)
39.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
39
(c)
F = (A' + B + D')(A' + B' + C')(A' + B' + C)(B' + C + D')
F' = AB'D + ABC + ABC' + BC'D
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
0
m1
0
m3 m2
m4
0
m5 m7 m6
0
m12
0
m13
0
m15
0
m14
m8 m9 m11 m10
F' = AB + BC'D
F = (A' + B')(B' + C + D')
F = A'D' + A'BC + AB'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
0
m1
0
m3
1
m2
1
m4
0
m5
1
m7
1
m6
0
m12
0
m13
0
m15
0
m14
1
m8
1
m9
1
m11
1
m10
40.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
40
(d)
F = BCD' + ABC' + ACD
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1 m3 m2
m4 m5 m7
1
m6
1
m12
1
m13
1
m15 m14
m8 m9
1
m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
0
m0
0
m1
0
m3
0
m2
0
m4
0
m5
0
m7 m6
m12 m13 m15
0
m14
0
m8
0
m9 m11
0
m10
F' = A'C' + A'D + B'C' + A'B' + ACD'
F = (A + C)(A + D') (B + C)(A + B)(A' +C' + D)
3.14
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1 m3 m2
m4
1
m5 m7 m6
m12 m13 m15
1
m14
m8 m9
1
m11
1
m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
0
m3
0
m2
0
m4 m5
0
m7
0
m6
0
m12
0
m13
0
m15 m14
0
m8
0
m9 m11 m10
SOP form (using 1s): F = A'BC'D + AB'CD + A'B'C' + ACD'
F = A'B'C' + A'C'D + AB'C + ACD'
POS form (using 0s): F' = AC' + A'C + A'C'D' + ABD
F = (A' + C)(A + C')(A + C + D)(A' + B' + D')
Alternative POS: F' = AC' + A'C + A'C'D' + BCD
F = (A' + C)(A + C')(A + C + D)(B' + C' + D')
41.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
41
3.15
0
1
00 01 11 10
z
y
x
yz
x
1
m0
1
m1
x
m3
x
m2
1
m4
1
m5
x
m7
1
m6
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3
x
m2
x
m4 m5 m7
1
m6
m12
1
m13 m15
1
m14
1
m8 m9 m11
x
m10
F = 1 F = A'D' + B'D' + BCD' + ABC'D
F = Σ(0,1, 2, 3, 4, 5, 6, 7) F = Σ(0, 2, 4, 6, 8, 10, 13, 14)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
x
m3 m2
m4
1
m5
1
m7
1
m6
1
m12 m13
1
m15
1
m14
m8
x
m9
x
m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
x
m0 m1 m3
1
m2
1
m4 m5
1
m7
x
m6
1
m12 m13 m15 m14
x
m8 m9 m11
1
m10
F = BC + CD + ABD' + A'BD F = B'D' + C'D' + A'BC
F = Σ(3, 5, 6, 7, 11, 12, 14, 15) F = F = Σ(0, 2, 4, 6, 7, 8, 10, 12)
3.16 (a)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
1
m4 m5
1
m7
1
m6
1
m12 m13
1
m15
1
m14
1
m8 m9
1
m11
1
m10
F = C + D'
F = (C'D)'
D'
C
F
42.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
42
(b)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1
1
m3 m2
m4 m5
1
m7 m6
m12
1
m13
1
m15 m14
m8
1
m9
1
m11 m10
F = AD + B'D + CD
F = ((AD)' (B'D)' (CD)')'
B'
C
F
A
D
D
D
(c) F = (A' + C' + D')(A' + C')(C' + D')
F' = (A' + C' + D')' + (A' + C')' + (C' + D')'
F' = ACD + AC + CD
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
0
m3
1
m2
1
m4
1
m5
0
m7
1
m6
1
m12
1
m13
0
m15
0
m14
1
m8
1
m9
0
m11
0
m10
F = C' + A'D'
F = (C(A + D))'
F = (C(A'D')')'
A'
F
C
D'
(d)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
1
m3
1
m2
1
m4
1
m5
1
m7
1
m6
1
m12
1
m13
1
m15
1
m14
1
m8 m9 m11
1
m10
F = A' + B + D'
F = (A(B')D)'
B' F
A
D
43.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
43
3.17
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
1
m3
1
m2
m4 m5 m7
1
m6
m12 m13 m15
1
m14
m8 m9
1
m11
1
m10
F = A'B' + B'C + CD'
F = ((A + B)(B + C') (C' + D))'
F = ((A'B')'(B'C)'(CD')' )'
F' = (A'B')'(B'C)'(CD')'
C F'
A'
B'
B'
C
D'
3.18 F = (A ⊕ B)'(C ⊕ D) = (AB' + A'B)'(CD' + C'D)
= (AB + A'B')(CD' + C'D) = ABCD' + ABC'D + A'B'CD' + A'B'C'D
F' = (AB + A'B')' + (CD' + C'D)'
F' = ( (A' + B')' + (A + B)' )' + ( (C' + D)' + (C + D')' )'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1 m3
1
m2
m4 m5 m7 m6
m12
1
m13 m15
1
m14
m8 m9 m11 m10
A'
B'
A
B
C'
D
C
D'
F'
44.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
reserved.
44
3.19
(a) F = (w + zʹ′)(xʹ′ + zʹ′)(wʹ′ + xʹ′ + yʹ′)
1
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0 m1 m3
1
m2
1
m4 m5 m7
1
m6
1
m12 m13 m15 m14
1
m8
1
m9
1
m11 m10
y
z
w
x
w
z
F
F = y'z' + wx' + w'z'
F =[(y + z)' + (w' + x)' + (w + z)']
F' =[(y + z)' + (w' + x)' + (w + z)']'
(b)
00
01
11
10
00 01 11 10
x
y
wx
yz
w
z
1
m0 m1
1
m3 m2
m4 m5 m7 m6
1
m12 m13
1
m15 m14
m8 m9 m11 m10
y
z'
y'
z
w
x'
w'
x
F'
F = Σ(0, 3, 12, 15)
F' =y'z+yz' + w'x + wx' = [(y + z')(w + x')(w + x')(w' + x)]'
F = (y + z')' + (y' + z)' + (w + x')' + (w' + x)'
(c) F = [(x + y)(x' + z)]' = (x + y)' + (x' + z)'
F' = [(x + y)' + (x' + z)']'
x
y
x'
z
F'
45.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
45
3.20 Multi-level NOR:
F = ACD(B + C) + (BC' + DE')
F' = [ACD(B + C) + (BC' + DE')]'
F' = [(A' + C' + D')'(B + C) + (B' + C)' + (D' + E)']'
F' = [((A' + C' + D') + (B + C)' )' + (B' + C)' + (D' + E)']'
F' = [(A' + C' + D' + (B + C)')' + (B' + C)' + (D' + E)']'
C'
A'
B'
C
D'
B
D'
E
C
F'
Multi-level NAND:
F = CD(B + C)A + (BC' + DE')
F' = [CD(B + C)A]' [BC' + DE']'
F' = [CD(B'C')'A]' [BC' + DE']'
F' = [CD(B'C')'A]' [[ (BC')' (DE')]' ]'
A
B
C
B'
C'
D
E'
C'
D F
3.21 F = w(x + y + z) + xyz
F' = [w(x + y + z)]'[xyz]' = [w(x'y'z')')]'(xyz)'
x'
w
F
y'
z'
x
y
z
46.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
46
3.22
D
C
B
A
w
x
y
z
D
C
B
A
w
x
y
z
47.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
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47
3.23
00
01
11
00 01 11 10
B
C
AB
CD
A
D
x
m0
x
m1 m3
1
m2
1
m4
x
m5 m7 m6
1
m12 m13 m15
1
m14
x
m8 m9 m11
1
m10
10
A
D
F
B'
C'
F = B'D' + AD' + C'D'
F' = D + A'BC
F = [D + A'BC]' = [D + (A + B' + C')']'
3.24 F(A, B, C, D) = S(0, 4, 8, 9, 10, 11, 12, 14)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3 m2
1
m4 m5 m7 m6
1
m12 m13 m15
1
m14
1
m8
1
m9
1
m11
1
m10
(a) F = C'D' + AB' + AD'
F' = (C'D')'(AB')'(AD')'
AND-NAND:
C'
D'
A
B'
A
D'
F
(b) F' = [C'D' + AB' + AD']'
AND-NOR:
48.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
48
C'
D'
A
B'
A
D'
F’
(c) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)'
F' = (C'D')'(AB')'(AD')' = (C + D)(A' + B)(A' + D)
F = [ (C + D)(A' + B)(A' + D) ]'
OR-NAND:
C
D
A'
B
A'
D
F
(d) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)'
NOR-OR:
C
D
A'
B
A'
D
F
3.25
A
B
C
D
ABCD
AND-AND AND
A
B
C
D
A + B + C + D
OR-OR OR
A
B
C
D
(AB CD)'
AND-NAND NAND
A
B
C
D
(A + B + C + D)'
OR-NOR NOR
A
B
C
D
(A'B'C'D')'
NOR-NAND OR
A
B
C
D
[(AB)' + (C' D')]'
NAND-NOR AND
ABCD
A + B + C + D
49.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
reserved.
49
A
B
C
D
A'B'C'D'
NOR-AND NOR
A
B
C
D
NAND-OR NAND
(A + B + C + D)'
A'B'
C'D'
A' + B' + C' + D'
(A + B + C + D)'
The degenerate forms use 2-input gates to implement the functionality of 4-input gates.
3.26
00
01
11
10
00 01 11 10
b
c
ab
cd
a
d
m0
1
m1
m3
1
m2
m4
1
m5 m7
1
m6
1
m12
1
m13 m15 m14
m8
1
m9 m11
1
m10
00
01
11
10
00 01 11 10
b
c
ab
cd
a
d
1
m0
1
m1
0
m3
1
m2
1
m4
1
m5
1
m7
0
m6
1
m12
0
m13
1
m15
0
m14
1
m8
0
m9
1
m11
1
m10
f = abc' + c'd + a'cd'+ b'cd'
g = (a + b +c' + d')(b' + c' + d)(a'+ c + d')
g' = a'b'cd + bcd' + ac'd
fg = ac'd + abc'd + b'cd'
3.27 x⊕ y = x'y + xy'; Dual = (x' + y)(x + y') = (x⊕ y)'
3.28
x
y
z
P
y
x
z
P
C
(a) 3-bit odd parity generator (b) 4-bit odd parity generator
50.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
50
3.29 D = A ⊕ B ⊕ C
E = A'BC + AB'C = (A ⊕ B)C
F = ABC' + (A' + B')C = ABC' + (AB)'C = (AB) ⊕ C
G = ABC
Half-Adder
S
C
Half-Adder
S
C
Half-Adder
S
C
C
AB
A B
A
B
D = A B C
E = (A B)C
F = (AB) C
G = ABC
3.30 F = AB'CD' + A'BCD' + AB'C'D + A'BC'D
F = (A ⊕ B)CD' + (A ⊕ B) C'D = (A ⊕ B)(C ⊕ D)
B
A
C
D
F
3.31 Note: It is assumed that a complemented input is generated by another circuit that
is not part of the circuit that is to be described.
(a) module Fig_3_20a_gates (F, A, B, C, C_bar, D);
output F;
input A, B, C, C_bar, D;
wire w1, w2, w3, w4;
and (w1, C, D);
or (w2, w1, B);
and (w3, w2, A);
and (w4, B, C_bar);
or (F, w3, w4);
endmodule
(b) module Fig_3_20b_gates (F, A, B, B_Bar, C, C_bar, D);
output F;
input A, B, B_bar, C, C_bar, D;
wire w1, w2, w3, w4;
not (w1_bar, w1);
not (w3_bar, w3);
not (w4_bar, w4);
nand (w1, C, D);
or (w2, w1_bar, B);
nand (w3, w2, A);
nand (w4, B, C_bar);
or (F, w3_bar, w4_bar);
endmodule
51.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
reserved.
51
(c) module Fig_3_21a_gates (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w2, w3, w4;
and (w1, A, B_bar);
and (w2, A_bar, B);
or (w3, w1, w2);
or (w4, C, D_bar);
and (F, w3, w4);
endmodule
(d) module Fig_3_21b_gates (F, A, A_bar, B, B_bar, C_bar, D);
output F;
input A, A_bar, B, B_bar, C_bar, D;
wire w1, w2, w3, w4, F_bar;
nand (w1, A, B_bar);
nand (w2, A_bar, B);
not (w1_bar, w1);
not (w2_bar, w2);
or (w3, w1_bar, w2_bar);
or (w4, w5, w6);
not (w5, C_bar);
not (w6, D);
nand (F_bar, w3, w4);
not (F, F_bar);
endmodule
(e) module Fig_3_24_gates (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar
wire w1, w2, w3, w4, w5, w6, w7, w8, w7_bar, w8_bar;
not (w1_bar, w1);
not (w2_bar, w2);
not (w3, E_bar);
nor (w1, A, B);
nor (W2, C, D);
and (F, w1_bar, w2_bar, w3);
endmodule
(f) module Fig_3_25_gates (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w1_bar, w2, w2_bar;
wire w3, w4, w5, w6, w7, w8;
not (w1, A_bar);
not (w2, B);
not (w3, A);
not (w4, B_bar);
and (w5, w1_bar, w2_bar));
and (w6, w3, w4);
nor (w7, w5, w6);
nor (w8, c, d_bar);
and (F, w7, w8);
endmodule
52.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
reserved.
52
3.32 Note: It is assumed that a complemented input is generated by another circuit that
is not part of the circuit that is to be described.
Note:
Because
the
signals
here
are
all
scalar–valued,
the
logical
operators
(!,
&&,
and
||)
are
equivalent
to
the
bitwise
operators
(~,
&,
|).
If
the
operands
are
vectors
the
bitwise
operators
produce
a
vector
result;
the
logical
operators
would
produce
a
sclara
result
(true
or
false).
(a) module Fig_3_20a_CA (F, A, B, C, C_bar, D);
output F;
input A, B, C, C_bar, D;
wire w1, w2, w3, w4;
assign w1 = C && D;
assign w2 = w1 || B;
assign w3 = !(w2 && A);
assign w4 = !w3;
assign w5 = !(B && C_bar);
assign w5_bar = !w5;
assign F = w4 || w5_bar);
endmodule
(b) module Fig_3_20b_CA (F, A, B, C, C_bar, D);
output F;
input A, B, B_bar, C, C_bar, D;
wire w2 = !w1;
wire w3 = !B_bar;
wire w4, w5, w5_bar, w6, w6_bar;
assign w1 = !(C && D);
assign w4 = w2 || w3;
assign w5 = !(w4 && A);
assign w5_bar = !w5;
assign w6 = !(B && C_bar);
assign w6_bar = !w6;
assign F = w5_bar || w6_bar;
endmodule
(c) module Fig_3_21a_CA (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w2, w3, w4;
assign w1 = A && B_bar;
assign w2 = A_bar && B;
assign w3 = w1 || w2);
assign w4 = C || D_bar;
assign F = w3 || w4;
endmodule
(d) module Fig_3_21b_CA (F, A, A_bar, B, B_bar, C_bar, D);
output F;
input A, A_bar, B, B_bar, C_bar, D;
wire w1, w2, w1_bar, w2_bar, w3, w4, w5, w6, F_bar;
assign w1 = !(A && B_bar);
assign w2 = !(A_bar && B);
assign w1_bar = !w1;
assign w2_bar = !w2;
assign w3 = w1_bar || w2_bar;
assign w4 = !C_bar;
assign w5 = !D;
assign w6 = w4 || w5;
assign F_bar = !(w3 && w6);
assign F = !F_bar;
endmodule
53.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
53
(e) module Fig_3_24_CA (F, A, B, C, D, E_bar);
output F;
input A, B, C, D, E_bar;
wire w1, w2, w1_bar, w2_bar, w3_bar;
assign w1 = !(A || B);
assign w1_bar = !w1;
assign w2 = !(C || D);
assign w2_bar = !w2;
assign w3 = !E_bar;
assign F = w1_bar && w2_bar && w3;
endmodule
(f) module Fig_3_25_CA (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = !A _bar;
assign w2 = !B;
assign w3 = w1 && w2;
assign w4 = !A;
assign w5 = !B_bar;
assign w6 = w4 && w5;
assign w7 = !(C || D_bar);
assign w8 = !(w3 || w6);
assign w9 = !w8;
assign w10 = !w7;
assign F = w9 && w10;
endmodule
3.33 (a)
Initially, with xy = 00, w1 = w2 = 1, w3 = w4 = 0 and F = 0. w1 should change to 0 3ns after xy
changes to 01. w4 should change to 1 6ns after xy changes to 01. F should change from 0 to 1 8ns
after w4 changes from 0 to 1, i.e., 14 ns after xy changes from 00 to 01.
3
8
6
6
3
F = x y
x
y
w1
w2
w3
w4
54.
Digital
Design
With
An
Introduction
to
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HDL
–
Solution
Manual.
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Copyright
2012,
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rights
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54
(b)
`timescale 1ns/1ps
module Prob_3_33 (F, x, y);
wire w1, w2, w3, w4;
and #6 (w3, x, w1);
not #3 (w1, x);
and #6 (w4, y, w1);
not #3 (w2, y);
or #8 (F, w3, w4);
endmodule
module t_Prob_3_33 ();
reg x, y;
wire F;
Prob_3_33 M0 (F, x, y);
initial #200 $finish;
initial fork
x = 0;
y = 0;
#20 y = 1;
join
endmodule
(c) To simulate the circuit, it is assumed that the inputs xy = 00 have been applied sufficiently long for
the circuit to be stable before xy = 01 is applied. The testbench sets xy = 00 at t = 0 ns, and xy = 1 at t =
10 ns. The simulator assumes that xy = 00 has been applied long enough for the circuit to be in a stable
state at t = 0 ns, and shows F = 0 as the value of the output at t = 0. For illustration, the waveforms show
the response to xy = 01 applied at t = 10 ns.
Name
x
w1
y
w2
w3
w4
F
t = 10 ns
t = 16 ns
t = 24 ns
Note: input change occurs at t = 10 ns.
Δ = 14 ns
55.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
55
3.34 module Prob_3_34 (Out_1, Out_2, Out_3, A, B, C, D);
output Out_1, Out_2, Out_3;
input A, B, C, D;
wire A_bar, B_bar, C_bar, D_bar;
assign A_bar = !A;
assign B_Bar = !B;
assign C_bar = !C;
assign D_bar = !D;
assign Out_1 = (A + B_bar) && C_bar && ( C || D);
assign Out_2 = ( (C_bar && D) || (B && C && D) || (C && D_bar) ) && (A_bar || B);
assign Out_3 = (((A && B) || C) && D) || (B_bar && C);
endmodule
3.35
module Exmpl-3(A, B, C, D, F) // Line 1
inputs A, B, C, Output D, F, // Line 2
output B // Line 3
and g1(A, B, B); // Line 4
not (D, B, A), // Line 5
OR (F, B; C); // Line 6
endofmodule; // Line 7
Line 1: Dash not allowed character in identifier; use underscore: Exmpl_3. Terminate line with semicolon
(;).
Line 2: inputs should be input (no s at the end). Change last comma (,) to semicolon (;). Output is
declared but does not appear in the port list, and should be followed by a comma if it is intended to
be in the list of inputs. If Output is a mispelling of output and is to declare output ports, C should
be followed by a semicolon (;) and F should be followed by a semicolon (;).
Line 3: B cannot be declared both as an input (Line 2) and output (Line 3). Terminate the line with a
semicolon (;).
Line 4: A cannot be an output of the primitive if it is an input to the module
Line 5: Too many entries for the not gate (may have only a single input, and a single output). Termiante
the line with a semicolon, not a comma.
Line 6: OR must be in lowercase: change to “or”. Replace semicolon by a comma (B,) in the list of ports.
Line 7: Remove semicolon (no semicolon after endmodule).
56.
Digital
Design
With
An
Introduction
to
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Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
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56
3.36 (a)
B
C
D d
A
a
y
x
z w
F
(b)
A1 A0 B1 B0
w1
w2
w3
F1
w6
w7
F3
w4
w5
F2
(c)
a b
y1
y2
y3
57.
Digital
Design
With
An
Introduction
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Verilog
HDL
–
Solution
Manual.
M.
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2012,
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57
3.37
UDP_Majority_4 (y, a, b, c, d);
output y;
input a, b, c, d;
table
// a b c d : y
0 0 0 0 : 0;
0 0 0 1 : 0;
0 0 1 0 : 0;
0 0 1 1 : 0;
0 1 0 0 : 0;
0 1 0 1 : 0;
0 1 1 0 : 0;
0 1 1 1 : 1;
1 0 0 0 : 0;
1 0 0 1 : 0;
1 0 1 0 : 0;
1 0 1 1 : 0;
1 1 0 0 : 0;
1 1 0 1 : 0;
1 1 1 0 : 1;
1 1 1 1 : 1;
endtable
endprimitive
3.38
module t_Circuit_with_UDP_02467;
wire E, F;
reg A, B, C, D;
Circuit_with_UDP_02467 m0 (E, F, A, B, C, D);
initial #100 $finish;
initial fork
A = 0; B = 0; C = 0; D = 0;
#40 A = 1;
#20 B = 1;
#40 B = 0;
#60 B = 1;
#10 C = 1; #20 C = 0; #30 C = 1; #40 C = 0; #50 C = 1; #60 C = 0; #70 C = 1;
#20 D = 1;
join
endmodule
58.
Digital
Design
With
An
Introduction
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Verilog
HDL
–
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2012,
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58
// Verilog model: User-defined Primitive
primitive UDP_02467 (D, A, B, C);
output D;
input A, B, C;
// Truth table for D = f (A, B, C) = S (0, 2, 4, 6, 7);
table
// A B C : D // Column header comment
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
// Verilog model: Circuit instantiation of Circuit_UDP_02467
module Circuit_with_UDP_02467 (e, f, a, b, c, d);
output e, f;
input a, b, c, d;
UDP_02467 M0 (e, a, b, c);
and (f, e, d); //Option gate instance name omitted
endmodule
A
B
t, ns
t, ns
10 20 30 40 50 60
10 20 30 40 50 60 70 80
70 80
C
t, ns
10 20 30 40 50 60 70 80
D
t, ns
10 20 30 40 50 60 70 80
E
t, ns
10 20 30 40 50 60 70 80
F
t, ns
10 20 30 40 50 60 70 80
59.
Digital
Design
With
An
Introduction
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Verilog
HDL
–
Solution
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Copyright
2012,
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rights
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59
3.39
a b s c
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
s = a'b + ab' = a ^ b
c = ab = a && b
module Prob_3_39 (s, c, a, b);
input a, b;
output s, c;
xor (s, a, b);
and (c, a, b);
endmodule
60.
Digital
Design
With
An
Introduction
to
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HDL
–
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2012,
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60
CHAPTER 4
4.1
(a) T1 = B'C, T2 = A'B, T3 = A + T1 = A + B'C,
T4 = D ⊕ T2 = D ⊕ (A'B) = A'BD' + D(A + B') = A'BD' + AD + B'D
F1 = T3 + T4 = A + B'C + A'BD' + AD + B'D
With A + AD = A and A + A'BD' = A + BD':
F1 = A + B'C + BD' + B'D
Alternative cover: F1 = A + CD' + BD' + B'D
F2 = T2 + D' = A'B + D'
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
T1 T2 T3 T4 F1 F2
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
ABCD
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
00
01
11
10
00 01 11 10
B
C
AB
CD
D
M0
1
M1
1
M3
1
M2
1
M4 M5 M7
1
M6
1
M12
1
M13
1
M15
1
M14
1
M8
1
M9
1
M11
1
M10
F1 = A + CD' + B'D + BD'
A
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
M0 M1 M3
1
M2
1
M4
1
M5
1
M7
1
M6
1
M12 M13 M15
1
M14
1
M8 M9 M11
1
M10
F2 = A'B + D'
00
01
11
10
00 01 11 10
B
C
CD
D
M0
1
M1
1
M3
1
M2
1
M4 M5 M7
1
M6
1
M12
1
M13
1
M15
1
M14
1
M8
1
M9
1
M11
1
M10
F1 = A + B'C+ B'D + BD'
A
61.
Digital
Design
With
An
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Verilog
HDL
–
Solution
Manual.
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M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
61
4.2
A
B
C
D
BC
[(A'D)' A']'= A + D
A'
(A'D)' = A + D’
BC + A'
F
G
F = (A + D)(A' + BC) = A'D + ABC + BCD += A'D + ABC
F = (A + D')(A' +BC) = A'D' + ABC + BCD' = A'D' + ABC
F = A'D + ABC + BCD = A'D + ABC
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3
1
m2
1
m4 m5 m7
1
m6
m12 m13
1
m15
1
m14
m8 m9 m11 m10
G = A'D' + ABC + BCD' = A'D' + ABC
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1
1
m3 m2
m4
1
m5
1
m7 m6
m12 m13
1
m15
1
m14
m8 m9 m11 m10
4.3 (a) Yi = (AiS' + BiS)E' for i = 0, 1, 2, 3
(b) 1024 rows and 14 columns
4.4 (a)
0
1
00 01 11 10
z
y
x
yz
x
1
m0
1
m1 m3
1
m2
m4
m5
m7
m6
x'
y'
y'
x'
F
000
001
010
011
100
101
110
111
xyz
1
1
1
0
0
0
0
0
F
F = x'y' + x'z'
62.
Digital
Design
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HDL
–
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2012,
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62
(b)
0
1
00 01 11 10
z
y
x
yz
x
m0
1
m1
1
m3 m2
m4
1
m5
1
m7
m6
000
001
010
011
100
101
110
111
xyz
0
1
0
0
0
0
0
0
F
F = z
F
z
4.5
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3
1
m2
m4
m5
1
m7
m6
x'
y
z
y
A
000
001
010
011
100
101
110
111
xyz
010
011
100
101
001
010
011
100
A
A = x'y + yz
ABC
0
1
00 01 11 10
z
y
x
yz
x
1
m0
1
m1
m3
m2
m4
1
m5 m7
1
m6
x
y'
z
y'
B
B
B = x'y' + y'z + xyz'
z'
x
y
0
1
00 01 11 10
z
y
x
yz
x
m0
1
m1
1
m3 m2
1
m4
m5
m7
1
m6
C
C
C= x'z + xz'
x
z
63.
Digital
Design
With
An
Introduction
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HDL
–
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Ciletti,
Copyright
2012,
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63
4.6
0
1
00 01 11 10
z
y
x
yz
x
m0 m1
1
m3 m2
m4
1
m5
1
m7
1
m6
x
z
y
x
F
000
001
010
011
100
101
110
111
xyz
0
0
0
1
0
1
1
1
A
F = xz + yz + xy
F
y
z
module Prob_4_6 (output F, input x, y, z);
assign F = (x & z) | (y & z) | (x & y);
endmodule
64.
Digital
Design
With
An
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HDL
–
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2012,
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64
4.7 (a)
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
ABCD wxyz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
m1
m3
m2
m4 m5 m7 m6
1
m12
1
m13
1
m15
1
m14
1
m8
1
m9
1
m11
1
m10
w = A
00
01
11
10
00 01 11 10
B
C
CD
D
m0
m1
m3
m2
1
m4
1
m5
1
m7
1
m6
m12 m13 m15 m14
1
m8
1
m9
1
m11
1
m10
x = AB' + A'B = A B
00
01
11
10
00 01 11 10
B
C
AB
CD
A
m0 m1
1
m3
1
m2
1
m4
1
m5 m7 m6
m12 m13
1
m15
1
m14
1
m8
1
m9
m11
m10
y = A'B'C A'BC' + ABC + AB'C'
= A'(A B) + A(B C)'
= A B C
= X C
D
00
01
11
10
00 01 11 10
B
C
AB
CD
m0
1
m1 m3
1
m2
1
m4 m5
1
m7 m6
m12
1
m13 m15
1
m14
1
m8
m9
1
m11
m10
z = A B C D
= y D
D
A
B
C
D
w
x
y
z
A
A
65.
Digital
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An
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2012,
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65
(b)
module Prob_4_7(output w, x, y, z, input A, B, C, D);
always @ (A, B, C, D)
case ({A, B, C, D})
4'b0000: {w, x, y, z} = 4'b0000;
4'b0001: {w, x, y, z} = 4'b1111;
4'b0010: {w, x, y, z} = 4'b1110;
4'b0011: {w, x, y, z} = 4'b1101;
4'b0100: {w, x, y, z} = 4'b1100;
4'b0101: {w, x, y, z} = 4'b1011;
4'b0110: {w, x, y, z} = 4'b1010;
4'b0111: {w, x, y, z} = 4'b1001;
4'b1000: {w, x, y, z} = 4'b1000;
4'b1001: {w, x, y, z} = 4'b0111;
4'b1010: {w, x, y, z} = 4'b0110;
4'b1011: {w, x, y, z} = 4'b0101;
4'b1100: {w, x, y, z} = 4'b0100;
4'b1101: {w, x, y, z} = 4'b0011;
4'b1110: {w, x, y, z} = 4'b0010;
4'b1111: {w, x, y, z} = 4'b0001;
endcase
endmodule
Alternative
model:
module Prob_4_7(output w, x, y, z, input A, B, C, D);
assign w = A;
assign x = A ^ B);
assign y = x ^ C;
assign z = y ^ D;
endmodule
66.
Digital
Design
With
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Verilog
HDL
–
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Copyright
2012,
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rights
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66
4.8 (a) The 8-4-2-1 code (Table 1.5) and the BCD code (Table 1.4) are identical for digits 0 – 9.
(b)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
8421
ABCD
Gray
wxyz
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1 m3 m2
m4 m5 m7 m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
C
CD
D
m0 m1 m3 m2
1
m4
1
m5
1
m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
w = AB'C'
AB
CD
A
m0 m1
1
m3
1
m2
1
m4
1
m5 m7 m6
m12 m13 m15 m14
m8 m9 m11 m10
D
A
C
x = AB'C' + A'B
00
01
11
10
00 01 11 10
B
AB
CD
A
m0
1
m1 m3
1
m2
m4
1
m5 m7
1
m6
m12
1
m13 m15 m14
m8 m9 m11 m10
D
C
y = A'BD' + A'B'D z = A'C'D + BC'D + A'CD'
67.
Digital
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HDL
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2012,
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67
4.9
1
0
1
1
0
1
1
1
1
1
ABCD a
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
b c d
1
0
1
1
0
1
1
0
1
1
e
1
0
1
0
0
0
1
0
1
0
f
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
g
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
m4
1
m5
1
m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
1
m3
1
m2
1
m4 m5
1
m7 m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
a = A'C + A'BD + B'C'D' + AB'C' b = A'B' + A'C'D' + A'CD + AB'C'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
1
m3 m2
1
m4
1
m5
1
m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1
1
m3
1
m2
m4
1
m5 m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
c = A'B + A'D + B'C'D' + AB'C' d = A'CD' + A'B' C+ B'C'D' + AB'C' + A'BC'D
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3 m2
1
m4
1
m5 m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3
1
m2
1
m4
1
m5 m7
1
m6
m12 m13 m15 m14
1
m8
1
m9 m11 m10
00
01
11
10
00 01 11 10
B
C
AB
CD
A
1
m0 m1 m3
1
m2
m4 m5 m7
1
m6
m12 m13 m15 m14
1
m8 m9 m11 m10
e = A'CD' + B'C'D'
D
f = A'BC' + A'C'D' + A'BD + AB'C' g = A'CD' + A'B'C + A'BC' + AB'C'
68.
Digital
Design
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HDL
–
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2012,
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rights
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68
4.10
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ABCD wxyz
0000
1111
1110
1101
1100
1011
1001
1000
1000
0111
0110
0101
0100
0011
0010
0001
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1
1
m3
1
m2
1
m4
1
m5
1
m7
1
m6
m12 m13 m15 m14
1
m8 m9 m11 m10
w = A'(B + C + D) + AB'C'D'
= A (B + C + D)
00
01
11
10
00 01 11 10
B
C
CD
D
m0
1
m1
1
m3
1
m2
1
m4 m5 m7 m6
1
m12 m13 m15 m14
m8
1
m9
1
m11
1
m10
x = B'(C + D) + CB'D'
= B (C + D)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
m0
1
m1 m3
1
m2
m4
1
m5 m7
1
m6
m12
1
m13 m15
1
m14
m8
1
m9
m11
1
m10
y = CD' + C'D = C D
D
00
01
11
10
00 01 11 10
B
C
AB
CD
m0
1
m1
1
m3 m2
m4
1
m5
1
m7 m6
m12
1
m13
1
m15 m14
m8
1
m9
1
m11
m10
z = D
D
A
A
For a 5-bit 2's complementer with input E and output v:
v = E (A + B + C + D)
69.
Digital
Design
With
An
Introduction
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Verilog
HDL
–
Solution
Manual.
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M.D.
Ciletti,
Copyright
2012,
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69
4.11 (a)
Half Adder
x y
C S
Half Adder
x y
C S
Half Adder
x y
C S
Half Adder
x y
C S
A1 A0
1
A2
A3
Note: 5-bit output
(b)
Full Adder
x y
B D
Full Adder
x y
B D
Full Adder
x y
B D
Half Adder
x y
B D
A1 A0
A2
A3 1 1 1 1
Note: To decrement the 4-bit number, add -1 to the number. In 2's complement format ( add Fh ) to
the number. An attempt to decrement 0 will assert the borrow bit. For waveforms, see solution to
Problem 4.52.
4.12
(a)
0 0
0 1
1 0
1 1
0 0
1 1
0 1
0 0
x y B D
D = x'y + xy'
B = x'y
(b)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
1 1
1 1
1 0
0 1
0 0
0 0
1 1
x y Bin B D
Diff = x y z
Bout = x'y + x'z + yz
70.
Digital
Design
With
An
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HDL
–
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70
4.13 Sum C V
(a) 1101 0 1
(b) 0001 1 1
(c) 0100 1 0
(d) 1011 0 1
(e) 1111 0 0
4.14 xor AND OR XOR
10 + 5 + 5 + 10 = 30 ns
4.15 C4 = G3 + P3C3 = G3 + P3(G2 + P2G1 + P2P1G0 + P2P1P0C0)
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
4.16 (a)
(C'G'i + p'i)' = (Ci + Gi)Pi = GiPi + PiCi
= AiBi(Ai + Bi) + PiCi
= AiBi + PiCi = Gi + PiCi
= AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1
(PiG'i) ⊕ Ci = (Ai + Bi)(AiBi)' ⊕ Ci = (Ai + Bi)(A'i + B'i) ⊕ Ci
= (A'iBi + AiB'i) ⊕ Ci = Ai ⊕ Bi ⊕ Ci = Si
(b)
Output of NOR gate = (A0 + B0)' = P'0
Output of NAND gate = (A0B0)' = G'0
S1 = (P0G'0) ⊕ C0
C1 = (C'0G'0 + P'0)' as defined in part (a)
4.17 (a)
(C'iG'i + P'i)' = (Ci + Gi)Pi = GiPi + PiCi = AiBi(Ai + Bi) + PiCi
= AiBi + PiCi = Gi + PiCi
= AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1
(PiG'i)⊕Ci = (Ai + Bi)(AiBi)'⊕Ci = (Ai + Bi)(A'i + B'i)⊕Ci
= (A'iBi + AiB'i)⊕Ci = Ai⊕Bi⊕Ci = Si
(b)
Output of NOR gate = (A0 + B0)' = P'0
Output of NAND gate = (A0B0)' = G'0
S0 = (P0G'0)⊕C0
C1 = (C'0G'0 + P'0)' as defined in part (a)
71.
Digital
Design
With
An
Introduction
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the
Verilog
HDL
–
Solution
Manual.
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Copyright
2012,
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71
4.18
Inputs
ABCD
Outputs
wxyz
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
d(A, b, c, d) = Σ(10, 11, 12, 13, 14, 15)
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1 m3 m2
m4 m5 m7 m6
x
m12
x
m13
x
m15
x
m14
m8 m9
x
m11
x
m10
w = A'B'C'
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0 m1
1
m3
1
m2
1
m4
1
m5 m7 m6
x
m12
x
m13
x
m15
x
m14
m8 m9
x
m11
x
m10
x = BC' + B'C = B C
00
01
11
10
00 01 11 10
B
C
CD
D
m0 m1
1
m3
1
m2
m4 m5
1
m7
1
m6
x
m12
x
m13
x
m15
x
m14
m8 m9
x
m11
x
m10
y = C
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0 m1 m3
1
m2
1
m4
1
m5 m7
1
m6
x
m12
x
m13
x
m15
x
m14
1
m8 m9
x
m11
x
m10
z = D'
72.
Digital
Design
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An
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HDL
–
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2012,
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72
4.19
9's Complementer
(See Problem 4.18)
Quadruple 2 x 1 MUX
Select = 1 Select = 0
A3 A2 A1 A0
BCD Adder (See Fig. 4.14)
Cin
Select
B3 B2 B1 B0
Mode = 0 FOR Add
Mode = 1 for Subtract
73.
Digital
Design
With
An
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Verilog
HDL
–
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2012,
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73
4.20 Combine the following circuit with the 4-bit binary multiplier circuit of Fig. 4.16.
4-bit Adder
B0
B1
B2
B3
A3
Cout
D7
D6
D5
D4
D3
C6
C5
C4
C3
C2
C1
C0
D2
D1
D0
Augend
4.21
A0
B0
A1
B1
A2
B2
B3
A3
x
x = (A0
B0
)'(A1
B1
)'(A2
B2
)'(A3
B3
)'
4.22
XS-3
ABCD
Binary
wxyz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
74.
Digital
Design
With
An
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HDL
–
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2012,
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74
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
x
m0
x
m1 m3 x
m4 m5 m7 m6
1
m12
x
m13
x
m15
x
m14
m8 m9
1
m11 m10
w = AB + ACD
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
X
m0
X
m1 m3
X
m2
m4 m5
1
m7 m6
m12
x
m13
x
m15
x
m14
1
m8
1
m9 m11
1
m10
x = B'C' + B'D' + BCD
y = C'D + CD'
z = D'
4.23
D0 = A1'A0' = (A1 + A0)' (NOR) D0' = (A1'A0')' (NAND)
D1 = A1'A0 = (A1 + A0')' (NOR) D1' = (A1'A0)' (NAND)
D2 = A1A0' = (A1' + A0)' (NOR) D2' = (A1A0')' (NAND)
D3 = A1A0 = (A1' + A0)' (NOR) D0' = (A1A0)' (NAND)
A1
A0
E
D0 = (A1 + A0 + E' )' = A'1A'0E
D1 = (A1 + A'0 + E' )' = A'1A0E
D2 = (A'1 + A0 + E' ) = A1A'0E
D3 = (A'1 + A'0 + E' )' = A1A0E
A1 A0
E
D0' = (A1 + A0 + E' ) = (A'1A'0E)'
D1' = (A1 + A'0 + E' ) = (A'1A0E)'
D2' = (A1' + A0 + E' ) = (A1A0'E)'
D3' = (A1' + A0' + E' ) = (A1A0E)'
D0
D1
D2
D3
75.
Digital
Design
With
An
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Verilog
HDL
–
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2012,
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rights
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75
4.24
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
D0
m0
D1
m1
D3
m3
D2
x
D4
m4
D5
m5
D7
m7
D6
m6
x
m12
x
m13
x
m15
x
m14
D8
m8
D9
m9
x
m11
x
m10
Inputs: A, B, C, D
Outputs: D0, D1, ... D9
D0 = A'B'C'D' D5 = BC'D
D1 = A'B'C'D D6 = BCD'
D2 = B'CD' D7 = BCD
D3 = B'CD D8 = AD'
D4 = BC'D' D9 = AD
76.
Digital
Design
With
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HDL
–
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2012,
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76
4.25
3 x 8
Decoder
3 x 8
Decoder
3 x 8
Decoder
3 x 8
Decoder
2 x 4
Decoder
A1
A0
A2
A3
A4
20
21
0
1
2
3
E
E
E
E
D24 - D31
D16 - D23
D8 - D15
D0 - D7
8
8
8
8
E
E
4.26
2 x 4
Decoder
2 x 4
Decoder
2 x 4
Decoder
2 x 4
Decoder
2 x 4
Decoder
A0
A1
A2
A3
20
21
0
1
2
3
E
E
E
E
D12 - D15
D8 - D11
D4 - D7
D0 - D3
4
4
4
4
20
21
20
21
20
21
20
21
E
E
77.
Digital
Design
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HDL
–
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77
4.27
0
1
2
3
4
5
6
7
3 x 8
Decoder
F1 = Σ(1, 4, 6)
A
B
C 20
21
22
F3 = Σ(2, 4, 6, 7)
F2 = Σ(3, 5)
4.28 (a)
F1 = x(y + y')z + x'yz' =xyx + xy'z + x'yz' = Σ(2, 5, 7)
F2 = xy'z' + x'y = xy'z' + x'yz + x'yz' = Σ(2, 3, 4)
F3 = x'y'z' + xy(z + z') =x'y'z' + xyz + xyz' = Σ(0, 6, 7)
0
1
2
3
4
5
6
7
3 x 8
Decoder
F1 = Σ((2, 5, 7)
x
y
z 20
21
22
F1 = Σ((2, 3, 4)
F1 = Σ(0, 6, 7)
(b)
78.
Digital
Design
With
An
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HDL
–
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Manual.
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2012,
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rights
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78
4.29
Inputs Outputs
D3 D2 D1 D0 x y V
0 0 0 0 x x 0
x x x 1 0 0 1
x x 1 0 0 1 1
x 1 0 0 1 0 1
1 0 0 0 1 1 1
00
01
11
10
00 01 11 10
D1
D1D0
D3
m0
1
m1
1
m3
1
m2
1
m4
1
m5
1
m7
1
m6
1
m12
1
m13
1
m15
1
m14
1
m8
1
m9
1
m11
1
m10
D2
D0
D3D2
00
01
11
10
00 01 11 10
D1
D1D0
D3
x
m0 m1 m3
1
m2
m4 m5 m7
1
m6
m12 m13 m15
1
m14
1
m8 m9 m11
1
m10
D2
D0
D3D2
V = D0 + D1 + D2 + D3
y = D0'D2' + D1D0'
D0
D1
D2
D3
x
y
V
D2
D1
D0
00
01
11
10
00 01 11 10
D1D0
x
m0 m1 m3 m2
1
m4 m5 m7 m6
1
m12 m13 m15 m14
1
m8 m9 m11 m10
D2
D0
D3D2
x = D1'D0'
79.
Digital
Design
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HDL
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79
4.30
D0
0
1
x
x
x
x
x
x
x
D1
0
0
1
x
x
x
x
x
x
D2
0
0
0
1
x
x
x
x
x
D3
0
0
0
0
1
x
x
x
x
D4
0
0
0
0
0
1
x
x
x
D5
0
0
0
0
0
0
1
x
x
D6
0
0
0
0
0
0
0
1
x
D7
0
0
0
0
0
0
0
0
1
x y z V
x x x 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 0 0 1
1 1 1 1
Inputs Outputs
If D2 = 1, D6 = 1, all others = 0
Output xyz = 100 and V = 1
4.31
8 x 1
MUX
s0
s1
s2
0
1
2
3
4
5
6
7
8 x 1
MUX
s0
s1
s2
0
1
2
3
4
5
6
7
2 x 1
MUX
s
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
s0
s1
s2
s3
y
80.
Digital
Design
With
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HDL
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80
4.32 (a) F = Σ (0, 2, 5, 8, 10, 14)
Inputs
ABCD
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1
101 0
101 1
110 0
110 1
111 0
111 1
F = D'
F = D'
F = D
F = 0
F = D'
F = D'
F = 0
F = D'
8 x 1
MUX
s0
s1
s2
0
1
2
3
4
5
6
7
A
B
C
D
0
Y
F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F = Σ(0, 2, 5, 8, 10, 14)
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Mux
input
line
(ABC)
Value
81.
Digital
Design
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HDL
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81
(b)
Inputs
ABCD
1
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1
101 0
101 1
110 0
110 1
111 0
111 1
F = 1
F = 1
F = D
F = 1
F = D'
F = 1
F = D'
F = 1
8 x 1
MUX
s0
s1
s2
0
1
2
3
4
5
6
7
A
B
C
D
1
Y
F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F = Π(2, 6, 11) = (A' +B' + C + D')(A' +B + C + D')(A +B' + C + D)
F' = (A' +B' + C + D')' + (A' +B + C + D')' + (A +B' + C + D)'
F' = (ABC'D) + (AB'C'D) + (A'BC'D') = Σ(13, 9, 4)
F = Σ(0, 1, 2, 3, 5, 6, 7, 8, 10, 11, 12, 14, 15)
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Mux
input
line
(ABC)
Value
4.33
Dual
4 x 1
MUX
x
0
1
Y
S
0
1
2
3
0
1
2
3
C
S(x, y, z) = Σ(1, 2, 4, 7)
C(x, y, z) = Σ(3, 5, 6, 7)
I0 I1 I2 I3
0 1 2 3
4 5 6 7
x x' x' x
x'
x
I0 I1 I2 I3
0 1 2 3
4 5 6 7
0 x' x' 1
x'
x
S C
y z
82.
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HDL
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82
4.34 (a)
A
0
0
1
1
0
0
1
1
1
1
B
1
1
0
0
0
0
0
0
1
1
C
1
1
1
1
0
0
0
0
0
0
D
0
1
0
1
0
1
0
1
0
1
F
1
1
1
1
0
1
0
1
1
0
I3
= 1
I5 = 1
I0
= D
I4
= D
I6 = D'
Other minterms = 0
since I1
= I2
= I7
= 0
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
m0
1
m1 m3 m2
m4 m5
1
m7
1
m6
1
m12 m13 m15 m14
m8
1
m9
1
m11
1
m10
F(A, B, C, D) = Σ(1, 6, 7, 9, 10, 11, 12)
(b)
A
0
0
0
0
0
0
1
1
1
1
0
0
1
1
B
0
0
1
1
1
1
1
1
0
0
0
0
1
1
C
1
1
0
0
1
1
1
1
0
0
0
0
0
0
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
0
0
0
0
1
1
1
1
0
1
1
0
1
0
I1
= 0
I2 = 0
I3 = 1
I7 = 1
I4
= D
Other minterms = 0
since I1
= I2
= 0
00
01
11
10
00 01 11 10
B
C
AB
CD
A
D
1
m0
1
m1
m3
m2
m4 m5
1
m7
1
m6
m12
1
m13
1
m15
1
m14
m8
1
m9 m11 m10
F(A, B, C, D) = Σ(0, 1, 6, 7, 9, 13, 14, 15)
I0
= D'
I6
= D'
4.35 (a)
Inputs
ABCD F
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AB = 00
F = D
AB = 01
F = C'D'
= (C + D)'
AB = 10
F = CD
AB = 11
F = 1
4 x 1
MUX
s0
s1
A
1
Y F
B
0
1
2
3
C
D
83.
Digital
Design
With
An
Introduction
to
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Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
All
rights
reserved.
83
(b) F = S(1, 2, 5, 7, 8, 10, 11, 13, 15)
Inputs
ABCD F2 = Σ(1, 2, 5, 7, 8, 10, 11, 13, 15)
0
1
1
0
0
1
0
1
1
0
1
1
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AB = 00
F = C'D + CD'
AB = 01
F = C'D + CD = D
AB = 10
F = C'D' + C'D + CD = C'D' + D
AB = 11
F = D
4 x 1
MUX
s0
s1
A
Y
F2
B
0
1
2
3
C
D
4.36
module priority_encoder_gates (output x, y, V, input D0, D1, D2, D3); // V2001
wire w1, D2_not;
not (D2_not, D2);
or (x, D2, D3);
or (V, D0, D1, x);
and (w1, D2_not, D1);
or (y, D3, w1);
endmodule
Note:
See
Problem
4.45
for
testbench)
4.37
module Add_Sub_4_bit (
output [3: 0] S,
output C,
input [3: 0] A, B,
input M
);
wire [3: 0] B_xor_M;
wire C1, C2, C3, C4;
assign C = C4; // output carry
xor (B_xor_M[0], B[0], M);
xor (B_xor_M[1], B[1], M);
xor (B_xor_M[2], B[2], M);
xor (B_xor_M[3], B[3], M);
// Instantiate full adders
full_adder FA0 (S[0], C1, A[0], B_xor_M[0], M);
full_adder FA1 (S[1], C2, A[1], B_xor_M[1], C1);
full_adder FA2 (S[2], C3, A[2], B_xor_M[2], C2);
full_adder FA3 (S[3], C4, A[3], B_xor_M[3], C3);
endmodule
module full_adder (output S, C, input x, y, z); // See HDL Example 4.2
wire S1, C1, C2;
// instantiate half adders
half_adder HA1 (S1, C1, x, y);
half_adder HA2 (S, C2, S1, z);
or G1 (C, C2, C1);
endmodule
84.
Digital
Design
With
An
Introduction
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HDL
–
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Manual.
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2012,
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reserved.
84
module half_adder (output S, C, input x, y); // See HDL Example 4.2
xor (S, x, y);
and (C, x, y);
endmodule
module t_Add_Sub_4_bit ();
wire [3: 0] S;
wire C;
reg [3: 0] A, B;
reg M;
Add_Sub_4_bit M0 (S, C, A, B, M);
initial #100 $finish;
initial fork
#10 M = 0;
#10 A = 4'hA;
#10 B = 4'h5;
#50 M = 1;
#70 B = 4'h3;
join
endmodule
Name 0 50 100
A[3:0]
B[3:0]
M
S[3:0]
C
x
x
x f 5
5
7
3
a
4.38
module quad_2x1_mux ( // V2001
input [3: 0] A, B, // 4-bit data channels
input enable_bar, select, // enable_bar is active-low)
output [3: 0] Y // 4-bit mux output
);
//assign Y = enable_bar ? 0 : (select ? B : A); // Grounds output
assign Y = enable_bar ? 4'bzzzz : (select ? B : A); // Three-state output
endmodule
//
Note
that
this
mux
grounds
the
output
when
the
mux
is
not
active.
module t_quad_2x1_mux ();
reg [3: 0] A, B, C; // 4-bit data channels
reg enable_bar, select; // enable_bar is active-low)
wire [3: 0] Y; // 4-bit mux
quad_2x1_mux M0 (A, B, enable_bar, select, Y);
initial #200 $finish;
initial fork
enable_bar = 1;
select = 1;
A = 4'hA;
B = 4'h5;
#10 select = 0; // channel A
85.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
Mano.
M.D.
Ciletti,
Copyright
2012,
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rights
reserved.
85
#20 enable_bar = 0;
#30 A = 4'h0;
#40 A = 4'hF;
#50 enable_bar = 1;
#60 select = 1; // channel B
#70 enable_bar = 0;
#80 B = 4'h00;
#90 B = 4'hA;
#100 B = 4'hF;
#110 enable_bar = 1;
#120 select = 0;
#130 select = 1;
#140 enable_bar = 1;
join
endmodule
Name 0 70 140
A[3:0]
B[3:0]
enable_bar
select
Y[3:0] 0
a
a 0
0
f 0
5
5 0
0 a
a f 0
f
f
With three-state output:
Name 0 70 140
A[3:0]
B[3:0]
enable_bar
select
Y[3:0] z
a
a 0
0
f z
5
5 0
0 a
a f z
f
f
4.39 // Verilog 1995
module Compare (A, B, Y);
input [3: 0] A, B; // 4-bit data inputs.
output [5: 0] Y; // 6-bit comparator output.
reg [5: 0] Y; // EQ, NE, GT, LT, GE, LE
always @ (A or B)
if (A==B) Y = 6'b10_0011; // EQ, GE, LE
else if (A < B) Y = 6'b01_0101; // NE, LT, LE
else Y = 6'b01_1010; // NE, GT, GE
endmodule
// Verilog 2001, 2005
module Compare (input [3: 0] A, B, output reg [5:0] Y);
always @ (A, B)
if (A==B) Y = 6'b10_0011; // EQ, GE, LE
else if (A < B) Y = 6'b01_0101; // NE, LT, LE
else Y = 6'b01_1010; // NE, GT, GE
endmodule
86.
Digital
Design
With
An
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HDL
–
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Manual.
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Ciletti,
Copyright
2012,
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rights
reserved.
86
4.40
module Prob_4_40 (
output [3: 0] sum_diff, output carry_borrow,
input [3: 0] A, B, input sel_diff
);
always @(sel_diff, A, B) {carry_borrow, sum_diff} = sel_diff ? A - B : A + B;
endmodule
module t_Prob_4_40;
wire [3: 0] sum_diff;
wire carry_borrow;
reg [3:0] A, B;
reg sel_diff;
integer I, J, K;
Prob_4_40 M0 ( sum_diff, carry_borrow, A, B, sel_diff);
initial #4000 $finish;
initial begin
for (I = 0; I < 2; I = I + 1) begin
sel_diff = I;
for (J = 0; J < 16; J = J + 1) begin
A = J;
for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end
end
end
end
endmodule
4.41
module Prob_4_41 (
output reg [3: 0] sum_diff, output reg carry_borrow,
input [3: 0] A, B, input sel_diff
);
always @ (A, B, sel_diff)
{carry_borrow, sum_diff} = sel_diff ? A - B : A + B;
endmodule
module t_Prob_4_41;
wire [3: 0] sum_diff;
wire carry_borrow;
reg [3:0] A, B;
reg sel_diff;
integer I, J, K;
Prob_4_46 M0 ( sum_diff, carry_borrow, A, B, sel_diff);
initial #4000 $finish;
initial begin
for (I = 0; I < 2; I = I + 1) begin
sel_diff = I;
for (J = 0; J < 16; J = J + 1) begin
A = J;
for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end
end
end
end
endmodule
87.
Digital
Design
With
An
Introduction
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the
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HDL
–
Solution
Manual.
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Copyright
2012,
All
rights
reserved.
87
Name
780 810 840 870
sel_diff
A[3:0]
B[3:0]
sum_diff[3:0]
carry_borrow
c
5 6
d e
7
9
f
8
0
a
1
b c
2 3
d e
4 5
f 0
6 7
1
8
2
9
3 4
a
5
b
6
c d
7 8
e
a
9
f 0
b
1
c d
2
b
Name
2064 2094 2124 2154
sel_diff
A[3:0]
B[3:0]
sum_diff[3:0]
carry_borrow
c
d
b
e
9
f 0
a
1
9
2
8
3
7
4
6 5
5 6
4
7
3
8
2
9
1 0
a
f
b c
e d
d e
c
a
f 0
b
1
a
2
9
b
4.42 (a)
module Xs3_Gates (input A, B, C, D, output w, x, y, z);
wire B_bar, C_or_D_bar;
wire CD, C_or_D;
or (C_or_D, C, D);
not (C_or_D_bar, C_or_D);
not (B_bar, B);
and (CD, C, D);
not (z, D);
or (y, CD, C_or_D_bar);
and (w1, C_or_D_bar, B);
and (w2, B_bar, C_or_D);
and (w3, C_or_D, B);
or (x, w1, w2);
or (w, w3, A);
endmodule
(b)
module Xs3_Dataflow (input A, B, C, D, output w, x, y, z);
assign {w, x, y, z} = {A, B, C, D} + 4'b0011;
endmodule
(c)
module Xs3_Behavior_95 (A, B, C, D, w, x, y, z);
input A, B, C, D;
output w, x, y, z;
reg w, x, y, z;
always @ (A or B or C or D) begin {w, x, y, z} = {A, B, C, D} + 4'b0011; end
endmodule
module Xs3_Behavior_01 (input A, B, C, D, output reg w, x, y, z);
88.
Digital
Design
With
An
Introduction
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HDL
–
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Manual.
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2012,
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rights
reserved.
88
always @ (A, B, C, D) begin {w, x, y, z} = {A, B,C, D} + 4'b0011; end
endmodule
module t_Xs3_Converters ();
reg A, B, C, D;
wire w_Gates, x_Gates, y_Gates, z_Gates;
wire w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow;
wire w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95;
wire w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01;
integer k;
wire [3: 0] BCD_value;
wire [3: 0] Xs3_Gates = {w_Gates, x_Gates, y_Gates, z_Gates};
wire [3: 0] Xs3_Dataflow = {w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow};
wire [3: 0] Xs3_Behavior_95 = {w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95};
wire [3: 0] Xs3_Behavior_01 = {w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01};
assign BCD_value = {A, B, C, D};
Xs3_Gates M0 (A, B, C, D, w_Gates, x_Gates, y_Gates, z_Gates);
Xs3_Dataflow M1 (A, B, C, D, w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow);
Xs3_Behavior_95 M2 (A, B, C, D, w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95);
Xs3_Behavior_01 M3 (A, B, C, D, w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01);
initial #200 $finish;
initial begin
k = 0;
repeat (10) begin {A, B, C, D} = k; #10 k = k + 1; end
end
endmodule
Name 0 30 60 90
k
A
B
C
D
BCD_value[3:0]
w_Gates
x_Gates
y_Gates
z_Gates
Xs3_Gates[3:0]
Xs3_Gates[3:0]
Xs3_Dataflow[3:0]
Xs3_Behavior_95[3:0]
Xs3_Behavior_01[3:0]
0
0011
3
3
3
3
0 1
4
4
4
0100
4
1 2
0101
5
5
5
5
2 3
6
6
6
0110
6
3 4
7
7
4
0111
7
7
8
8
8
1000
8
5
5
6
1001
9
9
9
9
6 7
a
a
a
1010
a
7 8
1011
b
b
b
b
8
9
c
c
c
c
1100
9
4.43 Two-channel mux with 2-bit data paths, enable, and three-state output.
4.44
module ALU (output reg [7: 0] y, input [7: 0] A, B, input [2: 0] Sel);
always @ (A, B, Sel) begin
y = 0;
case (Sel)
3'b000: y = 8'b0;
3'b001: y = A & B;
3'b010: y = A | B;
3'b011: y = A ^ B;
3'b100: y = A + B;
89.
Digital
Design
With
An
Introduction
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HDL
–
Solution
Manual.
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2012,
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rights
reserved.
89
3'b101: y = A - B;
3'b110: y = ~A;
3'b111: y = 8'hFF;
endcase
end
endmodule
module t_ALU ();
wire[7: 0]y;
reg [7: 0] A, B;
reg [2: 0] Sel;
ALU M0 (y, A, B, Sel);
initial #200 $finish;
initial fork
#5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0
#10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 Expect y = 8'd0
#20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B Expect y = 8'hAA = 8'1010_1010
#30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B Expect y = 8'h55 = 8'b0101_0101
#40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B Expect y = 8'h55 = 8'b0101_0101
#50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | B Expect y = 8'hAA = 8'b1010_1010
#60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B Expect y = 8'd0
#70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B Expect y = 8'hFF = 8'b1111_1111
#80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B Expect y = 8'h55 = 8'b0101_0101
#90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B Expect y = 8'hFF = 8'b1111_1111
#110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B Expect y = 8'h55 = 8'b0101_0101
#120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B Expect y = 8'hab = 8'b1010_1011
#130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#140 begin Sel = 3'b110; A = 8'd0; end // y = ~A Expect y = 8'hFF = 8'b1111_1111
#150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#160 begin Sel = 3'b111; end // y = 8'hFF Expect y = 8'hFF = 8'b1111_1111
join
endmodule
Name 0 60 120 180
Sel[2:0]
A[7:0]
B[7:0]
y[7:0]
55
00
aa
aa
aa
001
55
55
55
aa
aa
aa
010
55
00
55
aa
ff
011
55
00
55 ff
100
aa
55
55
101
55
ab 00
ff
ff
00
00
110
ff
aa
ff
111
Note that the subtraction operator performs 2's complement subtraction. So 8'h55 – 8'hAA adds the 2's
complement of 8'hAA to 8'h55 and gets 8'hAB. The sign bit is not included in the model, but hand
calculation shows that the 9th
bit is 1, indicating that the result of the operation is negative. The magnitude
of the result can be obtained by taking the 2's complement of 8'hAB.
4.45
module priority_encoder_beh (output reg X, Y, V, input D0, D1, D2, D3); // V2001
always @ (D0, D1, D2, D3) begin
X = 0;
Y = 0;
V = 0;
casex ({D0, D1, D2, D3})
90.
Digital
Design
With
An
Introduction
to
the
Verilog
HDL
–
Solution
Manual.
M.
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M.D.
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Copyright
2012,
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rights
reserved.
90
4'b0000: {X, Y, V} = 3'bxx0;
4'b1000: {X, Y, V} = 3'b001;
4'bx100: {X, Y, V} = 3'b011;
4'bxx10: {X, Y, V} = 3'b101;
4'bxxx1: {X, Y, V} = 3'b111;
default: {X, Y, V} = 3'b000;
endcase
end
endmodule
module t_priority_encoder_beh (); // V2001
wire X, Y, V;
reg D0, D1, D2, D3;
integer k;
priority_encoder_beh M0 (X, Y, V, D0, D1, D2, D3);
initial #200 $finish;
initial begin
k = 32'bx;
#10 for (k = 0; k <= 16; k = k + 1) #10 {D0, D1, D2, D3} = k;
end
endmodule
Name 0 60 120 180
k
D0
D1
D2
D3
X
Y
V
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
91.
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91
4.46 (a)
F = Σ(0, 2, 5, 7, 11, 14)
See code below.
(b) From prob 4.32:
F = Π (3, 8, 12) = (A' + B' + C + D)(A + B' + C' + D')(A + B + C' + D')
F' = ABC'D' + A'BCD + A'B'CD = Σ(12, 7, 3)
F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 10, 11, 13, 14, 15)
module Prob_4_46a (output F, input A, B, C, D);
assign F = (~A&~B&~C&~D) | (~A&~B&C&~D) | (~A&B&~C&D) | (~A&B&C&D) | (A&~B&C&D) |
(A&B&C&~D);
endmodule
module Prob_4_46b (output F, input A, B, C, D);
assign F = (~A&~B&~C&~D) | (~A&~B&~C&D) | (~A&~B&C&~D) | (~A&B&~C&~D) | (~A&B&~C&D) |
(~A&B&C&~D) | (A&~B&~C&~D) | (A&~B&~C&D) | (A&~B&C&~D) | (A&~B&C&D) | (A&B&~C&D) |
(A&B&C&~D) | (A&B&C&D);
endmodule
module t_Prob_4_46a ();
wire F_a, F_b;
reg A, B, C, D;
integer k;
Prob_4_46a M0 (F_a, A, B, C, D);
Prob_4_46b M1 (F_b, A, B, C, D);
initial
#200
$finish;
initial begin
k = 0;
#10 repeat (15) begin {A, B, C, D} = k; #10 k = k + 1; end
end
endmodule
Name 0 60 120 180
k
D0
D1
D2
D3
X
Y
V
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
92.
Digital
Design
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An
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HDL
–
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2012,
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rights
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92
4.47
module Add_Sub_4_bit_Dataflow (
output [3: 0] S,
output C, V,
input [3: 0] A, B,
input M
);
wire C3;
assign {C3, S[2: 0]} = A[2: 0] + ({M, M, M} ^ B[2: 0]) + M;
assign {C, S[3]} = A[3] + M ^ B[3] + C3;
assign V = C ^ C3;
endmodule
module t_Add_Sub_4_bit_Dataflow ();
wire [3: 0] S;
wire C, V;
reg [3: 0] A, B;
reg M;
Add_Sub_4_bit_Dataflow M0 (S, C, V, A, B, M);
initial #100 $finish;
initial fork
#10 M = 0;
#10 A = 4'hA;
#10 B = 4'h5;
#50 M = 1;
#70 B = 4'h3;
join
endmodule
Name 0 50 100
A[3:0]
B[3:0]
M
S[3:0]
C
x
x
x f 5
5
7
3
a
4.48
module ALU_3state (output [7: 0] y_tri, input [7: 0] A, B, input [2: 0] Sel, input En);
reg [7: 0] y;
assign y_tri = En ? y: 8'bz;
always @ (A, B, Sel) begin
y = 0;
case (Sel)
3'b000: y = 8'b0;
3'b001: y = A & B;
3'b010: y = A | B;
3'b011: y = A ^ B;
3'b100: y = A + B;
3'b101: y = A - B;
3'b110: y = ~A;
3'b111: y = 8'hFF;
endcase
end
93.
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With
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93
endmodule
module t_ALU_3state ();
wire[7: 0] y;
reg [7: 0] A, B;
reg [2: 0] Sel;
reg En;
ALU_3state M0 (y, A, B, Sel, En);
initial #200 $finish;
initial fork
#5 En = 1;
#5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0
#10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 Expect y = 8'd0
#20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B Expect y = 8'hAA = 8'1010_1010
#30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B Expect y = 8'h55 = 8'b0101_0101
#40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B Expect y = 8'h55 = 8'b0101_0101
#50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | BExpect y = 8'hAA = 8'b1010_1010
#60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B Expect y = 8'd0
#70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B Expect y = 8'hFF = 8'b1111_1111
#80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B Expect y = 8'h55 = 8'b0101_0101
#90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B Expect y = 8'hFF = 8'b1111_1111
#100 En = 0;
#115 En = 1;
#110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B Expect y = 8'h55 = 8'b0101_0101
#120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B Expect y = 8'hab = 8'b1010_1011
#130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#140 begin Sel = 3'b110; A = 8'd0; end // y = ~A Expect y = 8'hFF = 8'b1111_1111
#150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0
#160 begin Sel = 3'b111; end // y = 8'hFF Expect y = 8'hFF = 8'b1111_1111
join
endmodule
4.49
// See Problem 4.1
module Problem_4_49_Gates (output F1, F2, input A, B, C, D);
wire A_bar = !A;
wire B_bar = !B;
and (T1, B_bar, C);
and (T2, A_bar, B);
or (T3, A, T1);
xor (T4, T2, D);
or (F1, T3, T4);
or (F2, T2, D);
endmodule
module Problem_4_49_Boolean_1 (output F1, F2, input A, B, C, D);
wire A_bar = !A;
wire B_bar = !B;
wire T1 = B_bar && C;
wire T2 = A_bar && B;
wire T3 = A || T1;
wire T4 = T2 ^ D;
assign F1 = T3 || T4;
assign F2 = T2 || D;
endmodule
module Problem_4_49_Boolean_2(output F1, F2, input A, B, C, D);
assign F1 = A || (!B && C) || (B && (!D)) || (!B && D);
assign F2 = ((!A) && B) || D;
endmodule
