The document discusses sequential logic implementation including finite state machines (FSMs). It covers FSM design procedures like deriving state diagrams and transition tables from specifications. It also compares Moore and Mealy machines, noting that Moore machines have outputs depend only on current state while Mealy machines have outputs depend on current state and inputs. Mealy machines tend to require fewer states but Moore machines are safer to use in designs where outputs change at clock edges. The document provides examples of specifying and implementing FSMs in Verilog including both Moore and Mealy machines. It also gives an example FSM design for a vending machine.
This document describes several examples of VHDL code implementations for digital circuits, including:
1) Moore and Mealy finite state machines with 1 input and 1 output each
2) A 5x8 read-only memory (ROM) implemented using a constant array
3) A waveform generator that uses a 4x13 ROM to generate a repeating waveform pattern
4) An enhanced "smart" waveform generator that allows time steps in the waveform to be extended over multiple clock cycles
The examples provide VHDL code listings and brief explanations of how each circuit is modeled and synthesized from the VHDL description.
This document describes an exercise to implement basic logic circuits using an FPGA development board. It involves:
1. Creating a circuit to read input switches and display their states on LEDs.
2. Designing a 4-bit 2-to-1 multiplexer circuit to select between two 4-bit inputs based on a selection bit.
3. Building a 2-bit wide 3-to-1 multiplexer using two 2-to-1 multiplexers to select between three 2-bit inputs.
The circuits are tested by toggling switches and observing the output LEDs. This allows learning how to interface
inputs and outputs to an FPGA and implement basic multiplexer logic.
S-functions Paper Presentation: Switching Amplifier Design With S-functionsNMDG NV
This document discusses using S-functions to model switching amplifiers. S-functions are similar to S-parameters but can model nonlinear behavior by describing the amplifier's response to both fundamental and harmonic frequencies under different operating conditions. The document outlines how to extract S-functions by applying tickling tones at various harmonic frequencies while varying the large-signal operating point, and solving for the S-function coefficients. It also describes setups using tuners to control harmonic impedances during extraction and validation of the S-function model. An example case study of extracting S-functions for a GaN power amplifier is presented.
SPICE MODEL of DF2S6.8UFS , PSpice Model in SPICE PARKTsuyoshi Horigome
SPICE MODEL of DF2S6.8UFS , PSpice Model in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document describes several examples of VHDL code implementations for digital circuits, including:
1) Moore and Mealy finite state machines with 1 input and 1 output each
2) A 5x8 read-only memory (ROM) implemented using a constant array
3) A waveform generator that uses a 4x13 ROM to generate a repeating waveform pattern
4) An enhanced "smart" waveform generator that allows time steps in the waveform to be extended over multiple clock cycles
The examples provide VHDL code listings and brief explanations of how each circuit is modeled and synthesized from the VHDL description.
This document describes an exercise to implement basic logic circuits using an FPGA development board. It involves:
1. Creating a circuit to read input switches and display their states on LEDs.
2. Designing a 4-bit 2-to-1 multiplexer circuit to select between two 4-bit inputs based on a selection bit.
3. Building a 2-bit wide 3-to-1 multiplexer using two 2-to-1 multiplexers to select between three 2-bit inputs.
The circuits are tested by toggling switches and observing the output LEDs. This allows learning how to interface
inputs and outputs to an FPGA and implement basic multiplexer logic.
S-functions Paper Presentation: Switching Amplifier Design With S-functionsNMDG NV
This document discusses using S-functions to model switching amplifiers. S-functions are similar to S-parameters but can model nonlinear behavior by describing the amplifier's response to both fundamental and harmonic frequencies under different operating conditions. The document outlines how to extract S-functions by applying tickling tones at various harmonic frequencies while varying the large-signal operating point, and solving for the S-function coefficients. It also describes setups using tuners to control harmonic impedances during extraction and validation of the S-function model. An example case study of extracting S-functions for a GaN power amplifier is presented.
SPICE MODEL of DF2S6.8UFS , PSpice Model in SPICE PARKTsuyoshi Horigome
SPICE MODEL of DF2S6.8UFS , PSpice Model in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document summarizes the modeling parameters and performance of a voltage regulator component. It describes the manufacturer, part number, and key electrical parameters represented in the PSpice model. Simulation results show the input-output voltage differential is within 0.1% of measured, and ripple rejection ratio is within 0.9% of measured. The output characteristic comparison shows simulation within 0.65% of measured.
This document provides a device modeling report for a PWM stepping motor driver with the part number TB62206FG manufactured by Toshiba. The report details the circuit configuration including components, block diagrams of subcircuits, parameter definitions, and simulation results comparing phase input to phase output current.
This document summarizes the modeling parameters and performance of the uPC78N08H voltage regulator. It includes:
1) A list of model parameters used in the PSpice model including reference voltage, emission coefficient, and capacitance values.
2) Simulation results showing the input-output voltage differential is within 0.008% of measurements.
3) Ripple rejection ratio simulation of 67.535dB is within -0.684% of measured value.
4) Output characteristic simulation of 7.9796V is within -0.255% of measured 8V output voltage.
The document provides a device modeling report for a Toshiba TA7291P bridge driver IC. It includes:
- Component and part number details
- Circuit simulations and evaluation circuits showing the IC's operation under different input and output conditions
- Simulation results analyzing key parameters like supply current, input characteristics, saturation voltages, and diode characteristics.
The report concludes with 11 sections summarizing the IC's electrical behavior and performance based on circuit simulations, with tables comparing simulated and measured values.
The document summarizes an SPICE model of a 3-phase AC motor that can accurately reproduce: (1) frequency characteristics (impedance characteristics), (2) reverse electromotive force characteristics, and (3) physical characteristics. It provides details on parameter settings for the model, the simulation circuit diagram, and simulation results showing characteristics like phase current, back-EMF, speed, torque, power output, and efficiency under varying load conditions.
This document summarizes the modeling parameters and performance of the uPC78N24H voltage regulator. It includes:
1) A list of model parameters for the regulator including reference voltage, emission coefficient, and capacitance values.
2) Simulation results showing the input-output voltage differential is within 0.2% of measurements.
3) Ripple rejection ratio simulation matching measurements within 5%.
4) Output voltage simulation matching measurements to within 0.05% under varying load and input conditions.
SPICE MODEL of uPC24A12HF in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document discusses finite state machines (FSMs), specifically Moore and Mealy machines. It defines FSMs as circuits with a combinational block and memory block that can exist in multiple states, transitioning between states based on inputs. Moore machines output depends solely on the current state, while Mealy machines output depends on both the current state and inputs. Moore machines are safer since output only changes at clock edges, while Mealy machines are faster since output relies on inputs. Choosing between them depends on factors like whether synchronous/asynchronous operation is needed and whether speed or safety is a higher priority.
This document summarizes the modeling parameters and performance of a voltage regulator component. It describes the manufacturer, part number, and key electrical parameters represented in the PSpice model. Simulation results show the input-output voltage differential is within 0.1% of measured, and ripple rejection ratio is within 0.9% of measured. The output characteristic comparison shows simulation within 0.65% of measured.
This document provides a device modeling report for a PWM stepping motor driver with the part number TB62206FG manufactured by Toshiba. The report details the circuit configuration including components, block diagrams of subcircuits, parameter definitions, and simulation results comparing phase input to phase output current.
This document summarizes the modeling parameters and performance of the uPC78N08H voltage regulator. It includes:
1) A list of model parameters used in the PSpice model including reference voltage, emission coefficient, and capacitance values.
2) Simulation results showing the input-output voltage differential is within 0.008% of measurements.
3) Ripple rejection ratio simulation of 67.535dB is within -0.684% of measured value.
4) Output characteristic simulation of 7.9796V is within -0.255% of measured 8V output voltage.
The document provides a device modeling report for a Toshiba TA7291P bridge driver IC. It includes:
- Component and part number details
- Circuit simulations and evaluation circuits showing the IC's operation under different input and output conditions
- Simulation results analyzing key parameters like supply current, input characteristics, saturation voltages, and diode characteristics.
The report concludes with 11 sections summarizing the IC's electrical behavior and performance based on circuit simulations, with tables comparing simulated and measured values.
The document summarizes an SPICE model of a 3-phase AC motor that can accurately reproduce: (1) frequency characteristics (impedance characteristics), (2) reverse electromotive force characteristics, and (3) physical characteristics. It provides details on parameter settings for the model, the simulation circuit diagram, and simulation results showing characteristics like phase current, back-EMF, speed, torque, power output, and efficiency under varying load conditions.
This document summarizes the modeling parameters and performance of the uPC78N24H voltage regulator. It includes:
1) A list of model parameters for the regulator including reference voltage, emission coefficient, and capacitance values.
2) Simulation results showing the input-output voltage differential is within 0.2% of measurements.
3) Ripple rejection ratio simulation matching measurements within 5%.
4) Output voltage simulation matching measurements to within 0.05% under varying load and input conditions.
SPICE MODEL of uPC24A12HF in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document discusses finite state machines (FSMs), specifically Moore and Mealy machines. It defines FSMs as circuits with a combinational block and memory block that can exist in multiple states, transitioning between states based on inputs. Moore machines output depends solely on the current state, while Mealy machines output depends on both the current state and inputs. Moore machines are safer since output only changes at clock edges, while Mealy machines are faster since output relies on inputs. Choosing between them depends on factors like whether synchronous/asynchronous operation is needed and whether speed or safety is a higher priority.
Este documento resume las actividades y eventos planeados en el Colegio María Mercedes Carranza para la semana del 10 al 13 de mayo, incluyendo la celebración del Día del Trabajador, del Maestro y de la Madre. También detalla el horario de diferentes actividades como taekwondo, ajedrez y talleres de orientación. Además, presenta la organización para la entrada y salida de los estudiantes de primaria y los responsables de acompañarlos al descanso.
El documento presenta el programa de actividades para la semana del 7 al 11 de marzo en el Colegio María Mercedes Carranza IED, incluyendo los horarios de acompañamiento al ingreso, descanso y salida de los estudiantes, reuniones de docentes, celebración del Día Internacional de la Mujer, talleres y capacitaciones. También incluye información sobre los horarios del comedor escolar y los centros de interés para estudiantes con talentos.
Este documento presenta la coordinación de actividades para la semana del 18 al 21 de julio en el Colegio María Mercedes Carranza. Incluye los horarios de acompañamiento de estudiantes, reuniones de docentes, entrega de boletines, festividades y horarios de centros de interés como taekwondo y ajedrez.
Este documento presenta las actividades programadas para la semana del 8 al 12 de febrero en el Colegio María Mercedes Carranza IED. Incluye el acompañamiento de estudiantes en el ingreso, descanso y salida, charlas de prevención a cargo de la policía, reuniones de docentes, talleres del proyecto "Educando con energía", y horarios para el ingreso al comedor escolar con el 100% de cobertura de estudiantes. También contiene información general sobre el proceso electoral estudiantil, entrega de documentos y dese
Este documento presenta la coordinación de la jornada de la mañana para la semana del 16 al 19 de agosto en el Colegio María Mercedes Carranza. Incluye los horarios de acompañamiento de los estudiantes al ingreso, descanso y salida, así como las reuniones programadas para cada día con padres de familia y docentes. También contiene información general sobre el horario del comedor escolar, cambios en las semanas de nivelación y participación de un estudiante en campeonatos deportivos.
Este documento presenta la programación de actividades para la semana del 25 al 29 de abril en el Colegio María Mercedes Carranza. Incluye talleres sobre derechos sexuales y reproductivos, reuniones de coordinadores y comités, un simulacro de evacuación, sensibilizaciones sobre conciliación y el día del idioma, y una jornada pedagógica.
El documento presenta el cronograma de actividades y horarios para la semana del 31 de octubre al 4 de noviembre en el Colegio María Mercedes Carranza. Incluye los turnos de acompañamiento de docentes en el ingreso, descanso y salida de estudiantes de primaria y secundaria, así como las reuniones, eventos culturales y deportivos programados para cada día de la semana. También proporciona información general sobre el horario de ingreso al comedor escolar y otros anuncios.
El documento presenta el cronograma de actividades y reuniones programadas para la semana del 18 al 22 de abril en el Colegio María Mercedes Carranza. Incluye los horarios de acompañamiento de los estudiantes, las reuniones de docentes y directivos, los talleres del proyecto "Educando con energía", y los horarios del comedor y centros de interés del programa de talentos.
The document provides an overview of Moore and Mealy state machines. It discusses sequential design steps like drawing state diagrams and making next state truth tables. For Moore machines, outputs are determined solely by the current state. For Mealy machines, outputs are determined by both the current state and current inputs. The document gives examples to illustrate Moore and Mealy machines, comparing their timing and showing how Mealy machines can require fewer states.
El documento es una invitación del Colegio María Mercedes Carranza a participar en la Semana por la Paz del 5 al 9 de septiembre. La programación incluye un acto protocolario con la participación de estudiantes de diferentes ciclos, una intervención sobre derechos humanos y convivencia, y un foro final con ponentes y la presencia de la Personería de Bogotá para reflexionar sobre el proceso de paz en Colombia.
El resumen describe la programación semanal del Colegio María Mercedes Carranza IED para la semana del 30 de enero al 3 de febrero de 2017. Incluye los turnos de acompañamiento de los estudiantes al ingreso, descanso y salida, así como las reuniones y actividades programadas para cada día de la semana, como dirección de grupo, reuniones de áreas y ciclos, y el inicio del servicio de comida caliente en el comedor escolar.
Este documento presenta la coordinación de la jornada de la mañana para la semana del 8 al 12 de agosto en el Colegio María Mercedes Carranza. Incluye los turnos de acompañamiento de los estudiantes, las reuniones programadas para cada día con los diferentes ciclos y áreas, y la información general sobre el horario del comedor escolar.
NASA and commercial space flight companies are expanding our reach into the solar system and beyond.
Here at home, AECOM supports the mission by designing high — performance facilities and helping them develop and test new technologies.
Este documento presenta el cronograma de actividades y los turnos de acompañamiento para la semana del 7 al 11 de noviembre en el Colegio María Mercedes Carranza. Se asignan docentes para acompañar a los estudiantes durante el ingreso, descanso y salida. Se llevarán a cabo comisiones de evaluación y promoción los martes y miércoles. El jueves se entregarán los resultados y horarios de recuperación. El viernes iniciarán las clases de recuperación.
This document provides instructions for laboratory exercises involving digital logic circuits. The exercises include:
1) Studying the operation of logic gates like AND, OR, NOT, NAND, and XOR using integrated circuits and completing truth tables.
2) Verifying Boolean logic laws such as associativity and distributivity using logic gate circuits.
3) Implementing NOT, NAND, NOR, and XOR gates using integrated circuits and observing their truth tables.
4) Demonstrating De Morgan's theorem by connecting logic gate circuits in a specific configuration and completing a truth table.
The document discusses fault tolerant and online testability in reversible logic synthesis. It proposes a design for a fault tolerant full adder circuit using reversible logic that is both fault tolerant and online testable. The proposed design uses only 3x3 fault tolerant gates, has a minimum number of garbage outputs of 3, and has lower quantum cost compared to an existing design. Performance analysis shows the proposed design has advantages over the existing design in terms of number of gates, garbage outputs, and quantum cost.
This document discusses the design procedure for finite state machines (FSMs). It describes how to start with a word problem description, create a state table to define the next states and outputs, minimize logic expressions using K-maps, and draw the resulting circuit diagram incorporating flip-flops and combinational logic. An example of detecting three consecutive 1 inputs is used to illustrate the full procedure. The document also distinguishes between Mealy and Moore machine implementations and provides additional examples of odd parity checking and a vending machine FSM.
SPICE MODEL of TC7SET00FU in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
1. The document discusses programming for programmable logic controllers (PLCs), including basic PLC operations using binary numbers, logic gates, ladder diagrams, and mnemonic codes.
2. It describes the basic logic functions of AND, OR, and NOT gates that digital devices use, and how ladder diagrams represent circuit diagrams using these logic symbols.
3. The steps for designing ladder diagrams from truth tables or state diagrams are outlined, including converting the diagrams to mnemonic codes that can be programmed into a PLC.
The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.
The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.
This document summarizes the results of device modeling tests on a CMOS digital integrated circuit (TC7SH08FE) manufactured by Toshiba. The summary includes:
1) Truth table, circuit simulation, and measurement results show the device operates as expected under different input conditions.
2) Minimum input and output voltage levels meet specifications within an error of 3.58% or less.
3) Propagation delay times measured and simulated match to within 1.553% or better.
SPICE MODEL of TC7SZ00AFE in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
This document summarizes the results of device modeling and simulation of the TC7S02FU CMOS digital integrated circuit manufactured by Toshiba. Key specifications such as input voltages, output voltages, propagation delay times were measured and found to match simulation results with less than 1% error. Truth tables and signal timing diagrams from circuit simulations validate the correct logic functionality of the device.
Boolean algebra is a logical system used to simplify binary expressions. It uses binary variables that can have a value of 1 or 0, and logical operators like AND, OR and NOT. Boolean expressions can be represented in truth tables and minimized using Karnaugh maps or algebraic manipulation. Key concepts include minterms, maxterms, sum of products form, and product of sums form. Boolean algebra provides a standard way to simplify logical statements and circuits into their essential components.
1. Sequential Logic Implementation
! Models for representing sequential circuits
" Abstraction of sequential elements
" Finite state machines and their state diagrams
" Inputs/outputs
" Mealy, Moore, and synchronous Mealy machines
! Finite state machine design procedure
" Verilog specification
" Deriving state diagram
" Deriving state transition table
" Determining next state and output functions
" Implementing combinational logic
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 1
Mealy vs. Moore Machines
! Moore: outputs depend on current state only
! Mealy: outputs depend on current state and inputs
! Ant brain is a Moore Machine
" Output does not react immediately to input change
! We could have specified a Mealy FSM
" Outputs have immediate reaction to inputs
" As inputs change, so does next state, doesn’t commit until
clocking event
L’ R / TL, F
L / TL
A
react right away to leaving the wall
L’ R’ / TR, F
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 2
2. Specifying Outputs for a Moore Machine
! Output is only function of state
" Specify in state bubble in state diagram
" Example: sequence detector for 01 or 10
current next
reset input state state output
0
1 – – A
1 0 0 A B 0
B/0 D/1
0 1 A C 0
0 0 0 B B 0
0 0 1 B D 0
reset
A/0 1 0
0 0 C E 0
1 0 1 C C 0
1 0 0 D E 1
C/0 E/1 0 1 D C 1
0
0 0 E B 1
1 0 1 E D 1
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 3
Specifying Outputs for a Mealy
Machine
! Output is function of state and inputs
" Specify output on transition arc between states
" Example: sequence detector for 01 or 10
0/0 current next
reset input state state output
1 – – A 0
B
0 0 A B 0
0/0
0 1 A C 0
reset/0 0 0 B B 0
A 0/1 1/1
0 1 B C 1
0 0 C B 1
1/0 0 1 C C 0
C
1/0
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 4
3. Comparison of Mealy and Moore Machines
! Mealy Machines tend to have less states
" Different outputs on arcs (n^2) rather than states (n)
! Moore Machines are safer to use
" Outputs change at clock edge (always one cycle later)
" In Mealy machines, input change can cause output change as soon as
logic is done – a big problem when two machines are interconnected –
asynchronous feedback
! Mealy Machines react faster to inputs
" React in same cycle – don't need to wait for clock
" In Moore machines, more logic may be necessary to decode state
into outputs – more gate delays after
Logic
inputs Combinational inputs outputs
for
logic outputs
for Logic Combinational
Next State reg outputs reg
for logic for
outputs Next State
state feedback state feedback
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 5
Mealy and Moore Examples
! Recognize A,B = 0,1
" Mealy or Moore?
A
out
D Q
B
clock
Q
A
D Q out
Q
B
D Q
clock
Q
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 6
4. Mealy and Moore Examples (cont’d)
! Recognize A,B = 1,0 then 0,1
" Mealy or Moore?
out
A
D Q
Q
B
D Q
Q
clock
out
A
D Q D Q
Q Q
B
D Q D Q
Q Q
clock
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 7
Registered Mealy Machine (Really Moore)
! Synchronous (or registered) Mealy Machine
" Registered state AND outputs
" Avoids ‘glitchy’ outputs
" Easy to implement in programmable logic
! Moore Machine with no output decoding
" Outputs computed on transition to next state rather than
after entering
" View outputs as expanded state vector
output
Outputs
logic
Inputs
next state
logic
Current State
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 8
5. Verilog FSM - Reduce 1s Example
! Change the first 1 to 0 in each string of 1’s zero
" Example Moore machine implementation [0]
1 0
// State assignment 0 one1
parameter zero = 0, one1 = 1, two1s = 2;
[0]
module reduce (out, clk, reset, in); 0 1
output out;
1
input clk, reset, in;
reg out; two1s
reg [1:0] state; // state register [1]
reg [1:0] next_state;
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 9
Moore Verilog FSM (cont’d)
always @(in or state)
case (state)
zero
zero: begin // last input was a zero [0]
out = 0;
if (in) next_state = one1; 1 0
else next_state = zero;
end 0 one1
[0]
one1: begin // we've seen one 1
out = 0; 0 1
if (in) next_state = two1s; 1
else next_state = zero; two1s
end [1]
two1s: begin // we've seen at least 2 ones
out = 1;
if (in) next_state = two1s;
else next_state = zero;
include all signals
end that are input to state
and output equations
default: begin // in case we reach a bad state
out = 0;
next_state = zero;
endcase
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 10
6. Moore Verilog FSM (cont’d)
// Implement the state register
always @(posedge clk) zero
if (reset) state <= zero; [0]
else state <= next_state;
1 0
endmodule
0 one1
[0]
0 1
1
two1s
[1]
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 11
Mealy Verilog FSM for Reduce-1s Example
module reduce (clk, reset, in, out);
input clk, reset, in; output out;
reg out; reg state; // state register
0/0
reg next_state;
parameter zero = 0, one = 1; zero
always @(in or state)
case (state) 0/0 1/0
zero: begin // last input was a zero
if (in) next_state = one;
else next_state = zero; one1
out = 0; 1/1
end
one: // we've seen one 1
if (in) begin
next_state = one;
out = 1;
end
else begin
next_state = zero;
out = 0;
end
endcase
always @(posedge clk)
if (reset) state <= zero;
else state <= next_state;
endmodule CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 12
7
7. Synchronous Mealy Verilog FSM for
Reduce-1s Example
module reduce (clk, reset, in, out);
input clk, reset, in; output out;
reg out; reg state; // state register
reg next_state; reg next_out; 0/0
parameter zero = 0, one = 1;
zero
always @(in or state)
case (state)
zero: begin // last input was a zero 0/0 1/0
if (in) next_state = one;
else next_state = zero;
next_out = 0; one1
end
one: // we've seen one 1 1/1
if (in) begin
next_state = one;
next_out = 1;
end
else begin
next_state = zero;
next_out = 0;
end
endcase
always @(posedge clk)
if (reset) begin
state <= zero; out <= 0;
end
else begin
state <= next_state; out <= next_out;
end
endmodule CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 13
7
Announcements
! Review Session Announcement
! First Midterm, Thursday, 15 February, 2-3:30 PM,
125 Cory Hall
" ??? Quiz-like Questions -- Please Read Them Carefully! They
are not intended to be tricky; they should contain all the
information you need to answer the question correctly
" No calculators or other gadgets are necessary! Don’t bring
them! No blue books! All work on the sheets handed out!
" Do bring pencil and eraser please! If you like to unstaple the
exam pages, then bring a stapler with you! Write your name
and student ID on EVERY page in case they get separated --
it has happened!
" Don’t forget your two-sided 8.5” x 11” crib sheet!
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 14
8. Announcements
! Examination, Th, 2-3:30 PM, 125 Cory Hall
" Topics likely to be covered
# Combinational logic: design and optimization (K-maps up to and including 6
variables)
# Implementation: Simple gates (minimum wires and gates), PLA structures
(minimum unique terms), Muxes, Decoders, ROMs, (Simplified) Xilinx CLB
# Sequential logic: R-S latches, flip-flops, transparent vs. edge-triggered
behavior, master/slave concept
# Basic Finite State Machines: Representations (state diagrams, transition
tables), Moore vs. Mealy Machines, Shifters, Registers, Counters
# Structural and Behavioral Verilog for combinational and sequential logic
# Labs 1, 2, 3
# K&B: Chapters 1, 2 (2.1-2.5), 3 (3.1, 3.6), 4 (4.1, 4.2, 4.3), 6 (6.1, 6.2.1,
6.3), 7 (7.1, 7.2, 7.3)
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 15
Example: Vending Machine
! Release item after 15 cents are deposited
! Single coin slot for dimes, nickels
! No change
Reset
N
Vending Open
Coin Machine Release
Sensor FSM Mechanism
D
Clock
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 16
9. Example: Vending Machine (cont’d)
! Suitable Abstract Representation
" Tabulate typical input sequences: Reset
# 3 nickels
# nickel, dime
S0
# dime, nickel
# two dimes N D
" Draw state diagram:
# Inputs: N, D, reset S1 S2
# Output: open chute N D N D
" Assumptions:
# Assume N and D asserted S4 S5 S6
S3
for one cycle [open] [open] [open]
# Each state has a self loop N
for N = D = 0 (no coin)
S7
[open]
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 17
Example: Vending Machine (cont’d)
! Minimize number of states - reuse states whenever possible
Reset present inputs next output
state D N state open
0¢ 0 0 0¢ 0
0 1 5¢ 0
0¢ 1 0 10¢ 0
1 1 – –
N 5¢ 0 0 5¢ 0
0 1 10¢ 0
5¢ D 1 0 15¢ 0
1 1 – –
N 10¢ 0 0 10¢ 0
0 1 15¢ 0
D 1 0 15¢ 0
10¢
1 1 – –
15¢ – – 15¢ 1
N+D
15¢ symbolic state table
[open]
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 18
10. Example: Vending Machine (cont’d)
! Uniquely Encode States
present state inputs next state output
Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 – – –
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 – – –
1 1 – – 1 1 1
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 19
Example: Vending Machine (cont’d)
! Mapping to Logic D1
Q1
D0
Q1
Open
Q1
0 0 1 1 0 1 1 0 0 0 1 0
0 1 1 1 1 0 1 1 0 0 1 0
N N N
X X X X X X X X X X X X
D D D
1 1 1 1 0 1 1 1 0 0 1 0
Q0 Q0 Q0
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 20
12. Moore Verilog FSM for Vending Machine
module vending (open, Clk, Reset, N, D);
input Clk, Reset, N, D; output open; N’ D’ + Reset
reg open; reg state; // state register Reset
reg next_state;
parameter zero = 0, five = 1, ten = 2, fifteen = 3;
0¢
N’ D’
always @(N or D or state) [0]
case (state)
zero: begin N
if (D) next_state = five;
D 5¢
else if (N) next_state = ten; N’ D’
else next_state = zero; [0]
open = 0;
N
end
… 10¢
fifteen: begin D N’ D’
[0]
if (!Reset) next_state = fifteen;
else next_state = zero; N+D
open = 1;
end 15¢
endcase Reset’
[1]
always @(posedge clk)
if (Reset || (!N && !D)) state <= zero;
else state <= next_state;
endmodule
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 23
7
Mealy Verilog FSM for Vending Machine
module vending (open, Clk, Reset, N, D);
input Clk, Reset, N, D; output open;
Reset/0 (N’ D’ + Reset)/0
reg open; reg state; // state register
reg next_state; reg next_open;
parameter zero = 0, five = 1, ten = 2, fifteen = 3;
0¢ N’ D’/0
always @(N or D or state)
case (state)
N/0
zero: begin
if (D) begin
D/0 5¢ N’ D’/0
next_state = ten; next_open = 0;
end
else if (N) begin N/0
next_state = five; next_open = 0;
end
else begin D/1 10¢ N’ D’/0
next_state = zero; next_open = 0;
end N+D/1
end
…
15¢ Reset’/1
endcase
always @(posedge clk)
if (Reset || (!N && !D)) begin state <= zero; open <= 0; end
else begin state <= next_state; open <= next_open; end
endmodule
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 24
7
13. Example: Traffic Light Controller
! A busy highway is intersected by a little used farmroad
! Detectors C sense the presence of cars waiting on the farmroad
" with no car on farmroad, light remain green in highway direction
" if vehicle on farmroad, highway lights go from Green to Yellow to Red,
allowing the farmroad lights to become green
" these stay green only as long as a farmroad car is detected but never
longer than a set interval
" when these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green
" even if farmroad vehicles are waiting, highway gets at least a set
interval as green
! Assume you have an interval timer that generates:
" a short time pulse (TS) and
" a long time pulse (TL),
" in response to a set (ST) signal.
" TS is to be used for timing yellow lights and TL for green lights
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 25
Example: Traffic Light Controller
(cont’d)
! Highway/farm road intersection
farm road
car sensors
highway
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 26
14. Example: Traffic Light Controller
(cont’d)
! Tabulation of Inputs and Outputs
inputs description outputs description
reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights
C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights
TS short time interval expired ST start timing a short or long interval
TL long time interval expired
! Tabulation of unique states – some light configurations
imply others
state description
S0 highway green (farm road red)
S1 highway yellow (farm road red)
S2 farm road green (highway red)
S3 farm road yellow (highway red)
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 27
Example: Traffic Light Controller
(cont’d)
! State Diagram Reset
(TL•C)'
S0
TS / ST
S0: HG TL•C / ST
S1: HY TS' S1 S3 TS'
S2: FG
S3: FY TS / ST TL+C' / ST
S2
(TL+C')'
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 28
15. Example: Traffic Light Controller
(cont’d)
! Generate state table with symbolic states
! Consider state assignments output encoding – similar problem
to state assignment
(Green = 00, Yellow = 01, Red = 10)
Inputs Present State Next State Outputs
C TL TS ST H F
0 – – HG HG 0 Green Red
– 0 – HG HG 0 Green Red
1 1 – HG HY 1 Green Red
– – 0 HY HY 0 Yellow Red
– – 1 HY FG 1 Yellow Red
1 0 – FG FG 0 Red Green
0 – – FG FY 1 Red Green
– 1 – FG FY 1 Red Green
– – 0 FY FY 0 Red Yellow
– – 1 FY HG 1 Red Yellow
SA1: HG = 00 HY = 01 FG = 11 FY = 10
SA2: HG = 00 HY = 10 FG = 01 FY = 11
SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot)
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 29
Traffic Light Controller Verilog
(TL•C)' Reset
module traffic (ST, Clk, Reset, C, TL, TS);
input Clk, Reset, C, TL, TS; output ST;
reg ST; reg state;
reg next_state; reg next_ST; S0
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
TL•C TS / ST
always @(C or TL or TS or state)
case (state) TL+C / ST
S0: if (!(TL && C)) begin
next_state = S0; next_ST = 0; TS' S1 S3 TS'
else if (TL || C) begin
next_state = S1; next_ST = 1;
end
… TS / ST TL+C' / ST
endcase
S2
always @(posedge Clk) (TL+C')'
if (Reset) begin state <= S0; ST <= 0; end
else begin state <= next_state; ST <= next_ST; end
endmodule
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 30
17. Vending Machine (cont’d)
! OPEN = Q1Q0 creates a combinational delay after Q1 and Q0
change
! This can be corrected by retiming, i.e., move flip-flops and logic
through each other to improve delay
! OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
! Implementation now looks like a synchronous Mealy machine
" Common for programmable devices to have FF at end of logic
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 33
Vending Machine (Retimed PLD
Mapping)
OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
CLK
Q0
DQ
Seq
N
Q1
DQ
Seq
D
OPEN Open
DQ
Seq
Reset
CS 150 - Spring 2007 – Lec #7: Sequential Implementation – 34
18. Sequential Logic Implementation
Summary
! Models for representing sequential circuits
" Abstraction of sequential elements
" Finite state machines and their state diagrams
" Inputs/outputs
" Mealy, Moore, and synchronous Mealy machines
! Finite state machine design procedure
" Verilog specification
" Deriving state diagram
" Deriving state transition table
" Determining next state and output functions
" Implementing combinational logic
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