Most digital systems found in practice include memory elements, which require the system to be described in terms of sequential logic.

1. SEQUENTIAL LOGIC DESSIGN
with VHDL
PABLO ANDRÉS SANCHEZ
JOHN ALARCÓN

2. INTRODUCTION
MOST DIGITAL SYSTEMS FOUND IN PRACTICE INCLUDE MEMORY
ELEMENTS, WHICH REQUIRE THE SYSTEM TO BE DESCRIBED IN
TERMS OF SEQUENTIAL LOGIC.

3. Sequential Logic Dessign
A SEQUENTIAL SYSTEM IS FORMED BY A COMBINATIONAL CIRCUIT
AND A MEMORY ELEMENT MANAGER TEMPORARILY STORE THE
HISTORY OF THE SYSTEM.
IN ESSENCE, THE OUTPUT OF A SEQUENTIAL SYSTEM DEPENDS NOT
ONLY ON THE PRESENT VALUE ON THE INPUTS AT A GIVEN
MOMENT, BUT ALSO THE HISTORY OF THE SYSTEM.
IT IS SAID THAT THE SEQUENTIAL CIRCUITS ARE MEMORY WHILE
COMBINATIONAL HAVE NO MEMORY.

4. Types
SYNCHRONOUS:
THEIR BEHAVIOR IS SYNCHRONIZED WITH THE SYSTEM CLOCK
PULSE (CLK).
ASYNCHRONOUS:
ITS OPERATION DEPENDS ON THE ORDER AND TIME WHEN THE
INPUT SIGNALS ARE APPLIED

5. FLIP FLOP´s
THE MEMORY ELEMENT USED IN THE DESIGN OF SYSTEMS SYNCHRONOUS OR ASYNCHRONOUS
IT KNOWN AS FLIP FLOP. THE MAIN FEATURE OF A FLIP FLOP IS TO MAINTAIN OR STORE A BIT
INDEFINITELY UNTIL A PULSE OR SIGNAL CHANGES STATE.
FLIP FLOP THE BEST KNOWN ARE THE TYPES SR, JK, T AND D. THE FIGURE PRESENTED EACH OF
THESE ELEMENTS AND THE TRUTH TABLE THAT DESCRIBES ITS OPERATION.

6. Storage Registers
THEY SHOW A SIMILAR STRUCTURE FLIP FLOPS. THE DIFFERENCE IS
THAT STORE THE STATE OF A BIT VECTOR RATHER THAN A SINGLE
BIT.

7. Counters
IN ESSENCE IT´S A REGISTER THAT GOES THROUGH A DETERMINED
SEQUENCE OF STATES, AFTER APPLICATION OF INPUT PULSES.
ONDULATION COUNTERS
THIS COUNTER TRANSITION FROM AN OUTPUT OF FLIP FLOP SERVES AS A
SOURCE FOR FIRING ANOTHER FLIP FLOP (AT THE CLOCK INPUT)
SYNCHRONOUS COUNTER
IN SUCH COUNTER ALL FLIP FLOP HAVE THEIR CLOCK INPUTS SHORTED TO
THE SAME SIGNAL CLK. CHANGE THE STATE OF A FLIP FLOP PARTICULARLY
IT DEPENDS ON THE PRESENT STATE OF OTHER FLIP FLOP

8. Designing a State Machine
1. FINITE STATE MACHINE (FSM) CAN BE
DESCRIBED IN VHDL IN VARIOUS WAYS.
2. FIRST IN THE DECLARATIONS
SECTION OF ARCHITECTURE, AN
ENUMERATED TYPE IN WHICH
IDENTIFIERS ARE ASSIGNED TO EACH
STATE IS DEFINED.
3. GENERALLY BEST TO USE
ILLUSTRATIVE IDENTIFIERS FOR STATES.
4. SYNTHESIS TOOL WILL BE RESPONSIBLE
FOR CODING THESE STATES.
5. SUBSEQUENTLY, IN THE BODY OF THE
ARCHITECTURE STATE TRANSITION
FUNCTION IT DEFINED (F) AND OUTPUT
FUNCTION (G) IN ONE OR MORE PROCESSES.
6. THEREFORE WE HAVE:
• A SEQUENTIAL PROCESS MODELING BISTABLE STATE; SO THAT UPDATES THE STATE (STATE).
• A COMBINATIONAL PROCESS MODELING FUNCTIONS F AND G; THEREFORE DERIVES THE NEXT
STATE (ESTADO_SIG) AND UPDATES THE OUTPUT (O).