ReWArDS - NECSTTechTalk 11/06/2020
Hardware accelerators are an effective solution to increase the performance of algorithms in a wide array of disciplines, from Data Science to Scientific Calculus. However, data scientists and mathematicians often do not have the required knowledge or time to fully exploit these accelerators, and they perceive them as difficult and frustrating to use. Furthermore, Artificial Neural Networks are becoming the base of many of these applications, both in embedded and in server-class contexts. While Graphics Processing Units (GPUs) are predominantly used for training, solutions for inference often rely on Field Programmable Gate Arrays (FPGAs) since they are more flexible and cost-efficient in many scenarios. The main goal is employing FPGA systems for processing huge quantities of data, that may be analyzed in real time, in order to provide a ready-to-use valuable solution to data scientists and mathematicians and applying FPGA systems to machine learning and AI applications to have a power efficient solution for complicated analytics problems.
Recommended
More Related Content
Similar to ReWArDS - NECSTTechTalk 11/06/2020
Similar to ReWArDS - NECSTTechTalk 11/06/2020 (20)
More from NECST Lab @ Politecnico di Milano
More from NECST Lab @ Politecnico di Milano (20)
Recently uploaded
Recently uploaded (20)
ReWArDS - NECSTTechTalk 11/06/2020
- 1. ReWArDS Reconfigurable hardWare for Artificial intelligence and Data Science Luca Stornaiuolo luca.stornaiuolo@polimi.it 11/06/2020 NECST Talk – Sala Seminari
- 4. Context Definition35 Huge amount of data that need to be processed to get aggregated information in real-timeSmart Embedded Systems
- 6. Context Definition37 Performance Energy Efficiency Flexibility Ease of Development GPU ASIC CPU FPGA
- 7. Context Definition38 Performance Energy Efficiency Flexibility Ease of Development GPU ASIC CPU FPGA Performance Energy Efficiency Flexibility Ease of Development GPU ASIC CPU FPGA
- 8. ReWArDS
- 9. 40 ReWArDS
- 10. 41 ReWArDS DS
- 14. HLSPolyMem45 DDRSDRAMmemory Memory HierarchyFPGA Device L. Stornaiuolo, M. Rabozzi, D. Sciuto, M. D. Santambrogio, G. Stramondo, C. Ciobanu, A. L. Varbanescu
- 15. HLSPolyMem46 DDRSDRAMmemory Memory HierarchyFPGA Device Poly Mem L. Stornaiuolo, M. Rabozzi, D. Sciuto, M. D. Santambrogio, G. Stramondo, C. Ciobanu, A. L. Varbanescu
- 16. 47 HLSPolyMem 1 4 9 12 14 17 19 22 27 30 32 35 2 5 7 10 15 18 20 23 25 28 33 36 3 6 8 11 13 16 21 24 26 29 31 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 4 7 10 13 16 19 22 25 28 31 34 2 5 8 11 14 17 20 23 26 29 32 35 3 6 9 12 15 18 21 24 27 30 33 36 HLS Array Partitioning Block HLS Array Partitioning Cyclic PolyMem RoCo Scheme 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Input Matrix
- 19. 50 FaceDetection on multi-PYNQ Anna Maria Nestorov, Alberto Scolari, Enrico Reggiani, Marco D. Santambrogio
- 20. 51 FaceDetection on multi-PYNQ Anna Maria Nestorov, Alberto Scolari, Enrico Reggiani, Marco D. Santambrogio Xilinx Pynq FPG A Xilinx Pynq FPG A Xilinx Pynq FPG A Xilinx Pynq FPG A Stage1 Stage2_2 Stage3 Stage4 Stage5 Xilinx Pynq FPGA Xilinx Pynq FPGA Stage2_1 Xilinx Pynq FPGA Xilinx Pynq FPGA Xilinx Pynq FPGA Xilinx Pynq FPGA
- 21. 52 FaceDetection on multi-PYNQ FPGA Single PYNQ vs ARM Single PYNQ: 14.7× FPGA Distributed System vs ARM Distributed System: 39.5× FPGA Distributed System vs GPU: 0,082×
- 22. 53 FaceDetection on multi-PYNQ FPGA Single PYNQ vs ARM Single PYNQ: 16.2× FPGA Distributed System vs ARM Distributed System: 44× FPGA Distributed System vs GPU: 1.3× FPGA Single PYNQ vs ARM Single PYNQ: 14.7× FPGA Distributed System vs ARM Distributed System: 39.5× FPGA Distributed System vs GPU: 0,082×
- 25. 56 Giorgia Fiscaletti, Marco Speziali, Luca Stornaiuolo , Marco D. Santambrogio CnvW2A2 • 6 Convolutional Layers • 3 Fully-Connected Layers [1] BNN-PYNQ Quantized Neural Network (QNN) on PYNQ
- 26. 57 Minimize Data per Image on the Network Splitting Strategy
- 27. 58
- 28. 59
- 29. 60
- 32. 63 numPYNQ Overlay Correlation Matrix Dot Product FFT Transparent Hardware Acceleration on Zynq SoC for Python Data Science Applications Luca Stornaiuolo, Riccardo Pressiani, Filippo Carloni, Marco D. Santambrogio, Donatella Sciuto
- 35. 66 numPYNQ
- 36. 67 numPYNQ Transparent Hardware Acceleration on Zynq SoC for Python Data Science Applications 12.4x 5.5x Luca Stornaiuolo, Riccardo Pressiani, Filippo Carloni, Marco D. Santambrogio, Donatella Sciuto
- 40. ReWArDS Reconfigurable hardWare for Artificial intelligence and Data Science https://necst.it/ https://www.slideshare.net/necstlab 11/06/2020 NECST Talk – Sala Seminari