This document presents the architecture and implementation of a customized instruction set for tiled regular expressions matching, aimed at improving flexibility and performance. It discusses various components including a regular expression compiler, performance analysis on different architectures, and the proposed multi-core solution implemented on an FPGA. The results demonstrate significant speedups compared to traditional approaches, highlighting the advantages of the custom design.

1. TiReX: Tiled Regular eXpressions
matching architecture
Virtual NGC - Taverne d’Arbia (SI)
July 19, 2020
Filippo Carloni, Davide Conficconi, Alessandro Comodi, Alberto Scolari, Marco Santambrogio
{filippo.carloni, alessandro.comodi} @mail.polimi.it,
{davide.conficconi, alberto.scolari, marco.santambrogio} @polimi.it

2. 2
Context Definition

3. 3
Context Definition
Search Engine
Web PagesUsers

4. 4
Context Definition
Search Engine
Web Pages
Packets Analysis
Accepted
Packets
Rejected
Packets
Entering
PacketsUsers

5. 5
Context Definition
Search Engine
Web Pages
Packets Analysis
Accepted
Packets
Rejected
Packets
Entering
Packets
Genetic Market Research
Patient DNA Personalized MedicineDNA Analysis
Users

6. 6
Context Definition
Regular Expressions
(ACGT|AC)*TT

7. 7
Current Issues
Flexibility
Performance

8. 8
Current Issues
Flexibility
Performance
Possible Solution

9. 9
Related Works
NFA Directly implemented
Fixed architecture relative to one RE
Very fast
Too Space for the NFA for large RE
One character at time for base
implementation

10. 10
Proposed Solution
Customized Instruction Set Architecture (ISA)
Custom processor written in VHDL and implemented on a FPGA
Multi-core architecture

11. 11
Flow of RE
Regular
Expression
Compiler
1 & ACGT
2 JIM offset
3 (
4 |)* AC
5 & TT
ACGTCGGGGCGTGCAAATGCCCCGTGCGATTTGCGTGACGTCGGGGCGTGCAAATGCCCC
GTGCGATTTGCGTGACGTCGGGGCGTGCAAATGCCCCGTGCGATTTGCGTGACGTCGGGG
CGTGCAAATGCCCCGTGCGATTTGCGTGCGTGCGATTTGCGTGACGTCGGGGCGTGCAAA
CGTGCGATTTGCGTGACGTCGGGGCGTGCAAAGCTCGATCGATCGATCGA.
Data
Instruction
Set
Match results

12. 12
The Compiler
Regular Expression Compiler
1 & ACGT
2 JIM
offset
3 (
4 |)* AC
5 & TT
Instruction Set
(ACGT|AC)*TT
1. Lexical Analyzer
2. Code Transformation
3. Code Optimization

13. 13
Single Core
Architecture

14. 14
Board Test 1 Test 2 Test 3
Flex
Intel i7, 2.80 GHz
Exec. Time [µs] 271 121 263
Speedup 1X 1X 1X
Grep (Xeon)
Exec. Time [µs] 205 108.11 336.73
Speedup 1.32X 1.11X 0.78X
PYNQ-Z1
8-core, 70.5 MHz
Exec. Time [µs] 7.2 8.21 30.3
Speedup 37.63X 14.73X 8.67X
VC707
16-core, 130.1 MHz
Exec. Time [µs] 2.07 4.54 3.36
Speedup 130.9X 26.65X 78.27X
VU9P (AWS)
16-core, 202.7 MHz
Exec.Time [µs] 1.03 0.75 2.96
Speedup 263.11X 161.33X 88.85X
Performance Analysis
Latency Dataset
Baseline

15. 15
Summary
Fast
Flexible (Customized ISA)
Cross-Platform Design
Strength Points
Multi-core possibility

16. 16
Summary
Fast
Flexible (Customized ISA)
Cross-Platform Design
Strength Points
Multi-core possibility
Cover more types of regular
expression
Fix corner case bugs
Work in progress ...
Nondeterministic version

17. 17
Thank you
Questions?
Contacts
Filippo Carloni, Davide Conficconi, Alessandro Comodi, Alberto Scolari, Marco Santambrogio
{filippo.carloni, alessandro.comodi} @mail.polimi.it,
{davide.conficconi, alberto.scolari, marco.santambrogio} @polimi.it