1. SHASHI PRABHA SINGH
39, Awani Bihar,
Meerut Road, Ghaziabad,
UP - 201002
Email: spshashiprabha8@gmail.com
Mobile: +91 8800285062
I am seeking an opportunity that will enable me to utilize my knowledge and expertise in different areas while
constantly challenging me. A challenging and rewarding carrier in corporate sector where my skills get sharp
through continuous learning and growth opportunities.
 Operating
System
 MS Office
:
:
Windows (XP, Vista, 7, 8), Linux Ubuntu
Word, Excel, Power point
 Skills : VHDL, Verilog, Elementary knowledge of System Verilog, Tanner & Cadence
 Area of Interests : Digital Electronics, VHDL
 PROJECT: Implementation of Parallel Multiplier Accumulator Based on Radix-2 Modified Booth
Algorithm
 Technology : Xilinx-ISE Design Suite 13.2, Modelsim SE 6.5
 Duration : May 2015- Oct 2015
 Project Guide : Asst. Prof. Uma Sharma, AKGEC
 Description : The project describe about a new multiplier and accumulator architecture for low
Examination Discipline/
Specialization
School/college
Board/
University
Year of
Passing
%
M. Tech VLSI Design
Ajay Kumar Garg Engineering
College, Ghaziabad
UPTU 2015 76.6%
B. Tech
Electronics &
Communication
Engineering
Shri Ram Murti Smarak
Women’s College of Engg. &
Tech., Bareilly
UPTU 2013 73.4%
Intermediate Science + Maths
Stream
Sacred Heart’s Sr. Sec Public
School, Bareilly
C.B.S.E. Board 2009 72.4%
High school Science + Maths
Lohia H S School,
Sahawan, Deoria
U.P. Board 2006 74.8%
OBJECTIVE
EDUCATIONAL QUALIFICATION
M. TECH (PROJECTS & TRAINING)
TECHNICAL EXPERTISE

2. power and high speed arithmetic. High speed low power MAC units are required for
application of digital signal processing.
 TRAINING 2015
 Technology : Verilog, System Verilog
 Duration : 7 Weeks
 Organization : DUCAT, Noida
 Project : Seven Segment Display
 Project Guide : Mr. Harsh Parela, Senior Corporate Trainer.
 PROJECT: Digital Phase Selector
 Course Name : Microcontroller
 Organization : SRMSWCET, Bareilly
 Duration : 1 Year
 Brief description : When any of the mains phase lines fails, it automatically selects the available phase
line (out of three phase lines or backup lines).
 TRAINING 2012
 Organization : Signal & Telecommunication Department
 Location : Bareilly
 Duration : 12-06-12 to 26-07-12
 Brief description : This is all about the Railnet, Telecommunication & Networking.

 Industrial visit at “CDAC” Noida.
 Industrial visit at “Coel-el Technologies” Gurgaon.
 Attended a National Conference on "Wireless Communication in Electronics and Communication
Engineering" AKGEC, Ghaziabad.
 Attended a Faculty Development Program on "Recent Trend & Embedded System Design in
Communication in Electronics and Communication Engineering” AKGEC, Ghaziabad.
 Attended a one day workshop on “VHDL and Verilog” AKGEC, Ghaziabad.
 Attended a two days advance workshop on “Layout Design using Cadence Virtuoso Tool” IEC,
Ghaziabad.
 Participated in Workshop of “Circuit Designing & Simulation” conducted at SRMSWCET, Bareilly.
 Attended a Seminar on "Multiprotocol Lebel Switching” AKGEC, Ghaziabad.
 First prize in primary Group of second District level “Pratibha Khoj Pratiyogita” Bhatni, Deoria at
school level.
 Active part in 200m. Race & 4*100 m. Relay Race & got 3rd
prize in Annual Sports Meet in 12th
standard.
 Active part in “Story Scketching” at the National Level Cultural “Zest” in college fests.
 Attended national level technical fest “Techvyom”.
 Active part in “Essay Writing Competition” on the occasion of 60th
Independence Day at school level.
SEMINAR/WORKSHOP/CONFERENCES
ACHIEVEMENTS
EDUCATIONAL QUALIFICATION
EXTRA CURRICULAR
EDUCATIONAL QUALIFICATION
B. TECH (PROJECTS & TRAINING)

3.  Ability to work in a team
 Problem solving and logical abilities
 Willingness to work hard
 Ability to Learn
 Shashi Prabha Singh, Uma Sharma, “Implementation of Parallel Multiplier Accumulator based on Radix-
2 Modified Booth Algorithm”, International Journal for Scientific Research & Development, Vol. 3,
Issue 05, pp. 301-305, July 2015, ISSN 2321-0613.
Date of Birth : 16-08-1992
Father’s Name : Mr. Virendra Singh
Gender : Female
Hobbies : Playing Badminton
Marital Status : Unmarried
Nationality
Language Known
:
:
India
Hindi & English
I do her eb y confir m t hat t he infor mat ion fur nis hed ab ove is tru e t o t he b est of my
knowledge a nd b elief.
Date : 28 / 08 /2015
Place : Ghaziabad Shashi Prabha Singh
PERSONAL INFORMATION
INTEREST & ACHIEVEMENTS
EDUCATIONAL QUALIFICATION
EDUCATIONAL QUALIFICATION
PERSONAL TRAITS
INTEREST & ACHIEVEMENTS
EDUCATIONAL QUALIFICATION
EDUCATIONAL QUALIFICATION
INTERNATIONAL JOURNAL
DECLRATION
INTEREST & ACHIEVEMENTS
EDUCATIONAL QUALIFICATION
EDUCATIONAL QUALIFICATION