IC Design of Power Management Circuits (IV)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
IC Design of Power Management Circuits (IV)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
How to Identify and Prevent ESD Failures using PathFinderAnsys
This presentation provides an introduction to common ESD failure mechanism in today's ICs and the challenges in addressing them. It will highlight PathFinder, a layout based ESD integrity analysis platform with an integrated modeling, extraction and simulation environment that enables IC designers perform exhaustive verification of all ESD discharge pathways at the IP and full-chip level. It will also share case study of some real life ESD failure scenarios and how PathFinder was used to root-cause them. It reviews the list of ESD checks that can be performed from early floor planning to final sign-off for ESD robustness and ESD failure prevention. Learn more on our website: https://bit.ly/1vRDycB
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
Setup and hold time violation in flip-flopsJong Hwan Shin
When using a flip-flop, flip-flop should have constant input during setup time and hold time. This slide explains setup time violation and hold time violation in flip-flops.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and Fin...Sofics
Sofics presentation (B2.2) at the 1st International EOS/ESD Symposium on Design and System (IEDS). IEDS is dedicated to the fundamental understanding of issues related to electrostatic discharge on design and system and the application of this knowledge to the solution of problems.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
How to Identify and Prevent ESD Failures using PathFinderAnsys
This presentation provides an introduction to common ESD failure mechanism in today's ICs and the challenges in addressing them. It will highlight PathFinder, a layout based ESD integrity analysis platform with an integrated modeling, extraction and simulation environment that enables IC designers perform exhaustive verification of all ESD discharge pathways at the IP and full-chip level. It will also share case study of some real life ESD failure scenarios and how PathFinder was used to root-cause them. It reviews the list of ESD checks that can be performed from early floor planning to final sign-off for ESD robustness and ESD failure prevention. Learn more on our website: https://bit.ly/1vRDycB
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
Setup and hold time violation in flip-flopsJong Hwan Shin
When using a flip-flop, flip-flop should have constant input during setup time and hold time. This slide explains setup time violation and hold time violation in flip-flops.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and Fin...Sofics
Sofics presentation (B2.2) at the 1st International EOS/ESD Symposium on Design and System (IEDS). IEDS is dedicated to the fundamental understanding of issues related to electrostatic discharge on design and system and the application of this knowledge to the solution of problems.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
The MOSFET is an important element in embedded system design which is used to control the loads as per the requirement. The MOSFET is a high voltage controlling device provides some key features for circuit designers in terms of their overall performance.
Practical setup of power electronics lab power semicondutor devices [ scr, m...SHOEBSHAH
Some common power devices are the power diode, thyristor, power MOSFET, and IGBT. The power diode and power MOSFET operate on similar principles to their low-power counterparts, but are able to carry a larger amount of current and are typically able to support a larger reverse-bias voltage in the off-state.
Structural changes are often made in a power device in order to accommodate the higher current density, higher power dissipation, and/or higher reverse breakdown voltage. The vast majority of the discrete (i.e., non-integrated) power devices are built using a vertical structure, whereas small-signal devices employ a lateral structure. With the vertical structure, the current rating of the device is proportional to its area, and the voltage blocking capability is achieved in the height of the die. With this structure, one of the connections of the device is located on the bottom of the semiconductor die.
Flexible 1.36 inch 16*128 SPI SSD1316 Monochrome OLED Screen Module PanelShawn Lee
MPU Serial Interface (3-wire SPI)
The 3-wire serial interface consists of serial clock SCLK, serial data SDIN, and CSB.
There are altogether 9-bits that will be shifted into the shift register on every ninth clock in sequence: D/C bit, D7 to D0 bit.
The D/C bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM (D/C bit = 1) or the command register (D/C bit = 0).
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セル生産方式におけるロボットの活用には様々な問題があるが,その一つとして 3 体以上の物体の組み立てが挙げられる.一般に,複数物体を同時に組み立てる際は,対象の部品をそれぞれロボットアームまたは治具でそれぞれ独立に保持することで組み立てを遂行すると考えられる.ただし,この方法ではロボットアームや治具を部品数と同じ数だけ必要とし,部品数が多いほどコスト面や設置スペースの関係で無駄が多くなる.この課題に対して音𣷓らは組み立て対象物に働く接触力等の解析により,治具等で固定されていない対象物が組み立て作業中に運動しにくい状態となる条件を求めた.すなわち,環境中の非把持対象物のロバスト性を考慮して,組み立て作業条件を検討している.本研究ではこの方策に基づいて,複数物体の組み立て作業を単腕マニピュレータで実行することを目的とする.このとき,対象物のロバスト性を考慮することで,仮組状態の複数物体を同時に扱う手法を提案する.作業対象としてパイプジョイントの組み立てを挙げ,簡易な道具を用いることで単腕マニピュレータで複数物体を同時に把持できることを示す.さらに,作業成功率の向上のために RGB-D カメラを用いた物体の位置検出に基づくロボット制御及び動作計画を実装する.
This paper discusses assembly operations using a single manipulator and a parallel gripper to simultaneously
grasp multiple objects and hold the group of temporarily assembled objects. Multiple robots and jigs generally operate
assembly tasks by constraining the target objects mechanically or geometrically to prevent them from moving. It is
necessary to analyze the physical interaction between the objects for such constraints to achieve the tasks with a single
gripper. In this paper, we focus on assembling pipe joints as an example and discuss constraining the motion of the
objects. Our demonstration shows that a simple tool can facilitate holding multiple objects with a single gripper.
【DLゼミ】XFeat: Accelerated Features for Lightweight Image Matchingharmonylab
公開URL:https://arxiv.org/pdf/2404.19174
出典:Guilherme Potje, Felipe Cadar, Andre Araujo, Renato Martins, Erickson R. ascimento: XFeat: Accelerated Features for Lightweight Image Matching, Proceedings of the 2024 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) (2023)
概要:リソース効率に優れた特徴点マッチングのための軽量なアーキテクチャ「XFeat(Accelerated Features)」を提案します。手法は、局所的な特徴点の検出、抽出、マッチングのための畳み込みニューラルネットワークの基本的な設計を再検討します。特に、リソースが限られたデバイス向けに迅速かつ堅牢なアルゴリズムが必要とされるため、解像度を可能な限り高く保ちながら、ネットワークのチャネル数を制限します。さらに、スパース下でのマッチングを選択できる設計となっており、ナビゲーションやARなどのアプリケーションに適しています。XFeatは、高速かつ同等以上の精度を実現し、一般的なラップトップのCPU上でリアルタイムで動作します。