1. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads 主講人：虞台文

3. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Kernel Definitions and Objects

4. Windows Kernel

5. Windows Kernel Hardware dependent functions are placed in the kernel.

7. OS’s Machine I am staying on the top of an OS machine .

15. Process Creation Hierarchy Kernel p s . . . . . . . . . OS process user 1 login user j login user n login user processes application processes. Interaction with kernel objects p 1 p n q 1 q m p j child processes

16. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Queue Structures

18. Single-Level Queues Circular Array Implementation Link List Implementation

19. Priority Queues Array indexed by priority

20. Priority Queues Binary heap of priority

21. Priority Queues Binary heap of priority Array implementation of binary heap

22. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Threads

23. Address Spaces Memory Virtual Memory Lowest Address, e.g., 00000000 Highest Address, e.g., FFFFFFFF

24. Address Spaces Memory Virtual Memory OS User Programs Lowest Address, e.g., 00000000 Highest Address, e.g., FFFFFFFF Starting Address of all processes

25. Processes Only one process can be activated at a time. Each process thinks that it owns all memory. Their address spaces are different. OS User Programs OS Process 1 OS Process 2 OS Process n

26. Context Switching Only one process can be activated at a time. Each process thinks that it owns all memory. Context Switching Context Switching OS User Programs OS Process 1 OS Process 2 OS Process n

27. Context Switching Only one process can be activated at a time. Each process thinks that it owns all memory. The context switching among processes, i.e., to change address space, is very time consuming . OS User Programs OS Process 1 OS Process 2 OS Process n

29. Processes and Threads

32. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Implementing Processes and Threads

34. Process Control Block (PCB)

35. Process Identification A system-wide unique identifier.

36. State Vector

37. CPU’s State Contain necessary data, e .g., program counter , data register , and flag register, to restart the process at the point of last interruption.

38. Processor ID To identify the processor that is executing the process. Make sense only for multiprocessor system.

39. Memory Memory map information. Physical Memory  Virtual Memory

40. Status

41. Status Point to the list, e.g., ready list or wait list , on which the process may reside. running ready blocked

44. The Finer State Transition Diagram

45. The Finer State Transition Diagram Active Processes Suspended Processes

46. Creation Tree

47. Creation Tree Point to the PCB of the parent process. A link list of PCBs of the child processes

51. Processes and Threads (Windows 2000) Process Object Handle Table VAD VAD VAD object object Virtual Address Space Descriptors Access Token Thread Thread Thread . . . Access Token

52. Windows 2000 (EPROCESS) Executive Process

53. Kernel Process Block

54. Processes and Threads (Windows 2000) EPROCESS ETHREAD

55. Windows 2000 (ETHREAD)

56. Kernel Thread Block

57. Windows 2000 Thread States

60. Create

61. Create Create ( s0 , m0 , pi , pid ) { p = Get_New_PCB(); pid = Get_New_PID(); p->ID = pid; p->CPU_State = s0; p->Memory = m0; p->Priority = pi; p->Status.Type = ’ready_s’; p->Status.List = RL; p->Creation_Tree.Parent = self; p->Creation_Tree.Child = NULL; insert(self-> Creation_Tree.Child, p); insert(RL, p); Activate(); Scheduler(); } s0 m0 pi pid = Get_New_ PID (); ready_s RL self NULL Get_New_ PCB ();

62. Create Create ( s0 , m0 , pi , pid ) { p = Get_New_ PCB (); pid = Get_New_ PID (); p->ID = pid ; p->CPU_State = s0 ; p->Memory = m0 ; p->Priority = pi ; p->Status.Type = ’ready_s ’; p->Status.List = RL ; p->Creation_Tree.Parent = self ; p->Creation_Tree.Child = NULL ; insert (self-> Creation_Tree.Child, p); insert (RL, p); Activate (); Scheduler (); } The calling process

63. Create Create ( s0 , m0 , pi , pid ) { p = Get_New_ PCB (); pid = Get_New_ PID (); p->ID = pid ; p->CPU_State = s0 ; p->Memory = m0 ; p->Priority = pi ; p->Status.Type = ’ready_s ’; p->Status.List = RL ; p->Creation_Tree.Parent = self ; p->Creation_Tree.Child = NULL ; insert (self-> Creation_Tree.Child, p); insert (RL, p); Activate (); Scheduler (); }

64. Suspend

65. Suspend Suspend ( ) Suspend? We choose not .

66. Suspend Suspend ( pid ) { p = Get_ PCB (pid); s = p->Status.Type; if (( s == ’blocked_a ’)||( s ==’ blocked_s ’)) p->Status.Type = ’ blocked_s ’; else p->Status.Type = ’ ready_s ’; if ( s ==’ running ’) { cpu = p->Processor_ID; p->CPU_State = Interrupt (cpu); Scheduler (); } } returns all registers’ values of the cpu and frees the cpu.

67. Activate

68. Activate Activate ( ) Activate? We choose not .

69. Activate Activate ( pid ) { p = Get_ PCB (pid); if (p->Status.Type == ’ ready_s ’) { p->Status.Type = ’ ready_a ’; Scheduler (); } else p->Status.Type = ’ blocked_a ’; }

70. Destroy We need to release all resources associated with the process. What special action needs to be taken if the process is running ?

71. Destroy Destroy ( ) Killed? We choose to kill child processes .

72. Destroy Kill_Tree (p) { for (each q in p->Creation_Tree.Child) Kill_Tree (q); if (p->Status.Type == ’ running ’) { cpu = p->Processor_ID; Interrupt(cpu); } Remove (p->Status.List, p); Release_all (p->Memory); Release_all (p->Other_Resources); Close_all (p->Open_Files); Delete_PCB (p); } subroutine Kill_Tree ( ) killed Marked the corresponding cpu free.

73. Destroy Kill_Tree (p) { for (each q in p->Creation_Tree.Child) Kill_Tree (q); if (p->Status.Type == ’ running ’) { cpu = p->Processor_ID; Interrupt(cpu); } Remove (p->Status.List, p); Release_all (p->Memory); Release_all (p->Other_Resources); Close_all (p->Open_Files); Delete_PCB (p); } subroutine Kill_Tree ( ) killed

74. Destroy Destroy ( ) Destroy (pid) { p = Get_PCB (pid); Kill_Tree (p); Scheduler (); }

75. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Implementing Sync/Comm Mechanisms

78. The Story (80x86) Memory

79. The Story (80x86) Access resource Memory

80. The Story (80x86) Access resource Lock XCHG Memory

81. The Story (80x86) Access resource Memory

82. The Story (80x86) Access resource Lock XCHG The spin locks Memory

83. The Story (80x86) Access resource Lock XCHG Job Done The spin locks Memory

84. The Story (80x86) Access resource Job Done The spin locks Memory

85. The Story (80x86) Access resource Job Done Lock XCHG The spin locks Memory

86. Test-and-Set CPU Instruction TS ( R , X ) R = X ; X = 0 ; 0 : locked is locked 1 : locked is unlocked Indivisible Atomic A CPU Register A Memory Location (Lock Value) Read (test) lock value Lock (set) the lock Returns the value in R . The lock is always locked after being called.

92. Disallowing Preemption High Priority e.g., ISR Low Priority Shared Resource Low Priority

93. Dead Lock Condition High Priority e.g., ISR Low Priority Shared Resource Low Priority

94. Dead Lock Avoidance Low Priority High Priority e.g., ISR Low Priority Shared Resource Windows uses different implementations.

100. Implementing Monitors (Hoare) c. wait c.signal mutually exclusive access for processes Need a mutex, say mutex . Need a semaphore for processes blocked on c , say condsem_c . Need a semaphore for signaling processes, say urgent . condcnt_c : #processes wait on c urgentcnt : #signalers Initial values: mutex = 1; condsem_c = 0; urgent = 0; condcnt_c = 0; urgentcnt = 0; Internal Data Condition Variables Procedure 1 Procedure 2 Procedure 3

103. Mutual Access of Processes Procedure_body P ( mutex ) if( urgentcnt ) V ( urgent ); else V ( mutex ); Initial values: mutex = 1; condsem_c = 0; urgent = 0; condcnt_c = 0; urgentcnt = 0;

110. Priority Queue with Absolute Wakeup Times Set_LTimer( tn , tdel ) Hardware Timers 103 Wall-clock 12 Countdown p 1 115 p 2 135 p 3 140 p 4 150 Timer Queue TQ

111. Priority Queue with Absolute Wakeup Times Set_LTimer( ?? , 35 ) 103 Wall-clock Hardware Timers 12 Countdown p 1 115 p 2 135 p 3 140 p 4 150 Timer Queue TQ p 5 138 p 3 140 p 4 150 p 1 115 p 2 135 TQ +103 +138

112. Priority Queue with Absolute Wakeup Times 103 Wall-clock 12 Countdown Hardware Timers p 5 138 p 4 150 TQ 104 11 105 10 106 9 107 8 108 7 109 6 110 5 111 4 112 3 113 2 114 1 115 0 p 3 140 p 1 115 p 2 135

113. Priority Queue with Absolute Wakeup Times 115 Wall-clock Countdown Hardware Timers p 5 138 p 4 150 TQ 115 0 20 p 2 135 p 3 140 p 2 135 135 -115 20

114. Priority Queue with Time Differences Hardware Timer Set_LTimer( tn , tdel ) 12 Countdown p 1 15 p 2 20 p 3 5 p 4 10 Timer Queue TQ

115. Priority Queue with Time Differences 12 Countdown Hardware Timer Set_LTimer( ?? , 35 ) 12 32 32 37 37 47 35 p 5 3 p 3 2 p 4 10 p 1 15 p 2 20 TQ 3 2 p 1 15 p 2 20 p 3 5 p 4 10 Timer Queue TQ

116. Priority Queue with Time Differences 12 Countdown Hardware Timers p 5 3 p 4 10 TQ 11 10 9 8 7 6 5 4 3 2 1 0 p 3 2 p 1 15 p 2 20

117. Priority Queue with Time Differences Countdown Hardware Timers p 5 3 p 4 10 0 TQ 20 p 3 2 p 2 20

118. Communication Primitives Memory Memory Process q Process p OS OS Address space for process q Address space for process p The same physical memory used. Different physical memory used. Assume that the communication processes are in the same machine. System Space User Space

119. Communication Primitives OS OS Process q Process p Address space for process q Address space for process p Communication send/receive send/receive can be blocked or nonblocked .

120. Communication Primitives OS OS Process q Process p Address space for process q Address space for process p send(p,m) sbuf receive(q,m) rbuf send/receive can be blocked or nonblocked .

121. Communication Primitives OS OS Process q Process p Address space for process q Address space for process p send(p,m) receive(q,m) send/receive can be blocked or nonblocked . Different address mappings for p and q . How? sbuf rbuf sbuf rbuf

122. Communication Primitives send(p,m) OS OS Process q Process p Address space for process q Address space for process p send(p,m) send/receive can be blocked or nonblocked . sbuf’ sbuf’ sbuf

123. Communication Primitives send(p,m) OS OS Process q Process p Address space for process q Address space for process p receive(q,m) send/receive can be blocked or nonblocked . rbuf sbuf’ sbuf’ rbuf’ rbuf’ sbuf

124. Communication Primitives send(p,m) OS OS Process q Process p Address space for process q Address space for process p receive(q,m) send/receive can be blocked or nonblocked . rbuf sbuf’ sbuf’ rbuf’ rbuf’ sbuf

125. Communication Primitives send(p,m) OS OS Process q Process p Address space for process q Address space for process p receive(q,m) send/receive can be blocked or nonblocked . rbuf sbuf’ sbuf’ rbuf’ rbuf’ sbuf

126. Communication Primitives Copying through system buffers (Processes in the same machine) Use pool of system buffers

127. Communication Primitives Use pool of system buffers Copying accross network (Processes in the different machines)

128. Operating Systems Principles Process Management and Coordination Lecture 4: The Operating System Kernel: Implementing Processes and Threads Interrupt Handling

131. Interrupt Controller (82C59A)

132. Interrupt Controller (82C59A) to CPU Signaled By I/O Devices Interrupt requests are priority-leveled . IH’s of high-priority events can preempt those of lower priority. Interrupt requests are maskable. 80x86 uses STI and CLI to temporarily enable and disable all interrupts, respectively.

133. Interrupt Handling CPU INT Interrupt Controller (e.g., 8259) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Each interrupt has an interrupt service routine ( ISR ). ISR7: . . . . . . . . . . IRET ISR6: . . . . . . . . . . IRET ISR5: . . . . . . . . . . IRET ISR4: . . . . . . . . . . IRET ISR3: . . . . . . . . . . IRET ISR2: . . . . . . . . . . IRET ISR1: . . . . . . . . . . IRET ISR0: . . . . . . . . . . IRET Normal Job stack

134. Interrupt Handling CPU INT Interrupt Controller (e.g., 8259) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Each interrupt has an interrupt service routine ( ISR ). ISR7: . . . . . . . . . . IRET ISR6: . . . . . . . . . . IRET ISR5: . . . . . . . . . . IRET ISR4: . . . . . . . . . . IRET ISR3: . . . . . . . . . . IRET ISR2: . . . . . . . . . . IRET ISR1: . . . . . . . . . . IRET ISR0: . . . . . . . . . . IRET Normal Job Put the value of flag register , and program counter (PC) into the stack. flag * stack PC (*)

135. Interrupt Handling CPU INT Interrupt Controller (e.g., 8259) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Each interrupt has an interrupt service routine ( ISR ). ISR7: . . . . . . . . . . IRET ISR6: . . . . . . . . . . IRET ISR5: . . . . . . . . . . IRET ISR4: . . . . . . . . . . IRET ISR3: . . . . . . . . . . IRET ISR2: . . . . . . . . . . IRET ISR1: . . . . . . . . . . IRET ISR0: . . . . . . . . . . IRET Normal Job Read Interrupt Vector flag * ISR3: Push used registers (PUSHA) . . . . . . . . . . . . . . . . . . . . . . . Pop used registers (POPA) Return from interrupt (IRET) stack PC (*)

136. Interrupt Handling CPU INT Interrupt Controller (e.g., 8259) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Each interrupt has an interrupt service routine ( ISR ). ISR7: . . . . . . . . . . IRET ISR6: . . . . . . . . . . IRET ISR5: . . . . . . . . . . IRET ISR4: . . . . . . . . . . IRET ISR3: . . . . . . . . . . IRET ISR2: . . . . . . . . . . IRET ISR1: . . . . . . . . . . IRET ISR0: . . . . . . . . . . IRET Normal Job flag * ISR3: Push used registers (PUSHA) . . . . . . . . . . . . . . . . . . . . . . . Pop used registers (POPA) Return from interrupt (IRET) stack PC (*)

137. Interrupt Handling CPU INT Interrupt Controller (e.g., 8259) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Each interrupt has an interrupt service routine ( ISR ). ISR7: . . . . . . . . . . IRET ISR6: . . . . . . . . . . IRET ISR5: . . . . . . . . . . IRET ISR4: . . . . . . . . . . IRET ISR3: . . . . . . . . . . IRET ISR2: . . . . . . . . . . IRET ISR1: . . . . . . . . . . IRET ISR0: . . . . . . . . . . IRET Normal Job stack PC (*)

139. The Typical Sequence for Using a Hardware Device ...... ...... ...... Start I/O ...... Do_I/O ...... Interrupt Service Routine Done CPU I/O Processor Interrupt

140. The Typical Sequence for Using a Hardware Device

141. The Typical Sequence for Using a Hardware Device   start I/O       

142. Synchronization Primitives Needed P/V wait/signal

143. Monitor: Object-Oriented Approach Device Driver Implemented Using monitor Called by the processes need to do I/O. Called while I/O completion.

144. Implementing Using Monitor

145. Example: Monitor Clock Server

146. Example: Monitor Clock Server monitor Clock_Server { int tnow; Update_Clock () { . . . tnow = tnow + 1; /* Perhapes update time structure also */ } int Get_Time () { . . . return(tnow); /* Perhaps return some more complex structure instead */ } Set_Clock (int tnew) { . . . tnow = tnew; } }