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ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011



          On Fixed Point error analysis of FFT algorithm
                           Shaik Qadeer1, Mohammed Zafar Ali Khan2, and Syed Abdul Sattar3
                                                1
                                               MJCET/ Electrical, Hyderabad, India
                                                     Email: haqbei@gmail.com
                                                2
                                                  IITH/Electrical, Hyderabad, India
                                                       Email: zafar @iith.ac.in
                                                3
                                                  RITS/Electrical, Hyderabad, India
                                              Email: syedabdulsattar1965@ gmail.com

Abstract—In this correspondence the analysis of overall
quantization loss for the Fast Fourier Transform (FFT)
algorithms is extended to the case where the twiddle factor
word length is different from the register word length. First,
a statistical noise model to predict the Quantization error
after the multiplication of two quantized signals, of different
precision, is presented. This model is then applied to FFT
algorithms. Simulation results, that corroborate the                        Figure1. Additive noise model of quantization loss for same bit
theoretical analysis, are then presented.                                                        width multiplication.

Index Terms— DFT (Discrete Fourier Transform), FFT (Fast
Fourier Transform), DIT (Decimation in Time), and
Quantization loss analysis.

                          I. INTRODUCTION
    The discrete Fourier transforms (DFT) and linear filtering
is among the most fundamental operations in digital signal
processing. The Fast Fourier transform is an algorithm to
efficiently compute the discrete Fourier transform (DFT). It is
a very useful algorithm, playing an important role in various             Figure2. Additive noise model of quantization loss for unequal size
                                                                                               bit width multiplication.
digital signal processing applications from
telecommunication, image processing, radar, sonar to                      The organization of paper is as follows: The multiplier
vibrational analysis and material analysis and etc. In the actual         quantization noise model that takes care of effects of different
hardware design, the accuracy of FFT/IFFT module is an                    bit widths at the inputs is discussed in section II. Application
important design factor of system performance. When it is                 to FFT algorithms is discussed in section III. Section IV
implemented on a digital machine, quantization errors will                gives Simulation results followed by Summary in section V.
arise due to the finite word length of the machine. Theoretical
performance evaluation of signal to quantization noise                             II. GENERALIZED MULTIPLIER MODEL
(SQNR) of different FFT algorithms has been widely reported                   The additive noise model of quantization loss is widely
in previous works, for example [2]-[21]. All this consider the            adopted to measure the effect of the fixed length operations
twiddle factor bit width to be similar to register bit width, as it       in digital signal processing systems [2], [4]. The quantized
simplifies the analysis. However, in many practical cases like            product can be expressed as the sum of an unquantized
fixed point DSP processors [1], the input bit widths are not              product and a uniformly distributed additive quantization
the same, and the theoretical analysis given by [2]-[21] do               noise.
not predict the saturation of the SQNR curve due to the
constant twiddle factor bit width.                                        A. Previous model
    In this paper a model of quantization noise for                          If we consider the multiplication of quantized numbers x  ˆ
multiplication when the input registers have different bit
widths is developed first. The output noise of such a multiplier               ˆ                            ˆ
                                                                          and a of bit width b, the product y is quantized to (b+1) bits,
is then computed. The results are then applied to FFT                             ˆ
                                                                          so that y  Qb [ y ] . The variance of this is given in [6] and the
algorithms and simulation results are presented to verify the             corresponding model is shown in Figure 1.
accuracy of the proposed model
                                                                          B. Proposed model
                                                                             Consider the multiplication of quantized numbers x and
                                                                                                                               ˆ
                                                                                                                                 ˆ
                                                                          a of a bit widths b1 and b2 respectively. The product y is
                                                                          ˆ
  This work is a part of PhD thesis of Shaik Qadeer

© 2011 ACEEE                                                          1
DOI: 01.IJIT.01.03. 508
ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011


                              ˆ
quantized to b3 bits, so that y  Qb 3[ y ] .                                                      2        2      1
                                                                                                x  a 
 Each quantized number a, quantized to bit width b, can be                                                       3N 2
represented as an unquantized number with an additive                                                                                              (8)
quantization noise source e [2], [4] as                                     Substituting equation (8) in equation (7), we obtain
             ˆ
             aae                                     (1)
                                                                                      1  2b 3    1
Where e is a uniformly distributed random variable whose                      2 
                                                                               n        {2           [2  2b 2  2  2b1 ]  2 2 (b1 b 2 ) }
probability density function (pdf) is given in equation (2),
                                                                                     12          3N 2
                                                                                                                                    (9)
                                       2                                                                             ˆ
                                                                            Figure 2 depicts quantized product term y as the product of
and variance is given by 2              12
                                                where
                                                                            quantized inputs with an additive quantization noise source
                                                                            having different bit widths.

                                                                  (2)                           III. APPLICATION TO FFT
                                                                                In this section the generalized multiplier model developed
The quantized product term can be expressed as the product
                                                                            in previous section is applied to FFT. For this case we assume,
of quantized inputs with an additive quantization noise
                                                                            without loss of generality, that x is an input to the FFT, and a
source, e3, as
         ˆ                ˆˆ
         y  Qb 3 [ y ]  xa  e3                                           is the twiddle factor. Then variance of a will be  a 2  1 and
                                                       (3)
                                                                            assuming as in [[2], eqn. 6.4.7], that x and a are uncorrelated
If                then using equation (1) to replace quantized x ,
                                                               ˆ            and x has uniform density in the range ( 1 N , 1 N ) , the
a by their unquantized values we get
ˆ                                                                           variance of noise for each multiplication, given in equation
                                                                            (7), specializes to
                                                                                      1  2b3
       ˆ
       y  ( x  e1)( a  e 2)  e3  xa  n                      (4)         2 
                                                                               n        {2      2 2 2b 2  2  2b1  2  2( b1b 2) }
                                                                                                  x
                                                                                     12
                                                                                                                                                  (10)
where n = e1a+e2x+e1e2+e3 is the noise term. The                            A. Error analysis of Radix-2 FFT algorithm
conditional variance of n given x, a is
                                                                                In this subsection we discuss the variance of QE for Radix-
                                                                            2 FFT algorithm to the case of different register bit width.
       2 2 b 3      2 2 b 2      2 2b1 2 2( b1b 2)                     From the flow graph of the DIT FFT algorithm given in Figure
2 
 n               x2           a2       
        12             12           12        12                            3a, it can be seen that the DFT samples are computed by a
                                                                  (5)
                                                                            series of butterfly computations with a single complex
For the special case when b1 = b2 = b3 = b, we have                         multiplication per butterfly module. Some of the butterfly
                                                                            computations require multiplications by - 1 or -j that we do
                                                                            not treat separately here, to simplify the analysis. From Figure
              2 2 b                                                        3a, it is also observed that in general there are N/2 complex
       2 
        n            {1  x 2  a 2  2 2b }                     (6)
               12                                                           multiplications in first stage, N/4 in the second stage, N/8 in
                 2                 2                                        third stage, and so on, until the last stage, where there is only
Denoting E{ x }   x 2 , E{ a }  a 2 , the variance of n for             one complex multiplication. Following the procedure as in
different bit width input is given by                                       [2], instead of scaling the input samples by 1/N, we can
                                                                            distribute the total scaling of 1/N into each of the FFT stages
                                                                            to avoid overflow i.e. we can scale the input signals at each
        1  2b3
2 
 n        {2      2 2 2b 2   2 2  2b1  2 2( b1b 2) }
                    x             a                                         stage by 1/2. This scaling reduces the variance of QE as
       12                                                                   follows. Each factor of 1/2 reduces the variance of QE by a
                                                                 (7)
                                                                            factor of 1/4. Thus 4(N/2) QE introduced in first stage will
Assuming as in [[2], equation 6.4.7], that x and a are                      reduced the variance by (1/4)ν-1, the 4(N/4) in second stage
uncorrelated and have uniform density in the range ( 1 N , 1 N )           to (1/4)ν-2 , and so on, where is the number of FFT stages.
we have                                                                     Hence, the total variance of the QE at the output of FFT
                                                                            algorithm will be
                                                                                           N 1 1          N 1
                                                                                 2   2 {4(
                                                                                  q     n     )( )  4( )( )  2  ...  4}                      (11)
                                                                                            2 4             4 4
                                                                            which simplifies as [2], we get
                                                                                                            1
                                                                                            2  8 2 {1  ( )  }
                                                                                             q      n                                             (12)
                                                                                                            2
              Figure 3-Flow-graph of the DIT- FFT algorithm.
© 2011 ACEEE                                                            2
DOI: 01.IJIT.01.03. 508
ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011


For large values of N, FFT size, this can be approximated as

                   2  8 2
                    q      n                               (13)

Due to the scaling the input, the variance of the signal at the
output of FFT will become  X 2     1
                                         3N
                                              and SQNR is given
by

                                                           (14)



B. Error analysis of Split radix DIT FFT algorithm
    In this subsection we consider QE for Split radix FFT
algorithm. From the block diagram as shown in Figure 3b, it is
clear that each butterfly computation invloves 2 complex or 8
real multiplications. The number of butterflies from stage k=2
to  is given by

                                                          (15)               Figure 3b-Flow-graph of the SRDIT- FFT algorithm
                                                                                                 for N=32.

and the number of Radix-2 butterflies in stage k=1 is
given by

                                                          (16)

As Radix-2 multiplications are all non-trivials, so need not to
be consider for QE analysis. Now the variance of the QE for
this case for the computation of N-point DFT is given as


                                                          (17)         Figure 4. SQNR comparison chart of Radix-2DIT FFT algorithm
                                                                                     with fixed twiddle factor (10bits).

                                                                             IV. COMPARATIVE SIMULATION RESULTS
which simplifies as [2], we get
                                                                          In order to verify the expression derived in the previous
                                                          (18)        section, a fixed point simulation of SQNR for different FFT
                                                                      size is presented. It is assume that the word length of the
For large values of N, FFT size, this can be approximated as          internal register is same as that of the output register (b1 =
                                                                      b3). Figure 4 shows SQNR of Radix-2 DIT FFT algorithms
                                                          (19)        with the word length of twiddle factor set to 10 bits (b2 = 10),
                                                                      and the internal word length of fixedpoint FFT is swept from
QE for the computation of particular split radix FFT output           8 to 18 bits. FFTs of length 64, 256, 512 and 1024 are simulated.
is                                                                    From the figure it can be observed that the simulated SQNR
                                                                      (denoted by ‘NSim.’ for N-point FFT in Fig. 4) is within 0.5 dB
                                                          (20)
                                                                      of theoretical SQNR (denoted by ‘N- Theory’). Similar
Equation (20) is the noise variance of split radix DIT FFT            simulation for split radix FFT is shown in figure 5. For cross
algorithm due to quantization . SQNR for this case is given           verification figure 6 plots the SQNR as a function of FFT
by                                                                    length for various values of twiddle factor and internal register
                                                                      word lengths. It is observed that the theoretical SQNR is
                                                                      within 0.5 dB of the simulated SQNR. Accordingly, it can be
                                                                      concluded that the simulation results closely match
                                                          (21)
                                                                      theoretical SQNR curves obtained by plotting equation (14).




© 2011 ACEEE                                                      3
DOI: 01.IJIT.01.03. 508
ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011


                                                                         [4] W.-H. Chang and T. Nguyen, “On the Fixed-Point Accuracy
                                                                         Analysis of FFT Algorithms,” IEEE Transactions On Signal
                                                                         Processing, Vol. 56, No. 10, pp. 4673-4682, October 2008.
                                                                         [5] T. Tran, B. Liu, “Fixed-point fast Fourier transform error
                                                                         analysis”, IEEE Trans. on ASSP, 1976, vol.24(6), pp. 563–573.
                                                                         [6] W.-H. Chang and T. Nguyen, “Integer FFT with optimized
                                                                         coefficient sets,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal
                                                                         Processing (ICASSP),pg. 109-112, 2007.
                                                                         [7] T. Kaneko and B. Liu, “Accumulation of roundoff errors in
                                                                         fast Fourier transforms”, J. Ass. Comput. Mach., vol. 17, pp. 537–
                                                                         654, Oct. 1970.
                                                                         [8] C. J. Weinstein, “Roundoff noise in floating point fast Fourier
                                                                         transform computation”, IEEE Trans. Audio Electroacoust., vol.
                                                                         AU-17,pp. 209–215, Sept. 1969.
                                                                         [9] G. U. Ramos, “Roundoff error analysis of the fast Fourier
Figure 5. SQNR comparison chart of Split radix DIT FFT algorithm         transforrn”, Math. Comput., vol. 25, pp. 757-768, Oct. 1971.
               with fixed twiddle factor (10bits).                       [10] S.Y. Park and N.I. Cho, “Fixed point error analysis of CORDIC
                                                                         processor based on the variance propagation formula”, IEEE Trans.
                                                                         Circuits, Sys.I, Reg. Papers,vol. 51,no. 3, pp. 573-584, 2004.
                                                                         [11] Wade Lowdermilk and Fred Harris, “Finite Arithmetic
                                                                         Considerations for the FFT Implemented in FPGA-Based
                                                                         Embedded Processors in Synthetic Instruments”, in IEEE
                                                                         Instrumentation and Measurement Magazine, vol.8, no. 3, pg. 40-
                                                                         46, August 2007.
                                                                         [12] P.D. Welch, “A fixed point fast Fourier transform error
                                                                         analysis”, in IEEE Trans. Audio Electroacoust., vol. AU-17, pp.
                                                                         151–157, June 1969.
                                                                         [13] D.V. James, “Quantization errors in fast Fourier transform”,
                                                                         in IEEE Trans. Acoustics, Speech, Signal Processing, vol. ASSP-
                                                                         23, pp. 277–283, June 1975.
 Figure 6. SQNR comparision of Radix-2DIT FFT algorithms with            [14] A. V. Oppenheim and R. Schafer, “Digital Signal Processing”,
                   fixed input (10,12 bits).                             Chapter-9, Prentice-Hall of India, 2002.
                                                                         [15] Sanjit Mitra, “Digital Signal Processing: A Computer
                       V. CONCLUSION                                     Approach”, 3rd edition, Chapter-12, McGraw-Hill, 2006.
                                                                         [16] C.W. Barnes,B.N. Tran and S.H. Lueng, “On the Statistics of
     We have developed a generalized multiplier model and                Fixed-Point roundoff error,” in IEEE Trans. Acoust., Speech, Signal
applied it to derive the signal to quantization noise for FFT,           Process., vol. ASSP-33, no. 3,June-1985.
for the case when twiddle factor word length is different from           [17] V. Ashok N. and K.N.N. Prabhu,”The fractional Fourier
register word length. The results obtained are an important              transform: theory, implementation and error analysis”, in Elsevier
basis for the implementation of the FFT algorithm. Simulation            Journal on Microprocessors and Microsystems, vol. 27 , pp.511-
results indicate that the theoretical analysis agrees closely            521, 2003.
with the actual behavior of SQNR.                                        [18] D. Chandra, “Accumulation of coefficient roundoff error in
                                                                         FFT implemented with logarithmic number system”, in IEEE Trans.
                                                                         Acoust., Speech, Signal Process., vol. 35, no. 11, pp. 1633-1636,
                      ACKNOWLEDGMENT
                                                                         1987.
   The authors wish to thank MJCET for allowing us to                    [19] W. Schlecker, Christiane B. and H. Pfleiderer, “Quantisation
conduct this research. This work was supported in part by a              Noise in Fixed-Point Multiplications,” in Electrical Engineering
partial grant from MJCET.                                                (Archiv fur Elektrotechnik) Volume 89, Number 4, 339-342, DOI:
                                                                         10.1007/s00202-006-0009-3.
                                                                         [20] A. S. Sripad and D. L. Snyder,”A necessary and sufficient
                          REFERENCES                                     condition for quantization errors to be uniform and white,” in IEEE
[1] R. Venketramani and M. Bhaskar, “Digital Signal Processors”,         Trans. Acoust., Speech, Signal Processing, vol. ASSP-25, pp. 442-
Tata McGraW Hill, India, 2007.                                           448, Oct. 1977.
[2] John G. Proakis and D.G. Manolakis, “ Digital Signal                 [21] Z. Lukac and M. Temerinac , “Analysis of some methods For
Processing-Principles, Algorithms, and Applications”, 3rd edition,       maintaining accuracy in implementation of FFT on fixed point
Chapter 6, Prentice Hall of India, 2003.                                 DSP ,” in IEEE conerence, Serbia and Montenegro, Nis, September
[3] R.B. Perlow and T.C. Denk, “Finite Wordlength Design for             28 -30, 2005.
VLSI FFT Processors,” in Conf. Rec. 35th Asilomar Conf. Signals,
Systems, Computers, 2001, vol. 2-2, pp. 1227-1231




                                                                                        A part of paper is presented in CEMC2011
© 2011 ACEEE                                                         4
DOI: 01.IJIT.01.03. 508

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FFT Quantization Error Analysis

  • 1. ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011 On Fixed Point error analysis of FFT algorithm Shaik Qadeer1, Mohammed Zafar Ali Khan2, and Syed Abdul Sattar3 1 MJCET/ Electrical, Hyderabad, India Email: haqbei@gmail.com 2 IITH/Electrical, Hyderabad, India Email: zafar @iith.ac.in 3 RITS/Electrical, Hyderabad, India Email: syedabdulsattar1965@ gmail.com Abstract—In this correspondence the analysis of overall quantization loss for the Fast Fourier Transform (FFT) algorithms is extended to the case where the twiddle factor word length is different from the register word length. First, a statistical noise model to predict the Quantization error after the multiplication of two quantized signals, of different precision, is presented. This model is then applied to FFT algorithms. Simulation results, that corroborate the Figure1. Additive noise model of quantization loss for same bit theoretical analysis, are then presented. width multiplication. Index Terms— DFT (Discrete Fourier Transform), FFT (Fast Fourier Transform), DIT (Decimation in Time), and Quantization loss analysis. I. INTRODUCTION The discrete Fourier transforms (DFT) and linear filtering is among the most fundamental operations in digital signal processing. The Fast Fourier transform is an algorithm to efficiently compute the discrete Fourier transform (DFT). It is a very useful algorithm, playing an important role in various Figure2. Additive noise model of quantization loss for unequal size bit width multiplication. digital signal processing applications from telecommunication, image processing, radar, sonar to The organization of paper is as follows: The multiplier vibrational analysis and material analysis and etc. In the actual quantization noise model that takes care of effects of different hardware design, the accuracy of FFT/IFFT module is an bit widths at the inputs is discussed in section II. Application important design factor of system performance. When it is to FFT algorithms is discussed in section III. Section IV implemented on a digital machine, quantization errors will gives Simulation results followed by Summary in section V. arise due to the finite word length of the machine. Theoretical performance evaluation of signal to quantization noise II. GENERALIZED MULTIPLIER MODEL (SQNR) of different FFT algorithms has been widely reported The additive noise model of quantization loss is widely in previous works, for example [2]-[21]. All this consider the adopted to measure the effect of the fixed length operations twiddle factor bit width to be similar to register bit width, as it in digital signal processing systems [2], [4]. The quantized simplifies the analysis. However, in many practical cases like product can be expressed as the sum of an unquantized fixed point DSP processors [1], the input bit widths are not product and a uniformly distributed additive quantization the same, and the theoretical analysis given by [2]-[21] do noise. not predict the saturation of the SQNR curve due to the constant twiddle factor bit width. A. Previous model In this paper a model of quantization noise for If we consider the multiplication of quantized numbers x ˆ multiplication when the input registers have different bit widths is developed first. The output noise of such a multiplier ˆ ˆ and a of bit width b, the product y is quantized to (b+1) bits, is then computed. The results are then applied to FFT ˆ so that y  Qb [ y ] . The variance of this is given in [6] and the algorithms and simulation results are presented to verify the corresponding model is shown in Figure 1. accuracy of the proposed model B. Proposed model Consider the multiplication of quantized numbers x and ˆ ˆ a of a bit widths b1 and b2 respectively. The product y is ˆ This work is a part of PhD thesis of Shaik Qadeer © 2011 ACEEE 1 DOI: 01.IJIT.01.03. 508
  • 2. ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011 ˆ quantized to b3 bits, so that y  Qb 3[ y ] . 2 2 1 x  a  Each quantized number a, quantized to bit width b, can be 3N 2 represented as an unquantized number with an additive (8) quantization noise source e [2], [4] as Substituting equation (8) in equation (7), we obtain ˆ aae (1) 1  2b 3 1 Where e is a uniformly distributed random variable whose 2  n {2  [2  2b 2  2  2b1 ]  2 2 (b1 b 2 ) } probability density function (pdf) is given in equation (2), 12 3N 2 (9) 2 ˆ Figure 2 depicts quantized product term y as the product of and variance is given by 2   12 where quantized inputs with an additive quantization noise source having different bit widths. (2) III. APPLICATION TO FFT In this section the generalized multiplier model developed The quantized product term can be expressed as the product in previous section is applied to FFT. For this case we assume, of quantized inputs with an additive quantization noise without loss of generality, that x is an input to the FFT, and a source, e3, as ˆ ˆˆ y  Qb 3 [ y ]  xa  e3 is the twiddle factor. Then variance of a will be  a 2  1 and (3) assuming as in [[2], eqn. 6.4.7], that x and a are uncorrelated If then using equation (1) to replace quantized x , ˆ and x has uniform density in the range ( 1 N , 1 N ) , the a by their unquantized values we get ˆ variance of noise for each multiplication, given in equation (7), specializes to 1  2b3 ˆ y  ( x  e1)( a  e 2)  e3  xa  n (4) 2  n {2   2 2 2b 2  2  2b1  2  2( b1b 2) } x 12 (10) where n = e1a+e2x+e1e2+e3 is the noise term. The A. Error analysis of Radix-2 FFT algorithm conditional variance of n given x, a is In this subsection we discuss the variance of QE for Radix- 2 FFT algorithm to the case of different register bit width. 2 2 b 3 2 2 b 2 2 2b1 2 2( b1b 2) From the flow graph of the DIT FFT algorithm given in Figure 2  n  x2  a2  12 12 12 12 3a, it can be seen that the DFT samples are computed by a (5) series of butterfly computations with a single complex For the special case when b1 = b2 = b3 = b, we have multiplication per butterfly module. Some of the butterfly computations require multiplications by - 1 or -j that we do not treat separately here, to simplify the analysis. From Figure 2 2 b 3a, it is also observed that in general there are N/2 complex 2  n {1  x 2  a 2  2 2b } (6) 12 multiplications in first stage, N/4 in the second stage, N/8 in 2 2 third stage, and so on, until the last stage, where there is only Denoting E{ x }   x 2 , E{ a }  a 2 , the variance of n for one complex multiplication. Following the procedure as in different bit width input is given by [2], instead of scaling the input samples by 1/N, we can distribute the total scaling of 1/N into each of the FFT stages to avoid overflow i.e. we can scale the input signals at each 1  2b3 2  n {2   2 2 2b 2   2 2  2b1  2 2( b1b 2) } x a stage by 1/2. This scaling reduces the variance of QE as 12 follows. Each factor of 1/2 reduces the variance of QE by a (7) factor of 1/4. Thus 4(N/2) QE introduced in first stage will Assuming as in [[2], equation 6.4.7], that x and a are reduced the variance by (1/4)ν-1, the 4(N/4) in second stage uncorrelated and have uniform density in the range ( 1 N , 1 N ) to (1/4)ν-2 , and so on, where is the number of FFT stages. we have Hence, the total variance of the QE at the output of FFT algorithm will be N 1 1 N 1  2   2 {4( q n )( )  4( )( )  2  ...  4} (11) 2 4 4 4 which simplifies as [2], we get 1  2  8 2 {1  ( )  } q n (12) 2 Figure 3-Flow-graph of the DIT- FFT algorithm. © 2011 ACEEE 2 DOI: 01.IJIT.01.03. 508
  • 3. ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011 For large values of N, FFT size, this can be approximated as  2  8 2 q n (13) Due to the scaling the input, the variance of the signal at the output of FFT will become  X 2  1 3N and SQNR is given by (14) B. Error analysis of Split radix DIT FFT algorithm In this subsection we consider QE for Split radix FFT algorithm. From the block diagram as shown in Figure 3b, it is clear that each butterfly computation invloves 2 complex or 8 real multiplications. The number of butterflies from stage k=2 to is given by (15) Figure 3b-Flow-graph of the SRDIT- FFT algorithm for N=32. and the number of Radix-2 butterflies in stage k=1 is given by (16) As Radix-2 multiplications are all non-trivials, so need not to be consider for QE analysis. Now the variance of the QE for this case for the computation of N-point DFT is given as (17) Figure 4. SQNR comparison chart of Radix-2DIT FFT algorithm with fixed twiddle factor (10bits). IV. COMPARATIVE SIMULATION RESULTS which simplifies as [2], we get In order to verify the expression derived in the previous (18) section, a fixed point simulation of SQNR for different FFT size is presented. It is assume that the word length of the For large values of N, FFT size, this can be approximated as internal register is same as that of the output register (b1 = b3). Figure 4 shows SQNR of Radix-2 DIT FFT algorithms (19) with the word length of twiddle factor set to 10 bits (b2 = 10), and the internal word length of fixedpoint FFT is swept from QE for the computation of particular split radix FFT output 8 to 18 bits. FFTs of length 64, 256, 512 and 1024 are simulated. is From the figure it can be observed that the simulated SQNR (denoted by ‘NSim.’ for N-point FFT in Fig. 4) is within 0.5 dB (20) of theoretical SQNR (denoted by ‘N- Theory’). Similar Equation (20) is the noise variance of split radix DIT FFT simulation for split radix FFT is shown in figure 5. For cross algorithm due to quantization . SQNR for this case is given verification figure 6 plots the SQNR as a function of FFT by length for various values of twiddle factor and internal register word lengths. It is observed that the theoretical SQNR is within 0.5 dB of the simulated SQNR. Accordingly, it can be concluded that the simulation results closely match (21) theoretical SQNR curves obtained by plotting equation (14). © 2011 ACEEE 3 DOI: 01.IJIT.01.03. 508
  • 4. ACEEE Int. J. on Information Technology, Vol. 01, No. 03, Dec 2011 [4] W.-H. Chang and T. Nguyen, “On the Fixed-Point Accuracy Analysis of FFT Algorithms,” IEEE Transactions On Signal Processing, Vol. 56, No. 10, pp. 4673-4682, October 2008. [5] T. Tran, B. Liu, “Fixed-point fast Fourier transform error analysis”, IEEE Trans. on ASSP, 1976, vol.24(6), pp. 563–573. [6] W.-H. Chang and T. Nguyen, “Integer FFT with optimized coefficient sets,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing (ICASSP),pg. 109-112, 2007. [7] T. Kaneko and B. Liu, “Accumulation of roundoff errors in fast Fourier transforms”, J. Ass. Comput. Mach., vol. 17, pp. 537– 654, Oct. 1970. [8] C. J. Weinstein, “Roundoff noise in floating point fast Fourier transform computation”, IEEE Trans. Audio Electroacoust., vol. AU-17,pp. 209–215, Sept. 1969. [9] G. U. Ramos, “Roundoff error analysis of the fast Fourier Figure 5. SQNR comparison chart of Split radix DIT FFT algorithm transforrn”, Math. Comput., vol. 25, pp. 757-768, Oct. 1971. with fixed twiddle factor (10bits). [10] S.Y. Park and N.I. Cho, “Fixed point error analysis of CORDIC processor based on the variance propagation formula”, IEEE Trans. Circuits, Sys.I, Reg. Papers,vol. 51,no. 3, pp. 573-584, 2004. [11] Wade Lowdermilk and Fred Harris, “Finite Arithmetic Considerations for the FFT Implemented in FPGA-Based Embedded Processors in Synthetic Instruments”, in IEEE Instrumentation and Measurement Magazine, vol.8, no. 3, pg. 40- 46, August 2007. [12] P.D. Welch, “A fixed point fast Fourier transform error analysis”, in IEEE Trans. Audio Electroacoust., vol. AU-17, pp. 151–157, June 1969. [13] D.V. James, “Quantization errors in fast Fourier transform”, in IEEE Trans. Acoustics, Speech, Signal Processing, vol. ASSP- 23, pp. 277–283, June 1975. Figure 6. SQNR comparision of Radix-2DIT FFT algorithms with [14] A. V. Oppenheim and R. Schafer, “Digital Signal Processing”, fixed input (10,12 bits). Chapter-9, Prentice-Hall of India, 2002. [15] Sanjit Mitra, “Digital Signal Processing: A Computer V. CONCLUSION Approach”, 3rd edition, Chapter-12, McGraw-Hill, 2006. [16] C.W. Barnes,B.N. Tran and S.H. Lueng, “On the Statistics of We have developed a generalized multiplier model and Fixed-Point roundoff error,” in IEEE Trans. Acoust., Speech, Signal applied it to derive the signal to quantization noise for FFT, Process., vol. ASSP-33, no. 3,June-1985. for the case when twiddle factor word length is different from [17] V. Ashok N. and K.N.N. Prabhu,”The fractional Fourier register word length. The results obtained are an important transform: theory, implementation and error analysis”, in Elsevier basis for the implementation of the FFT algorithm. Simulation Journal on Microprocessors and Microsystems, vol. 27 , pp.511- results indicate that the theoretical analysis agrees closely 521, 2003. with the actual behavior of SQNR. [18] D. Chandra, “Accumulation of coefficient roundoff error in FFT implemented with logarithmic number system”, in IEEE Trans. Acoust., Speech, Signal Process., vol. 35, no. 11, pp. 1633-1636, ACKNOWLEDGMENT 1987. The authors wish to thank MJCET for allowing us to [19] W. Schlecker, Christiane B. and H. Pfleiderer, “Quantisation conduct this research. This work was supported in part by a Noise in Fixed-Point Multiplications,” in Electrical Engineering partial grant from MJCET. (Archiv fur Elektrotechnik) Volume 89, Number 4, 339-342, DOI: 10.1007/s00202-006-0009-3. [20] A. S. Sripad and D. L. Snyder,”A necessary and sufficient REFERENCES condition for quantization errors to be uniform and white,” in IEEE [1] R. Venketramani and M. Bhaskar, “Digital Signal Processors”, Trans. Acoust., Speech, Signal Processing, vol. ASSP-25, pp. 442- Tata McGraW Hill, India, 2007. 448, Oct. 1977. [2] John G. Proakis and D.G. Manolakis, “ Digital Signal [21] Z. Lukac and M. Temerinac , “Analysis of some methods For Processing-Principles, Algorithms, and Applications”, 3rd edition, maintaining accuracy in implementation of FFT on fixed point Chapter 6, Prentice Hall of India, 2003. DSP ,” in IEEE conerence, Serbia and Montenegro, Nis, September [3] R.B. Perlow and T.C. Denk, “Finite Wordlength Design for 28 -30, 2005. VLSI FFT Processors,” in Conf. Rec. 35th Asilomar Conf. Signals, Systems, Computers, 2001, vol. 2-2, pp. 1227-1231 A part of paper is presented in CEMC2011 © 2011 ACEEE 4 DOI: 01.IJIT.01.03. 508