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module nco ( clk,resetb,step,modmask, ticks, fout);
parameter W_ACCUM = 24;
parameter W_TICK = 8;
parameter W_STEP = 24;
parameter W_MOD = 24;
input clk;
input resetb;
input [W_STEP-1:0] step;
input [W_MOD-1:0] mod;
input [W_TICK-1:0] mask;
output [W_TICK-1:0] ticks;
output fout;
reg [W_ACCUM-1:0] accum, accum_in;
reg [W_TICK-1:0] ticks;
reg wrap;
wire [W_ACCUM-1:0] sum = accum + step;
wire [W_ACCUM-1:0] rem = sum - mod;
wire over = (sum >= mod);
always @(posedge clk or negedge resetb)
if (~resetb) accum <= 0;
else accum <= accum_in;
always @(over or rem or sum) begin
if (over) begin
accum_in <= rem;
wrap <= 1;
end
else begin
accum_in <= sum;
wrap <= 0;
end
end
always @(posedge clk) begin
if (~resetb) ticks <= 0;
else begin
if (wrap)
ticks <= ticks + 1;
end
end
assign fout = |(ticks & mask);
endmodule
module ncotest;
reg clk;
reg resetb;
reg [23:0] step;
reg [23:0] mod;
reg [7:0] mask;
wire fout;
wire [7:0] ticks;
parameter W_ACCUM = 24; parameter W_TICK = 8;
parameter W_STEP = 24;
parameter W_MOD = 24;
nco nco1 (.clk(clk),.resetb(resetb),.step(step),.mod(mod),.mask(mask),.fout(fout),.ticks(ticks));
parameter PERIOD_NS = 36;
parameter DUMP_ON = 1;
real sys_freq;
initial begin
step = 0;
mod = 0;
mask = 8'b00000001;
sys_freq = 1000000000.0/(PERIOD_NS);
#300;
$display ("NCO Test. NCO Accumulator width is %0d bits, system clock period is %0d ns (%fMHz).",
W_ACCUM,
PERIOD_NS,
sys_freq
);
mod = 125 << 12;
step = 9 << 12;
nco_test (mod, step, 1000000);
mod = 3125 << 10;
step = 2304 << 10;
nco_test (mod, step, 1000000);
mask = 8'b10000000;
mod = 500 << 12;
step = (151 << 12) - 9566;
nco_test (mod, step, 1000000);
$display ("Done.");
$finish;
end
task nco_test;
input [23:0] mod_arg;
input [23:0] step_arg;
input interval;
integer interval;
integer start_time;
integer fout_edges;
begin
step = step_arg;
mod = mod_arg;
fout_edges = 0;
start_time = $time;
while ( ($time - start_time) < interval) begin
@(posedge fout);
fout_edges = fout_edges + 1;
end
$display ("For Mod=%0d(0x%h), Step=%0d(0x%h), Frequency of fout = %f Hz, Expected fout is %f Hz.",
mod, mod,
step, step,
((fout_edges*1.0)/($time - start_time))*1000000000.0,
((step*1.0)/(mod*1.0))*(sys_freq)/(mask*2.0)
);
end
endtask
initial begin
clk = 0;
forever begin
#(PERIOD_NS/2) clk = ~clk;
end
end
initial begin
resetb = 0;
#200 resetb = 1;
end
initial begin
if (DUMP_ON) begin
$dumpfile ("nco.vcd");
$dumpvars (0,ncotest);
end
end
endmodule
Module nco rtl

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Module nco rtl

  • 1. module nco ( clk,resetb,step,modmask, ticks, fout); parameter W_ACCUM = 24; parameter W_TICK = 8; parameter W_STEP = 24; parameter W_MOD = 24; input clk; input resetb; input [W_STEP-1:0] step; input [W_MOD-1:0] mod; input [W_TICK-1:0] mask; output [W_TICK-1:0] ticks; output fout; reg [W_ACCUM-1:0] accum, accum_in; reg [W_TICK-1:0] ticks; reg wrap; wire [W_ACCUM-1:0] sum = accum + step; wire [W_ACCUM-1:0] rem = sum - mod; wire over = (sum >= mod); always @(posedge clk or negedge resetb) if (~resetb) accum <= 0; else accum <= accum_in; always @(over or rem or sum) begin if (over) begin accum_in <= rem; wrap <= 1; end else begin accum_in <= sum; wrap <= 0; end end always @(posedge clk) begin if (~resetb) ticks <= 0; else begin if (wrap) ticks <= ticks + 1; end end assign fout = |(ticks & mask); endmodule module ncotest;
  • 2. reg clk; reg resetb; reg [23:0] step; reg [23:0] mod; reg [7:0] mask; wire fout; wire [7:0] ticks; parameter W_ACCUM = 24; parameter W_TICK = 8; parameter W_STEP = 24; parameter W_MOD = 24; nco nco1 (.clk(clk),.resetb(resetb),.step(step),.mod(mod),.mask(mask),.fout(fout),.ticks(ticks)); parameter PERIOD_NS = 36; parameter DUMP_ON = 1; real sys_freq; initial begin step = 0; mod = 0; mask = 8'b00000001; sys_freq = 1000000000.0/(PERIOD_NS); #300; $display ("NCO Test. NCO Accumulator width is %0d bits, system clock period is %0d ns (%fMHz).", W_ACCUM, PERIOD_NS, sys_freq ); mod = 125 << 12; step = 9 << 12; nco_test (mod, step, 1000000); mod = 3125 << 10; step = 2304 << 10; nco_test (mod, step, 1000000); mask = 8'b10000000; mod = 500 << 12; step = (151 << 12) - 9566; nco_test (mod, step, 1000000); $display ("Done."); $finish; end task nco_test; input [23:0] mod_arg; input [23:0] step_arg;
  • 3. input interval; integer interval; integer start_time; integer fout_edges; begin step = step_arg; mod = mod_arg; fout_edges = 0; start_time = $time; while ( ($time - start_time) < interval) begin @(posedge fout); fout_edges = fout_edges + 1; end $display ("For Mod=%0d(0x%h), Step=%0d(0x%h), Frequency of fout = %f Hz, Expected fout is %f Hz.", mod, mod, step, step, ((fout_edges*1.0)/($time - start_time))*1000000000.0, ((step*1.0)/(mod*1.0))*(sys_freq)/(mask*2.0) ); end endtask initial begin clk = 0; forever begin #(PERIOD_NS/2) clk = ~clk; end end initial begin resetb = 0; #200 resetb = 1; end initial begin if (DUMP_ON) begin $dumpfile ("nco.vcd"); $dumpvars (0,ncotest); end end endmodule