The document discusses ARM assembly language basics including: - Common syntax elements like labels, opcodes, operands, and comments. - Instructions for moving data between registers and memory locations. - Pseudo-instructions and data processing instructions for arithmetic, logical, and shift operations. - Memory access instructions for loading and storing data using pre-indexing, post-indexing, and stack operations.

1. Embedded Systems
MODULE 2

2. Assembly Basics
• we introduce some basic syntax of ARM assembly to
make it easier to understand the rest of the code
Assembler Language: Basic Syntax
ARM assembly syntax:
Label:
opcode operand1, operand2, ... ; Comments
• Label is used as a reference to an address location
• Opcode/Mnemonic is the name of the instruction;
• Operand1 is the destination of the operation;
• Operand2 is normally the source of the operation;
• Comments are written after” ; “ , which does not affect the program;
EXAMPLE:

3. Moving immediate data:
MOV R3, #0x11 ; Set register R3 to 0x11
Constants using EQU:
NVIC_IRQ_SETEN0 EQU 0xE000E100;
Use of DCI, DCB, DCD:
• DCI (Define Constant Instruction) can be used to code an instruction if the assembler
cannot generate the exact instruction
DCI 0xBE00 ; → Opcode for Breakpoint (BKPT 0) ,a 16 bit instruction
• DCB (Define Constant Byte) for defining byte size constant values, such as characters;
MY_NUMBER DCD 0x12345678; →MY_NUMBER =0x12345678 , Get the value
code
• DCD (Define Constant Data) for defining word size constant values to define binary
data in your code.
HELLO_TXT DCB "Hellon",0; →HELLO_TXT= Hello Various other instructions will
be explained later on

4. Assembler Language: Use of Suffixes
Table 4.1 Suffixes in Instructions
Suffix Description
S Update Application Program Status register (APSR)
(flags); for example: ADDS R0, R1 ; this will update APSR
EQ, NE, LT, GT, and Conditional execution; EQ = Equal, NE = Not Equal, LT=
Less Than, GT = Greater so on Than, and so forth. For example:
BEQ<Label> ; Branch if equal

5. Assembler Language: Unified Assembler Language
To support and get the best out of the Thumb®-2 instruction set, the Unified Assembler
Language (UAL) was developed to allow selection of 16-bit and 32-bit instructions and to
make it easier to port applications between ARM code and Thumb code by using the same
syntax for both.
ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax
ADD R0, R0, R1 ; Equivalent instruction using UAL syntax
AND R0, R1 ; Traditional Thumb syntax
ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)
ADDS R0, #1 ; Use 16-bit Thumb instruction by default
; for smaller size
ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)

6. Instruction List
The ARM Cortex instruction can be classified into the following:
1. Moving Data
2. Pseudo-Instructions
3.Data processing instructions
4. Call & Unconditional Branch Instructions
5. Decision & Conditional Branch Instructions
6. Combined Compare & Conditional branch Instructions
7. Instruction Barrier & Memory Barrier Instructions
8. Saturation operation Instructions
9. Useful Thumb-2 instruction

7. Move instructions
This can be grouped into the following category:
• Moving Data Between Register And Register
• Moving An Immediate Data Value Into A Register
• Moving Data Between Memory And Register
• Moving Data Between Special Register And Register

8. (a) Moving Data Between Register And Register
MOV R8, R3;
data from R3 goes into R8.
(b) Moving An Immediate data value Into a Register
MOV R0,#0X12
12Hex goes into R0.
MOV R1, # ‘A’
ASCII value of A goes into R1.
MOVS R0, #0X78
Suffix S is used to move 8 bit or less than that into register 78H goes to
R0.
MOVW.W R0,#0X789A
it’s a thumb-2 instruction. Moves 32 bit data 0000789A to R0.
Data 3456789A can be stored in R0 as
MOVW.W R0,#0X789A
moves 789A as LOWER 16-bit data in R0.
MOVT.W R0,#0X3456
moves 3456 as HIGHER 16-bit data in R0.
MOVT
upper 16bits , MOVW
lower 16bits

9. (c) Moving Data Between Memory And Register
The ARM supports memory access via two instructions, LDR and STR
LDRB Rd, [Rn, #offset] Read byte from memory location Rn + offset
(Calculates an address from a base register value & an offset regiter value, Loads a byte
from memory,zero extends it to form a 32 bit word & writes it to a register)
LDRH Rd, [Rn, #offset] Read half word from memory location Rn + offset
LDR Rd, [Rn, #offset] Read word from memory location Rn + offset
LDRD Rd1,Rd2, [Rn, #offset] Read double word from memory location Rn + offset
(Calculate an address fron a base register value & an immediate offset, loads two words
from memory & writes them to two registers.)
STRB Rd, [Rn, #offset] Store byte to memory location Rn + offset
STRH Rd, [Rn, #offset] Store half word to memory location Rn + offset
STR Rd, [Rn, #offset] Store word to memory location Rn + offset
STRD Rd1,Rd2, [Rn, #offset] Store double word to memory location Rn + offset

10. The exclamation mark (!) in the instruction specifies whether the register Rd should be updated
after the instruction is completed.
“!” indicates the update of base register R1
STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store; (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store.
(Store multiple,Increment after):-Stores multiple registers to consecutive memory locations
using an address from a base register)
ARM processors also support memory accesses with preindexing and postindexing.
(a) Pre-Indexing
• Pre-indexing load instructions for various sizes (word, byte, half word, and double word)
LDR.W Rd, [Rn, #offset]!
LDRB.W Rd, [Rn, #offset]!
LDRH.W Rd, [Rn, #offset]!
LDRD.W Rd1, Rd2,[Rn, #offset]!
• Pre-indexing load instructions for various sizes with sign extend (byte, half word)
LDRSB.W Rd, [Rn, #offset]!
LDRSH.W Rd, [Rn, #offset]!

11. Pre-indexing store instructions for various sizes (word, byte, half word, and double word)
STR.W Rd, [Rn, #offset]!
STRB.W Rd, [Rn, #offset]!
STRH.W Rd, [Rn, #offset]!
STRD.W Rd1, Rd2,[Rn, #offset]!
ARM Cortex-3 also supports multiple memory load and store operation with Increment after
and decrement before facility. This is illustrated below.

12. b) Post indexing
Postindexing memory access instructions carry out the memory transfer using the base address
specified by the register and then update the address register afterward.
For example,
LDR.W R0,[R1], #offset ; Read memory[R1], with R1 is updated to R1+offset
• Postindexing load instructions for various sizes (word, byte, half word, and double word)
LDR.W Rd, [Rn], #offset
LDRB.W Rd, [Rn], #offset
LDRH.W Rd, [Rn], #offset
LDRD.W Rd1, Rd2,[Rn], #offset
• Postindexing load instructions for various sizes with sign extend (byte, half word)
LDRSB.W Rd, [Rn], #offset
LDRSH.W Rd, [Rn], #offset
• Postindexing store instructions for various sizes (word, byte,half word, and double word)
STR.W Rd, [Rn], #offset
STRB.W Rd, [Rn], #offset
STRH.W Rd, [Rn], #offset
STRD.W Rd1, Rd2,[Rn], #offset

13. Two other types of memory operation are Stack PUSH and Stack POP.
Accessing Stack memory Locations through PUSH & POP
PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into stack memory
POP {R2,R3} ; Pop R2 and R3 from stack
Usually, a PUSH instruction will have a corresponding POP with the same register list, but this is
not always necessary.
• For example, a common exception is when POP is used as a function return:
PUSH {R0-R3, LR} ; Save register contents at beginning of subroutine
.... ..........................; Processing
.......
........
POP {R0-R3, PC} ; restore registers and return

14. (d)Moving data between special Registers to another Register
To access APSR registers, one can use the instructions MRS and MSR. For example,
MRS R0, PSR ; Read Processor status word into R0
MSR CONTROL, R1 ; Write value of R1 into control register
• APSR can be written only in privileged mode.

15. Pseudo-Instructions
• Both LDR and ADR pseudo-instructions can be used to set registers to a program address
value. They have different syntaxes and behaviors.
• For LDR, if the address is a program address value, the assembler will automatically set
the LSB to 1.
LDR R0, = address1 ; R0 set to 0x4001
.............................
address1 ; address here is 0x4000
Mov R0, R1 ; address1 contains program code
• If address1 is a data address, LSB will not be changed.
LDR R0, =address1 ; R0 set to 0x4000
...
address1 ; address here is 0x4000
DCD 0x0 ; address1 contains data
• For ADR, one can load the address value of a program code into a register without setting
the LSB automatically and no equal sign (=) in the ADR statement is required.
ADR R0, address1
...
address1 ; (address here is 0x4000)
MOV R0, R1 ; address1 contains program code.

16. Data Processing Instructions
The Cortex-M3 provides many different instructions for data processing
(a) Arithmetic operation instructions include ADD, SUB, MUL, DIV, unsigned and signed
divide (UDIV/SDIV).
(b) Logical instructions include AND, OR, NOT, Exor, Shift & Rotate.
• ADD instruction can operate between two registers or between one register and an
immediate data value:
ADD R0, R0, R1 ; R0 = R0 + R1
ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
ADD.W R0, R1, R2 ; R0 = R1 + R2
ADD.W R0, R1, R2 ; Flag unchanged. ADDS.W R0, R1, R2 ; Flag change.
All the Cortex-M3 Arithmetic Instructions are listed below: