The document discusses the MIPI System Power Management Interface (SPMI) version 1.0, which is a two-wire serial interface enabling connections between multiple masters and slaves in power management systems. It outlines the multi-master verification architecture, verification challenges including bus arbitration and noise issues, and presents solutions for them. The conclusion highlights the protocol's importance in reducing chipset connections, notes areas for improvement, and references the MIPI specification for further details.

1. Sanjeev Kumar, Lead Engineer, Sr
Qualcomm India Private Limited
Purva Joshi, Engineer
Qualcomm India Private Limited
Ritesh Jain, Engineer, Sr Staff/Manager
Qualcomm India Private Limited
MIPI-SPMISM 1.0 Multi-master Verification

2. © 2017 MIPI Alliance, Inc.
Agenda
• MIPI-SPMI – An Introduction
• MIPI-SPMI Multi-master Verification Architecture
• Verification Challenges and their Solutions
• Conclusions and References
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3. © 2017 MIPI Alliance, Inc.
MIPI-SPMI – An Introduction
• SPMI (System Power Management Interface):
– 2-wire serial interface
– Supports up-to 4 masters and 16 slaves
– Connects the integrated Power Controller (PC) of a System-on-Chip (SoC)
processor system with one or more Power Management Integrated
Circuits (PMIC) voltage regulation systems
• Within PC, SPMI-related functions are referred to as “Master”.
• Within PMIC, SPMI related functions are referred to as “Slave”.
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4. © 2017 MIPI Alliance, Inc.
MIPI-SPMI – An Introduction
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MIPI-SPMI Multi-master Verification Architecture
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Verification Challenges and their Solutions
• Multiple masters waking up at the same time and trying to connect
– No RCS request
– Pending RCS request
• Second master trying to connect when one master is already present
– SSC Detection
– Bus Idle
– Bus Arbitration
• Multiple masters and slaves arbitrating with different priority levels
– A-bit and SR-bit for slaves; priority and secondary MPLs for masters
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7. © 2017 MIPI Alliance, Inc.
Verification Challenges and their Solutions
• BOM (Bus Owner Master) transfer, i.e. SCLK Handover
• Disconnection of a master
– Using TBO command
– During command parity error
• Noise during
– Bus Idle
– Master Arbitration
– Slave Arbitration
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Multiple masters waking up at the same time and
trying to connect
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Second master trying to connect when one master is
already present
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Multiple masters and slaves arbitrating with different
priority levels and BOM (Bus Owner Master) transfer
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Disconnection of a master
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Noise on SDATA bus
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Conclusions and References
• MIPI-SPMI protocol plays a vital role in reducing the number of pin
connections in a chipset as it support multi-master and multi-slave
systems and various types of data path commands.
• There are certain areas which needs some improvement. Some of
them has been addressed in MIPI-SPMI spec ver. 2.0. Some more
are yet to be taken care as suggested by us in this presentation.
• Reference: MIPI® Alliance Specification for System Power
Management Interface (SPMI) - Version 1.0 – 27 October 2008
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