High End RTP Production System For 200 mm / 300 mm wafer size For 180 nm, 130 nm, and 100 nm technology Processes Implant activation S/D Ultra Shallow Junction Formation TiSi 2 , CoSi 2 processes Dry oxides, oxynitrides Steam applications STI liner oxides Sidewall oxides Thin gate oxides PSG and BPSG reflow processes Others

1. 3000 RTP System
by Cubit Pte Ltd
soroskim@cubit.com.sg

2. Applications
High-End RTP Production System
For 200 mm / 300 mm wafer size
For 180 nm, 130 nm, and 100 nm technology
Processes :
Implant activation
S/D
Ultra-Shallow Junction Formation
TiSi2, CoSi2 processes
Dry oxides, oxynitrides
Steam applications
STI liner oxides
Sidewall oxides
Thin gate oxides
PSG and BPSG reflow processes
Others

3. 3000 Footprint
Process & Fac. Module
Handling Module
(dep. on config.)
Power &
Control
Rack
up to 15 m
Blower
Small Footprint: 3.2-3.6 m2
200 / 300 mm Capability

4. 3000 Footprint With Steam Option
Steam
Module
Power &
Control
Rack
Process & Fac. Module
Handling Module
(dep. on config.)
up to 15 m
Blower
Small Footprint: 3.6-4.1 m2
200 / 300 mm Capability

5. 3000 with Steam Option
Additional Steam Features
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6. 200mm & 300mm Production Configuration
2 x 300 mm FOUP 200 mm Open Cassettes

7. 3000 Customer List
NEC 1
Varian 2
White Oak 4
Infineon 3
UMC ~20
TSMC 2
Macronix 2
Chartered 7
Hynix 1
Lucent 1
Hitachi 1
200mm
Infineon 6
UMC 3
TSMC 1
Trecenti 7
TI 1
300mm
Wacker 2
Mitsubishi 1
MEMC 3
LG Siltron 1
Taisil 1
Wafer Mfg.
> 70 Tools

8. Facts
3000 in 256 M DRAM high volume mass production for
200 mm wafers and in-pilot production on 300 mm wafers
300 mm chip production field experience since 04/98
(SC300 / Dresden, SAMSUNG / Korea)
I300I 300 mm benchmark evaluation successfully completed in
Feb. 1998, SELETE 300 mm benchmark evaluation successfully
completed in March 2000
SEMATECH benchmark evaluation on 200 mm wafers (S/D anneal),
thin oxides, and Spike Annealing in Dec. 1999
Large market penetration of 3000 worldwide
(Taiwan, USA, Europe, Singapore, Japan, Korea)
First 3000 system with Wet Oxidation option shipped by 07/00.
Backside-independent Ripple temperature measurement
down to 450 °C.
Ripple measurement proven in high volume production

9. Reactor Concept
Front
Back
Bottom lamps
Top lamps
Top view with 200 mm wafer
and 300 mm wafer + edge guard ring

10. Reactor Concept
Aluminum chamber sealed with top &
bottom quartz windows
Top side heating by 26 linear lamps
Back side heating by 26 linear lamps
Side heating by 2 x 2 linear lamps

11. Reactor Cross-Section
Bottom quartz plate
Gas inlet
Door slot
Bottom
lamps
Side lamps
Ring & liner tray
200 mm wafer
Quartz pads
Top quartz plate
Rotor with
wafer support
Top lamps

12. Wafer Rotation
Rotor
Quartz pads
(for air cushion)
Gas supply 2
(for air cushion)
300 mm wafer
Quartz plate
Gas supply 1 (for acc. /
dec.)

13. 0 10 20 30 40 50 60 70 80 90
0
20
40
60
80
100
120
N
2
O
2
Pyro
Set
O
2
-Concentration
(ppm)
/
N
2
-Gas
Flow
(slm)
Recipe Time (s)
0
100
200
300
400
500
600
700
800
Set
/
Pyro
Temperature
(°C)
Ambient Control Using O2 Sensor
O2-sensor inlet about 1 cm from door O2-concentration < 10 ppm within less
200 mm titanium coated silicon wafer than 9 s measured by oxygen sensor

14. Ripple Temperature Measurement
Measurement Principle

Wafer 

Incident lamp light
 : Transmissivity
  Reflectivity
 : Absorptivity
Measurement Principle:
Separation of reflected lamp light and radiation emitted from the wafer
Emissivity calculation:  =  −  −  ( =  for T > 600 °C)
Rescaling of measured emissivity to black body intensity
Calculation of actual wafer temperature
Energy Balance:  +  +  = 1
Kirchhoff Law:  = 

15. Reflectivity
Transmissivity
Emissivity
Ripple Temperature Measurement
Measurement Principle
DC lamp signal with AC modulation
and phase shift
DC lamp signal with AC modulation
Reflected DC lamp signal with AC modulation
Transmitted DC lamp signal with
AC modulation and phase shift
Temperature radiation from wafer
Absolute
Temperature
I
t
I
t
I
t
I
t
t
Lamp
Pyro
Wafer
Optical System Optical System
Wafer
Pyro

16. Ripple Temperature Measurement
Backside Independence in Production
Backside Coated
Bare Silicon
Wafers
RTO Process:
1080 °C, 95 s, O2
From: „Evaluation of an AST 3000 RTP-Tool for Production“
Regina Hayn et al, Infineon Technologies, RTP Conference 1999, Colorado Springs, USA
Mean Oxide Thickness within +/- 3.1 Å
(including influence of backside preparation
on wafer frontside)
110,0
115,0
120,0
125,0
130,0
135,0
140,0
145,0
150,0
bare
Si
90
nm
Poly
90
nm
Poly
170
nm
WSi
170
nm
WSi
22.5
nm
Oxide
22.5
nm
Oxide
40
nm
Oxide
40
nm
Oxide
55
nm
Oxide
55
nm
Oxide
26.5
nm
Nitride
26.5
nm
Nitride
175
nm
Nitride
175
nm
Nitride
200
nm
Nitride
200
nm
Nitride
bare
Si
Wafer Backside Coating
Oxide
Thickness
(Å)

17. Impact of Quartz Ware Contamination
on Temperature Measurement
General
Processes like BPSG reflow or RTA of B+ or BF2
+ tend to contaminate
the quartz ware, temperature measurement devices and the process chamber.
Contamination might have a strong effect on temperature measurement.
Especially temperature measurement techniques making use of passive emissivity
compensation, rely on clean surfaces to function properly because they cannot
compensate contamination.
Therefore, the temperature measurement devices have to be changed or
cleaned frequently.
This results in high costs for quartz ware and reduced uptime.
Ripple Pyrometry
The Ripple pyrometer optic is to a large extent not affected by contamination,
because it is separated from the process environment by the quartz ware and it
actively measures optical properties of the wafer incl. optical paths between wafer
and pyrometer.
After heavy contamination, quartz ware can easily be cleaned and /or changed.
Higher uptime
Lower CoO
Better process stability

18. Impact of Quartz Ware Contamination
on Temperature Measurement (continued)
Coated quartz wafer, placed 3 mm above the rotor
(simulation of quartz contamination)
Wafer
Experimental Set-Up

19. Temperature stability within +/- 1°C
Insensitivity of Ripple Temperature Measurement
against heavy quartz contamination
-2,0
-1,0
0,0
1,0
2,0
Bare 3.3 nm
Si3N4
7.7 nm
Si3N4
56.3 nm
Si3N4
2 nm
PolySi
12.7 nm
PolySi
Coating of Quartz Wafer
Temperature
Variation
(°C)
700 °C ( Wafer HR)
1000 °C ( Wafer LR)
Impact of Quartz Ware Contamination
on Temperature Measurement (continued)

20. Implant conditions : As, 20 keV, 1.0·1016 cm-2
RTP process : 1000 °C, 30 s
Measurement on 4-Point-Probe : 121 sites, 3 mm edge exclusion
Uniform Lamp Correction Table Uniform LCT Optimized LCT
No rotation Rotation Rotation
Std. Dev. (1 ) = 1.1 % = 1.1 % = 0.8 %
Temp. Range = ± 2.4 °C = ± 1.8 °C = ± 1.2 °C
Inherent Uniformity (200 mm)

21. Process Performance (200 mm)
1050 °C, 15 s, O2
Thin Gate Oxide
Mean Thickness: 40 Å
Uniformity (1 ): 0.5 %
Repeatability (1 ): 0.4 %
Sensitivity: 0.2 Å/°C
S/D Anneal
(As, 1.0·1016 cm-2, 25 keV)
Mean RS: 110 W/Sq.
Uniformity (1 ): 0.5 %
Repeatability (1 ): 0.3 %
Sensitivity: 1.1 W/Sq.*°C
Slot 1
Slot 12
Slot 25
1000 °C, 10 s, N2+O2

22. Process Performance (200 mm)
Results from
2 month monitoring
RTO Process:
1080 °C, 95 s, O2
+/- 2.65 Å
all points all wafers
From: „Evaluation of an AST 3000 RTP-Tool for Production“
Regina Hayn et al, Infineon Technologies, RTP Conference 1999, Colorado Springs, USA

23. 0
10
20
30
40
50
60
0 25 50 75 100 125
Wafer Number
Mean
R
S
(
W
/Sq.)
0,0
0,5
1,0
1,5
2,0
2,5
3,0
Post Mean
Stand.
Dev.
(1

)
(%)
Pre Stand. Dev.
Post Stand. Dev.
Pre Mean
Batch 1 Batch 2 Batch 3 Batch 4 Batch 5
Process Performance (200 mm)
Low Temp. CoSi2 Formation
RTP Process: 490 °C, 30 sec, pure N2 ambient
Wafers: 15 nm Co + 8 nm Ti on bare 200 mm Si wafer
Repeatability: 1.1 %, Av. Uniformity 1.8 %
Result: Repeatability: 0.6 % (- 0.5 % added)
Av. Uniformity: 1.2 % (- 0.6 % added)

24. Process Performance (300 mm)
Results From a 5-Day Marathon
122
123
124
125
126
127
128
129
130
131
132
0 5 10 15 20 25
Wafer Number
Mean
Oxide
Thickness
(Å)
0,20
0,40
0,60
0,80
1,00
1,20
Std.
Dev.
1

(%)
196
198
200
202
204
206
0 5 10 15 20 25
Wafer Number
Mean
Sheet
Resistance
(
W
/Sq.)
0,2
0,6
1,0
1,4
1,8
2,2
Std.
Dev.
1

(%)
RTO: 1080 °C, 120 s
Mean Thickness: 130 Å
Uniformity (1 ): 0.3 ... 0.6 %
Repeatability (1 ): 0.3 %
TCV: 1.8 °C
Sensitivity: 1.1 Å/°C
121 Sites / 3 mm Edge Exclusion
S/D Anneal: 1060 °C, 10 s
Mean RS: 203 W/Sq.
Uniformity (1 ): 0.5 ... 0.9 %
Repeatability (1 ): 0.2 %
Sensitivity: 1.1 W/Sq.·°C
121 Sites / 3 mm Edge Exclusion

25. 300 mm Benchmark Results
25
26
27
28
29
30
31
0 10 20 30 40 50 60 70 80 90 100 110
Wafer Number
Mean
Oxide
Thickness
(Å)
0,30
0,40
0,50
0,60
0,70
0,80
0,90
Std.
Dev.
1

(%)
47
48
49
50
51
52
0 10 20 30 40 50 60 70 80 90 100
Wafer Number
Mean
Oxide
Thickness
(Å)
0,40
0,50
0,60
0,70
0,80
0,90
Std.
Dev.
1

(%)
RTO: 1040 °C, 6 s, pure O2
Mean Thickness: 30 Å
Uniformity (1 ): 0.4 ... 0.5 %
Repeatability (1 ): 0.22 %
Thickness Range APAW: 0.85 Å
121 Sites / 3 mm Edge Exclusion
RTO: 1100 °C, 12 s, pure O2
Mean Thickness: 51 Å
Uniformity (1 ): 0.45 ... 0.55 %
Repeatability (1 ): 0.24 %
Thickness Range APAW: 1.54 Å
121 Sites / 3 mm Edge Exclusion

26. Process Performance (300 mm)
Bare Silicon Wafer With 500 Å Ti / RTP Process : 770 °C, 20 s
Measurement on 4-Point-Probe :121 sites, 5 mm edge exclusion
Post-map: RS mean = 2.19 W/Sq.
Std. dev = 1.40%
RS mean = 0.11 W/Sq.
Pre-map: RS mean = 19.7 W/Sq.
Std. dev = 1.95%
RS mean = 19.7 W/Sq.
Pre-map: RS mean = 19.6 W/Sq.
Std. dev = 1.95%
RS mean = 1.37 W/Sq.
Post-map: RS mean = 2.19 W/Sq.
Std. dev = 1.46%
RS mean = 0.12 W/Sq.

27. 0 100 200 300 400 500 600 700 800 900 1000
1E17
1E18
1E19
1E20
1E21
1E22
C
B
A
Boron
concentration
(cm
-3
)
Depth (Å)
XJ
@ 5E17 cm
-3
Standard Process: 10 s soak time, 40 °C/s ramp-up rate
A: 1050°C, RD: 27 °C/s, XJ
=830 Å, Rs
=327.6 W/Sq
Spike Anneal: 0 s soak time, 240 °C/s ramp-up rate
B: 1050°C, RD: 27 °C/s, XJ
=680 Å, Rs
=345.5 W/Sq
C: 1050°C, RD: 86 °C/s, XJ
=580 Å, Rs
=357.8 W/Sq
Fast-Ramp Spike-Annealing (200 mm)
RTA Spike Anneal versus Standard RTA Process
240 °C/s ramp-up, 0 s soak time 40 °C/s ramp-up, 10 s soak time
Junction depth: 595 Å Junction depth: 830 Å
Reduction of junction depth by 235 Å
B+, 1.0·1015 cm-2, 1.0 keV
1050 °C, 60-65 ppm O2

28. Fast-Ramp Spike-Annealing (200 mm)
20 22 24 26 28 30 32 34 36 38 40 42 44
650
700
750
800
850
900
950
1000
1050
1100
160 °C/s
240 °C/s
Ramp-Up: 350 °C/s
Temperature
(°C)
Time (s)
Controlled ramp-up rates up to 350 °C/s

29. 0 10 20 30 40 50 60 70 80 90 100
400
500
600
700
800
900
1000
1100
1100 °C / 60 s / lightly doped wafer
1100 °C / 10 s / heavily doped wafer
Temperature
(°C)
Time (s)
Fast Cooling-Down (200 mm)
Cooling-down rates up to 90 °C/s

30. Process Performance (300 mm)
Fast-Ramp Spike-Annealing for USJF
1100 °C, Spike
200 °C/sec and 300 °C/sec
Ambient 100 ppm O2 in N2
Implant: BF2
+
, 20 keV, 1.0·E15 cm-2
Spike Time : at 200 °C/sec: 1.80 sec
(1050-1100-1050 °C) at 300 °C/sec: 1.58 sec
1050 °C, Spike,
250 °C/sec
Ambient 1000 ppm O2 in N2
Implant: As
+
, 25 keV, 1.0·E16 cm-2
Uniformity (1  Std. Dev.): 0.45 %
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
0 10 20 30 40 50 60 70 80
Time (s)
Temperature
(°C)

31. Process Performance (200 mm)
Fast-Ramp Spike-Annealing for USJF (continued)
1050 °C, Spike, 100 ppm O2 in N2
Ramp-Up Rate: 300 °C/sec
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
0 10 20 30 40 50 60 70 80
Time (s)
Temperature
(°C)
Repeatability at 1040 °C
(1  Std. Dev):
at 300 °C/sec: 0.80 °C
Spike Time (1000-1050-1000 °C):
at 300 °C/sec: 1.42 sec
1030
1035
1040
1045
1050
1 3 5 7 9 11 13 15 17 19 21 23 25
Wafer No.
Soak
Temperature
(°C)

32. Process Performance (200 mm)
Fast-Ramp Spike-Annealing for USJF (continued)
Temperature Profiles
Process:
1050 °C / Spike
100 ppm O2 in N2
300 °C/s Ramp-Up / 90 °C/s Ramp-Down
40 45 50 55 60 65 70 75 80
300
400
500
600
700
800
900
1000
1100
Slot # 55
Slot # 51
Slot # 50
Slot # 41
Slot # 34
Slot # 10
Slot # 8
Temperature
(°C)
Process time (s)

33. Process Performance (200 mm)
Fast-Ramp Spike-Annealing for USJF (continued)
56 57 58 59 60
900
920
940
960
980
1000
1020
1040
1060
1080
1100
Slot # 55
Slot # 51
Slot # 50
Slot # 41
Slot # 34
Slot # 10
Slot # 8
Temperature
(°C)
Process time (s)
Temperature Profiles
Process:
1050 °C / Spike
100 ppm O2 in N2
300 °C/s Ramp-Up / 90 °C/s
Ramp-Down

34. Process Performance (200 mm)
Fast-Ramp Spike-Annealing for USJF (continued)
SIMS Profiles
Implant condition: 11B+, 1 keV, 1E15 cm-2,Tilt/Twist: 7°/35°
0 100 200 300 400 500 600 700
1E17
1E18
1E19
1E20
1E21
1E22
Slot # 53
Slot # 51
Slot # 50
Slot # 41
Slot # 34
Slot # 10
Boron
concentration
(cm
-3
)
Depth (Å)
XJ
@ 3E18 cm
-3
XJ
@ 7E17 cm
-3

35. Uptime Data
3000 Uptime Data from 200 mm DRAM Mass Production
June 99
July 99
Aug. 99
Sep. 99
Oct. 99
Nov. 99
Tool 1
Tool 2
90
91
92
93
94
95
96
97
98
99
100
Uptime
(%)
Average: 98.0 %

36. Competitive Advantage
Capability for Ultra-Shallow Junction Formation
Ramp rates > 250 °C/s without slow down before set point
True spike anneal profile
Fast cool down up to 90 °C/s, without expensive cooling gas solution
Tight ambient control (0 - 500 ppm O2 in N2)
Potential for ramp rates > 350 °C/s (400 °C/s demonstrated in App Lab)
Steam Capability
Longest steam experience from Steampulse and 2800 Pyrogenic
Steam concentrations 2-80 % - both ultra-thin and thick oxides possible
Reduced thermal budget due to high steam concentrations
Superior WiW uniformity due to ex-situ steam generation
H2-rich and O2-rich steam capability in the same chamber

37. Competitive Advantage (continued)
Excellent CoO: High Throughput - Small Footprint
Due to dual-arm robot, tight ambient control and fast cool-down:
TiSi2 formation (750 °C / 15 s) Throughput > 50 W/h
Implant Annealing (1050 °C / 10 s) Throughput > 50 W/h
Footprint: 3.2 - 3.6 m2 incl. maintenance space
The 3000 tools can be placed next to each other without additional
spacing for service access  more throughput per floorspace
Stand-Alone System
Cost effective separation of individual systems by process type
(no cross contamination)
Flexible capacity planning, minimizing CoO as capacity is added
Lowest cost method of having back up tool availability
Better reliability than multi-chamber cluster tool
Uptime > 95 %
Bridge Tool
Same process chamber both for 200 mm and 300 mm processing
Easy transition from 200 mm process technology into 300 mm
production

38. Competitive Advantage (continued)
Dual Side Heating with Linear Lamps
Reduced pattern effect and “continental drift” for smaller geometries
especially for faster ramps when compared to only top-side heating systems
Superior slip performance at higher temperatures
Ultra-high ramp-up rates of > 250 °C/s and more
Long lamp lifetime and easy & fast maintainability compared
to bulb lamp configurations
Superior inherent and dynamic uniformity due to lamp configuration and
chamber design especially for fast-ramp spike-anneals
(no need for Multi-Point Control down to 100 nm technology).
Ripple Temperature Measurement
Ripple is an absolute, active and direct temperature measurement system,
independent of wafer backside layers, bulk material, backside finishment,
backside non-uniformities. Other RTP systems are using passive
emissivity compensation
Ripple is insensitive to chamber contamination (ie. BPSG), which strongly
influences systems with only passive emissivity compensation.
Ripple allows to control spike-anneals with ramp-up rates > 250 °C/s