The document discusses placement algorithms used in circuit design. It describes the min-cut placement algorithm which partitions the layout surface and circuit into halves recursively to minimize wirelength. Terminal propagation is discussed to address limitations of min-cut by considering terminal pin positions. Placement by simulated annealing is also summarized, using neighborhood structures and cost functions to iteratively improve placement quality as temperature decreases.

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Placement
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• The process of arranging the circuit components on a layout surface.
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• Inputs: A set of fixed modules, a netlist.
o m
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. c
• Goal: Find the best position for each module on the chip according to
ld
O
appropriate cost functions.
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– Considerations: routability/channel density, wirelength, cut size,
W
w
performance, thermal issues, I/O pads.
tu D B C A
U
jn
1 2 1 3
.
T
1
w
E F G H
5 5 6
3 5
w
2
N
Density = 2 (2 tracks required)
7 8
3
w 4 6 8 4
J
6 A B C D
4
8 7 2 7
E F G H
wirelength = 10 wirelength = 12
Shorter wirelength, 3 tracks required.
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Estimation of Wirelength
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• Semi-perimeter method: Half the perimeter of the bounding rectangle
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approximation!
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that encloses all the pins of the net to be connected. Most widely used
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.c
• Complete graph: Since #edges in a complete graph ( n(n−1) ) is n
ld
× #
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2 2
or
2
of tree edges (n − 1), wirelength ≈ n (i,j)∈net dist(i, j).
W
tu
and then to the next closest, etc. w
• Minimum chain: Start from one vertex and connect to the closest one,
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. jn
• Source-to-sink connection: Connect one pin to all other pins of the
T
net. Not accurate for uncongested chips.
w w
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• Steiner-tree approximation: Computationally expensive.
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• Minimum spanning tree
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4
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10 7
7 8 8
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3 3
3
o m
R
. c 3
ld
4
O
or
semi−perimeter len = 11 complete graph len * 2/n = 17.5 chain len = 14
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tu w
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. jn
T
8
w
10
w 7
N
3 4 3
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3
4
source−to−sink len = 17 Steiner tree len = 12 Spanning tree len = 13
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Min-Cut Placement
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• Breuer, “A class of min-cut placement algorithms,” DAC-77.
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• Quadrature: suitable for circuits with high density in the center.
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• Bisection: good for standard-cell placement.
. c
ld
O
• Slice/Bisection: good for cells with high interconnection on the periphery.
or 3a 1
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3a 2a 2
1
tu w 3b
1
3c
3
4
5
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jn
3b 2b 6
.
3d 7
T
w
4a 2 4b 6a 5a 6b 4 6c 5b 6d 10a 9a10b8 10c 9b 10d
w
N
n/2 C2
n/2 n/4 n/k n/k
w n/4 C2
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C1
C1 C1 n/4 n/k
n/4 C2
n/2 n/2 n/2
(k−1)n/k (k−2)n/k
quadrature bisection slice/bisection
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Algorithm for Min-Cut Placement
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Algorithm: Min Cut Placement(N, n, C)
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/* N : the layout surface */
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/* n: # of cells to be placed */
/* n0 : # of cells in a slot */
. c
ld
O
/* C: the connectivity matrix */
or
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1
2
begin
tu w
if (n ≤ n0 ) then PlaceCells(N, n, C);
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jn
3 else
4
.
(N1 , N2 ) ← CutSurface(N );
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5
w
6
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(n1 , C1 ), (n2 , C2 ) ← Partition(n, C);
Call Min Cut Placement(N1 , n1 , C1 );
N
7 Call Min Cut Placement(N2 , n2 , C2 );
w end
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8
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Quadrature Placement Example
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• Apply K-L heuristic to partition + Quadrature Placement: Cost C1 = 4, C2L = C2R = 2,
etc.
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P
Q
2 4
7
8
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R
c
1 14 Q1
5 12
ld .
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R
or
3
9 13
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6
w
16 Q2
tu
11
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n 10 15 Q3
.j
T
w w P 2 4 8 14 O1
N
C4a C4a
w 2,4,5,7 8,12,13,14 5 7 12 13
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C2 C2 C2
1,3,6,9 10,11,15,16 Q 1 9 11 16 O2
C4b C4b
3 6 10 15 O3
C1 R
C3a C1 C3b
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Min-Cut Placement with Terminal Propagation
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• Dunlop & Kernighan, “A procedure for placement of standard-cell VLSI
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circuits,” IEEE TCAD, Jan. 1985.
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R
. c
• Drawback of the original min-cut placement: Does not consider the
ld
O
positions of terminal pins that enter a region.
or
– What happens if we swap {1, 3, 6, 9} and {2, 4, 5, 7} in the previous
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example?
tu w prefer to have them in R1
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S
. jn S
T
L1
w w L1 R1
N
w R
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L2 L2 R2
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Terminal Propagation
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• We should use the fact that s is in L1 !
center dummy cell
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s s p
o m
R
L1
p R1 L1
. c R1
ld
O
or
L2 R2 L2 R2
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Lower cost
tu w higher cost
P will stay in R1 for the rest of partitioning!
U
. jn
• When not to use p to bias partitioning? Net s has cells in many groups?
minimum rectilinear
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w w Steiner tree
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p p2
w
p1
p
J
R
h h/3 h h/3
L
p3
Don’t use p to bias the
solution in either direction! Use p! G
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Terminal Propagation Example
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• Partitioning must be done breadth-first, not depth-first.
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a S
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R
b S
a
. c b
ld
O
c
or
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d
tu w c d
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. jn
T
C1 C1 C1 C1
w w
N
p1 c b
a b a b L1 a
L1 R1
b R1
L
w R L R
J
L2
c d c d L2 c d R2 a d R2
unbiased partition with terminal without terminal
of R propagation propagation
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Placement by Simulated Annealing
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• Sechen and Sangiovanni-Vincentelli, “The TimberWolf placement and
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o m
routing package,” IEEE J. Solid-State Circuits, Feb. 1985; “TimberWolf
3.2: A new standard cell placement and global routing package,” DAC-
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86.
.c
ld
O
or
• TimberWolf: Stage 1
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– Modules are moved between different rows as well as within the same
row.
tu w
U
jn
– Modules overlaps are allowed.
.
– When the temperature is reached below a certain value, stage 2
T
begins.
w w
N
• TimberWolf: Stage 2
w
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– Remove overlaps.
– Annealing process continues, but only interchanges adjacent modules
within the same row.
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Solution Space & Neighborhood Structure
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• Solution Space: All possible arrangements of the modules into rows,
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possibly with overlaps.
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• Neighborhood Structure: 3 types of moves
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ld
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– M1 : Displace a module to a new location.
– M2 : Interchange two modules.
or
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– M3 : Change the orientation of a module.
tu
U
. jn 1 2 2 1
T
w w 3 4
N
4 3
overlap
w
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M1 M2 M3
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Neighborhood Structure
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• TimberWolf first tries to select a move between M1 and M2 : P rob(M1 ) = 0.8, P rob(M2 ) =
0.2.
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module will be chosen with probability 0.1.
o m
• If a move of type M1 is chosen and it is rejected, then a move of type M3 for the same
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.c
• Restrictions: (1) what row for a module can be displaced? (2) what pairs of modules
ld
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can be interchanged?
• Key: Range Limiter
or
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tu w
– At the beginning, (WT , HT ) is very large, big enough to contain the whole chip.
– Window size shrinks slowly as the temperature decreases. Height and width ∝
U
jn
log(T ).
.
– Stage 2 begins when window size is so small that no inter-row module interchanges
T
are possible.
w w
N
w W
J
T
H
T
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Cost Function
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• Cost function: C = C1 + C2 + C3.
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• C1 : total estimated wirelength.
o m
R
c
– C1 = (αi wi + βi hi )
.
i∈N ets
ld
– αi , βi are horizontal and vertical weights, respectively. (αi = 1, βi = 1 ⇒ 1 × perime-
O
2
or
ter of the bounding box of Net i.)
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– Critical nets: Increase both αi and βi .
βi < αi .
tu w
– If vertical wirings are “cheaper” than horizontal wirings, use smaller vertical weights:
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. jn
• C2 : penalty function for module overlaps.
T
w
– C2 = γ 2
Oij , γ: penalty weight.
i=j
w
N
– Oij : amount of overlaps in the x-dimension between modules i and j.
w
• C3 : penalty function that controls the row length.
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– C2 = δ r∈Rows
|Lr − Dr |, δ: penalty weight.
– Dr : desired row length.
– Lr : sum of the widths of the modules in row r.
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Annealing Schedule
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• Tk = rk Tk−1 , k = 1, 2, 3, . . .
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m
• rk increases from 0.8 to max value 0.94 and then decreases to 0.8.
o
R
• At each temperature, a total # of nP attempts is made.
.c n: # of
ld
O
modules; P : user specified constant.
• Termination: T < 0.1.
or
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tu w
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. jn
T
w w
N
w
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