Lab 3 Cover SheetName: Adders and Two’s ComplementDate: Grade ItemGrade Attached block diagrams/schematics of (T1) Ripple-Carry Adder, (T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder using Two’s Complement: /9 VHDL Code showing the design of your (T1) Full Adder and Ripple-Carry Adder, (T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder using Two’s Complement: /9 Simulation screenshots showing correct operation of your (T1) Ripple-Carry Adder and (T2) Two’s Complement circuit: /6 Demonstrations of VHDL code, simulation waveforms, and FPGA implementation of (T3) Ripple-Carry Adder using Two’s Complement: /5 Questions on cover sheet: /8 Total Grade: /37 VHDL Code: Copy-paste your VHDL design module code for: 1. Your full adder and ripple-carry adder (task 1): 2. Your two’s complement circuit (task 2): 3. Your ripple-carry adder using two’s complement (task 3): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). 1. Your ripple-carry adder (task 1): 2. Your two’s complement circuit (task 2): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click Tools(Edit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. Explain the design process that you used to create the RCA and Two’s Complement circuits (lab tasks 1 and 2). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL. 2. When adding two 4-bit numbers together, an addition overflow may occur and carry-out will be ‘1’. Why is this a problem if we are adding unsigned numbers? Why may this be beneficial if we are adding signed numbers (using two’s complement)? 3. Explain the design process that you used to create the 4-bit RCA using Two’s Complement (lab task 3). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL. As a follow-up question, do ...

1. Lab 3 Cover SheetName:
Adders and Two’s ComplementDate:
Grade ItemGrade
Attached block diagrams/schematics of (T1) Ripple-Carry
Adder,
(T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder
using Two’s Complement:
/9
VHDL Code showing the design of your (T1) Full Adder and
Ripple-Carry Adder,
(T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder
using Two’s Complement:
/9
Simulation screenshots showing correct operation of your
(T1) Ripple-Carry Adder and (T2) Two’s Complement circuit:
/6
Demonstrations of VHDL code, simulation waveforms, and
FPGA
implementation of (T3) Ripple-Carry Adder using Two’s
Complement:
/5
Questions on cover sheet:
/8

2. Total Grade:
/37
VHDL Code:
Copy-paste your VHDL design module code for:
1. Your full adder and ripple-carry adder (task 1):
2. Your two’s complement circuit (task 2):
3. Your ripple-carry adder using two’s complement (task 3):
Simulation Screenshots:
Use the “Print Screen” button to capture your screenshot (it
should show the entire screen, not just the window of the
program).
1. Your ripple-carry adder (task 1):
2. Your two’s complement circuit (task 2):
Simulation Screenshot Tips: (you can delete this once you
capture your screenshot)
1. Make the “Wave” window large by clicking the “+” button
near the upper-right of the window
2. Click the “Zoom Full” button (looks like a blue/green-filled
magnifying glass) to enlarge your waveforms
3. In order to not print a lot of black, change the color scheme
of the “Wave” window:

3. 3.1. Click Tools(Edit Preferences…
3.2. The “By Window” tab should be selected, then click Wave
Windows in the “Window List” to the left
3.3. Scroll to the bottom of the “Wave Windows Color Scheme”
list and click waveBackground. Then click white in the color
“Palette” at the right of the screen.
3.4. Now color the waveforms and text black:
3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.”
Then click black in the color “Palette” at the right of the screen.
3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if
you have a cursor you want to print)
3.5. Once you have captured your screenshot, you can click the
Reset Defaults button to restore the “Wave” window to its
original color scheme
Questions: (Please use this cover sheet to type and print your
responses)
1. Explain the design process that you used to create the RCA
and Two’s Complement circuits (lab tasks 1 and 2). Be sure to
refer to your schematics/block diagrams and the process to
translate these into VHDL.
2. When adding two 4-bit numbers together, an addition
overflow may occur and carry-out will be ‘1’. Why is this a
problem if we are adding unsigned numbers? Why may this be
beneficial if we are adding signed numbers (using two’s
complement)?
3. Explain the design process that you used to create the 4-bit
RCA using Two’s Complement (lab task 3). Be sure to refer to
your schematics/block diagrams and the process to translate
these into VHDL.
As a follow-up question, do you feel that your design is optimal
(please explain)? Is there any way you could have better
minimized your use of full adders and logic gates (please

4. explain)?
4. Give two reasons why we may not want to create a test bench
to simulate a circuit using all possible input signal
combinations:
1/2
Management Integrity
Background
Your firm has been approached by a company desiring to
change from their current Big-4 CPA firm to a regional firm to
save over $100,000 in annual audit fees. The potential client is
a privately owned producer of private label garments in the
highly competitive sector, which sells primarily to major
retailers such as Wal-Mart, Kmart, Sears and JC Penney. The
company has experienced some financial difficulties in the past
year, which could lead to its major line of credit being pulled if
it does not make a profit.
In performing some preliminary analytical procedures, you
noted some of the following changes in accounts related to
accounts receivable:
Current Year
(000 omitted)
Previous Year
(000 omitted)
Industry
(000 omitted)
Sales
$40,000
$39,000
Accounts Receivable
$8,000
$6,300

5. % of accounts receivable current
72%
65%
No. of days’ sales in accounts receivable
63
41
43
Gross margin
18.70%
15.90%
16.30%
Days’ sales in inventory
72
45
47
Times interest earned
1.40
5.70
6.50
You also noticed the addition of a large account called “other
assets” on the balance sheet.
When you inquire about the balances, the president has
explanations for the changes. The other assets are old
equipment that the company was previously depreciating, but
they purchased new computerized production equipment during
the year. They have not discarded the old equipment yet because
they might use it if demand increases beyond the capacity of
their current equipment. They merely wanted to move the
equipment out of fixed assets for the current period since the
equipment is not being depreciated.
The new computer equipment is also the explanation for the
improved margins. By automating production beyond previous
automation levels, they have been able to reduce labor costs and
increase margins. This increased production capacity has also
allowed them to increase inventory over levels in previous

6. years.
The changes in accounts receivable are also tied to the new
computerized manufacturing equipment. Since they now have
ability to produce more garments more quickly than in the past,
they can offer their customers a wider selection of products.
Some of the customers returned some goods in exchange for the
new products, so they were rebilled for the new deliveries.
Having more time to pay for the goods since they were rebilled
makes it appear that there are more days in accounts receivable.
There are many risks associated with accepting new clients,
especially if the clients could be in financial distress. The
reason behind planning analytical procedures is to identify areas
of heightened risk of misstatement and then plan the audit to
determine whether potential explanations satisfy all the
unexpected changes that are observed in the account balances.
Further, it is important to be skeptical of management-provided
explanations.
Instructions:
· What information would you want to gather regarding the
integrity of management, and what are probable sources of that
information?
· What other critical background information might you want to
get before accepting this client, and what are probable sources
of that information?
· What other factors, if any, might suggest a high degree of risk
in taking on this client?
· Based on the cursory preliminary analytical analysis, what
accounts appear to have a high risk of material misstatement,
and why?
· What effect would the risk analysis have on your planning this
audit if you decide to take the engagement?
Your paper should meet the following requirements:
· 4-5 pages in length
· Formatted according to CSU-Global Guide to Writing and
APA Requirements
Include at least two or three outside sources. The CSU-Global

7. Library is a great place to start.
3/17/17, 1'21 PMEGCP 281 Lab 3
Page 1 of
2http://ecs.fullerton.edu/~mturi/courses/egcp281/labs/lab3-
281.html
Objectives:
Gain more experience with modular circuit design
Gain experience with arithmetic circuits including: Full Adders,
Ripple Carry Adders (RCAs), and
Two's Complement
Lab Description:
You will design a ripple-carry adder (RCA) using full adders as
components. You will then use this RCA to
implement a two's complement conversion circuit and adapt it to
add two numbers with two's complement.
You will again use modular or structural design techniques to
create these larger digital systems.
Lab Tasks:
1. Design a Ripple Carry Adder to add two 4-bit numbers:
a. Create a VHDL design module for a Full Adder; use Boolean
expressions to define this circuit.
Create a VHDL test bench to test the output for all possible
input signal combinations. Simulate

8. your design and verify your output.
b. Create a VHDL design module for this 4-bit Ripple Carry
Adder (RCA):
i. You will have two 4-bit inputs (you can call them A and B),
one 1-bit carry-in input,
one 4-bit sum output, and one 1-bit carry-out output. Use the
Full Adder VHDL
module you just created. Specifically, use a component
declaration and port mapping to
create a modular design that uses your pre-existing work.
ii. How will you design this circuit? How many Full Adders and
other gates will you need
in order to create this 4-bit RCA? Draw a block
diagram/schematic of your design
including any components or logic gates. Label the components
that you do use (e.g. Full
Adders). You will include this block diagram/schematic in your
report.
c. Create a VHDL test bench to test the output for all possible
input signal combinations, wait a
minute, how many input combinations will this be?!? Instead,
simulate your design using five
pairs of input numbers and verify your output. Include the
waveforms in your report.
d. Further test your circuit by implementing this on the FPGA
board. Connect the input busses of A
and B to eight switches, set carry-in to one button, and connect
the output bus and carry-out to
five LEDs.
2. Design a circuit to take the Two's Complement of a 4-bit

9. number:
a. In the same project, create a new VHDL design module and
add the components that you will
need to implement the 4-bit Two's Complement circuit:
i. You will have one 4-bit input and one 4-bit output. You will
again use component
declaration and port mapping to create a modular design.
ii. How will you design this circuit? How many Full Adders and
other gates will you need
3/17/17, 1'21 PMEGCP 281 Lab 3
Page 2 of
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281.html
in order to create this 4-bit Two's Complement circuit? Draw a
block diagram/schematic
of your design including any components or logic gates. Label
the components that you
do use (e.g. RCA, Full Adders, etc.). You will include this
block diagram/schematic in
your report.
b. Create a VHDL test bench to test the output for all possible
input signal combinations. Simulate
your design and verify your output. Include the waveforms in
your report.
3. Lastly, design a circuit to add two 4-bit numbers where one
number can be expressed in Two's
Complement:

10. a. In the same project, create a VHDL design module for a 4-bit
RCA using Two's Complement:
i. This will be a modular design which will use VHDL
component declarations and port
mapping. This time, you will have two 4-bit inputs (you can call
them A and B), one 1-
bit select input, and one 4-bit sum output. If the select bit is 1,
then the Two's
Complement of input number B will be added to A. If the select
bit is 0, then the sum is
just A + B.
ii. How will you design this circuit? There is a more efficient
way than to use your 4-bit
RCA from Lab Task 1 and your Two's Complement circuit from
Lab Task 2. If you are
stumped, think about using every Full Adder input of a RCA,
and think about how you
will now use the select input.
iii. Draw a block diagram/schematic of your design including
any components or logic
gates. Label the components that you do use (e.g. Full Adders,
RCA, Two’s Complement
circuit, etc.) and within each component, show the Full Adders
and logic gates that are
within the component. You will include this block
diagram/schematic in your report.
b. Create a VHDL test bench to test the output for five pairs of
input numbers (and don't forget to
try toggling the select input). Simulate your design and verify
your output.

11. c. Implement this circuit on the FPGA board. Connect the input
busses to eight switches, connect
the select input to a button, and connect the output bus to four
LEDs.
d. Ask the instructor to check your design, simulation
waveforms, and FPGA board implementation
of your circuit
4. Once you have completed the lab tasks, and after you close
this project, remember to copy your project
folder to a flash drive, your Dropbox, your Google Drive, or
your email in order to keep a copy of your
files.
Lab Submission:
Once you verify the correct operation of your circuits, you are
to put your code and screenshots into the
lab3coversheet-281.doc in the designated areas. This will be the
file that you will print and submit by the due
date. For each task, please copy-paste your code into the correct
areas of the cover sheet. You are then to take
screenshots of your simulation waveforms from ModelSim. I
recommend "maximizing" the windows of the
program to make your screenshot more readable. Lastly, please
attach your block diagrams/schematics to
your cover sheet.
http://ecs.fullerton.edu/~mturi/courses/egcp281/labs/lab3covers
heet-281.doc