This document discusses the evolution of processor interconnect technology and techniques for improving efficiency. It notes that as processors run faster, the interconnect network becomes a larger source of power consumption. New materials like copper wiring and switching techniques like wormhole switching were developed to address these issues. The document also examines routing algorithms and ways to reduce wire length and capacitance to lower power dissipation, as interconnects now account for over half the power used in a processor. Developing more efficient interconnect infrastructure could enable cheaper, more powerful mobile devices.

1. Matthew Agostinelli Interconnect Technology 5/2/2014
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Introduction
Computer processors in this world continue to run
faster and more efficient as the technology for them
evolve. There is a common goal for processors to be
able to run a plethora of operations but use less
power. With changing technology, the interconnect
network of a processor becomes more of a problem
as transistor size becomes smaller. The power
dissipation alone with current Interconnect
technology accounts for more than 20 percent of
power used in a processor. In this article there will be
detailed description of the problems that need to be
overcome to make processors more efficient and
powerful. In this article we will explore the different
ways the interconnect network of processors have
evolved over time and the different techniques used
to design the most efficient processors of today. A
general rule of thumb for the total cost of a
supercomputer is that two thirds of the total cost is
due to the processor and memory modules and one
third of the cost is the network itself. [1] So the
development of new technology in processor design
is a huge topic of discussion as companies like
AMD®, and Intel® are in the race to design the
fastest most efficient processor.
Cost of the interconnection network
In today’s world one of the main goals for computer
design is to design a cheaper computer. The most
crucial part of the computer would be the processor.
The processor has a very complex interconnect
network. It is estimated that as much as one third of
the network cost is related to the total number of
wires; this cost includes the expense of driving
messages at very high rates through the wires. [1] So
in turn developing a better interconnect network
make a cheaper processor which would be a huge
step in the right direction.
Materials used
For the longest time aluminum metal was used for the
wiring of a computer processor. It is a lightweight
metal and doesn’t react with the silicon in the wafer
when bonded to it. The problem with the aluminum
wiring is the fact that it was very expensive to use
and hard to design complicated interconnect
infrastructures due to wire diameter. IBM in 1997
introduced a new technology which was thought to
be impossible. They introduced the first copper chip.
Copper wires conduct electricity with about 40
percent less resistance than aluminum wires, which
results in an additional 15 percent burst in
microprocessor speed. Copper wires are also
significantly more durable and 100 times more
reliable over time, and can be shrunk to smaller sizes
than aluminum. [4] Not only was the copper more
efficient, it made it possible to lay more complicated
wire networks which it turn made the processors
more powerful. One drawback to the copper wiring
was how it reacted with the silicon in the wafer. It
alters the electrical properties of the silicon when in
contact with the wafer. A solution to this problem
was to create an insulating layer in between the
silicon and the copper wiring. Over time there are
numerous advancements in this technology as
processors continue to evolve with engineering
standards.
Switching Analogies
Ways to increase processor speeds would be to create
better switching methods between the header node,
memory, and the destination node. We want low
buffering space to be used, and latency of the
message being sent to be as small as possible.
Latency is defined in clock cycles, and is the time
from header injection into the network then finally
into the destination node. Since there are many
messages being sent from different nodes the average
latency must be defined.
𝐿𝑖 = 𝑖𝑛𝑑𝑖𝑣𝑖𝑑𝑢𝑎𝑙 𝐿𝑎𝑡𝑒𝑛𝑐𝑦 𝑜𝑓 𝑎 𝑚𝑒𝑠𝑠𝑎𝑔𝑒
𝑃 = 𝑡𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑚𝑒𝑠𝑠𝑎𝑔𝑒𝑠
𝐿 𝑎𝑣𝑔 =
𝐿𝑖
𝑃
Buffering Space is used for saving or loading
statements that need to be sent.
Circuit Switching
With circuit switching there is a defined path which
is reserved for the transmission of data. This path is
reserved until all data has been transmitted.
Disadvantages to this approach, is that valuable
resources are held up while data is being transferred.
This in turn causes unnecessary delays in the path.
Packet Switching
In this method data is divided into fixed length
blocks, there is no defined path of the packet being
sent. When the source has a packet to be sent is
transmits the data. This form of switching requires a
large buffer requirement which isn’t helpful when
designing a fast processor.

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Wormhole switching
This form of switching is generally used for
interconnect design. For starters the switches can be
small and compact making it easier to design more
complicated networks. The way this technique works
is it sends out a header flit which contains the routing
information. The flit follows this path in a pipeline
fashion. The subsequent flits then follow the path
defined until all data is received. One drawback to
this method would be that messages have to cross
their channel entirely before the channel can be used
for another message. One way to fix this is to make
virtual channels in the input and output ports which
take flits belonging to a particular packet and allow
flits to use the virtual channel buffers. This increases
the utilization of the physical channel. Our goal with
the switching architecture is to have high throughput.
The operation of a switch has three processes. First it
has an input arbitration, then routing is defined, and
finally an output arbitration. As mentioned above to
have high throughput we need to have a virtual
channel switch where each port has multiple parallel
buffers.
Energy dissipation
With a complex interconnect network energy
dissipation becomes a big issue as complexity of the
network increases. The total energy dissipated is a
combination of energy from switches and energy
from the wiring network.
𝐸 𝑝𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟 = Σ𝐴𝐹𝑗 𝑪𝒋 𝑉2
𝑓
𝐸 = 𝐸𝑠𝑤𝑖𝑡𝑐ℎ + 𝐸𝑖𝑛𝑡𝑒𝑟𝑐𝑜𝑛𝑛𝑒𝑐𝑡
The energy from the switches and interconnect
depend on the capacitance from the signal activity
𝐸 = ∝ 𝑠𝑤𝑖𝑡𝑐ℎ∗ 𝑪𝑉2
To reduce the energy dissipated simply just reduce
the wire length of the interconnect infrastructure.
Architectures that possess longer interswitch wires
will generally create more routing challenges [4]. The
less wire used would decrease the energy dissipation.
Switching algorithms could reduce Energy
dissipation and can be referred to with routing
algorithms later in the article. It is said that about
50% percent of the power dissipated in a processor is
due to the interconnect network. Yet only 10% of
interconnect power dissipation is due to the routing
network. The switches at each junction have a
capacitance and as stated above energy dissipation is
directly correlated to the capacitance of the switches
so one way to reduce this energy dissipation is to
develop better routing algorithms which reduce
overall capacitance for the network.
Routing algorithms
One way to make computer processors more efficient
is to develop better routing algorithms to send data.
In a processor most of the power dissipation is due to
the interconnect network. We want to reduce the
power consumption and one way to do that is to
reduce wire capacitance - simple and efficient routing
algorithms, small diameter, high connectivity, and
small degree. Also, one would wish the
interconnection network to be as efficient as possible.
[1]
Reduce Wire Length
One way to reduce wire capacitance would be to
reduce overall length of the wire. Since the energy
dissipated is directly related to capacitance in the
wire making it shorter would reduce power
consumption overall.
Interconnect Spacing
In the majority of processors most networks are
routed at minimal spacing to reduce materials cost.
This isn’t helpful because as wire spacing decreases
the power dissipation and wire capacitance increase.
The graph below shows how spacing and capacitance
are related.
Figure 1: Taken from [7]
Conclusion
In our world today we want to have the most
powerful processors on the market. There is currently

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a huge push to develop software that doesn’t require
so much processing power. This is good because
developing cheaper processors that run simpler
software make overall device prices a lot cheaper.
The goal used to be high bandwidth and high
throughput but with the new software developments
the focus on infrastructure would be less power
consumption. With mobile processors in tablets and
cellphones the main goal would be exactly that.
Energy dissipation is mainly due to the switches in
the interconnect network. Routing algorithms are
being developed to find solutions to this problem.
Reducing wire length and using the right spacing
could dramatically reduce power consumption. The
interconnect infrastructure of a computer processor is
very important and extensively researched. More
development in this field could lead to a better future
in mobile computing.
Bibliography
[1] Schibell, Stephen T., and Richard M. Stafford.
"Processor Interconnection Networks from Cayley
Graphs." Discrete Applied Mathmatics: 35-55. Print.
[2] Pande, P. P., et al. "Performance evaluation and
design trade-offs for network-on-chip interconnect
architectures." IEEE TRANSACTIONS ON
COMPUTERS 54.8 (2005): 1025-40. Print.
[3] Wentzlaff, David, et al. "On-chip Interconnection
Architechture of the Tile Processor." IEEE Computer
Society (2007): n. pag. Berkeley.edu. Web. 1 May
2014. <http://www.cs.berkeley.edu/
~kubitron/cs258/handouts/papers/wentzlaff_tile64_n
oc_ieeemicro2007.pdf>.
[4] Issac, Randy. "Copper Interconnects The
Evolution of Microprocessors." Intel. Intel, n.d. Web.
1 May 2014. <http://www-
03.ibm.com/ibm/history/ibm100/us/en/icons/copperc
hip/>.
[5] "An Introduction to the Intel ® QuickPath
Interconnect." Intel. Intel, Jan. 2009. Web. 1 May
2014. <http://www.intel.com/content/dam/doc/white-
paper/ quick-path-interconnect-introduction-
paper.pdf>.
[6] Palesi, M.; Holsmark, R.; Kumar, S.; Catania, V.
"Application Specific Routing Algorithms for
Networks on Chip", Parallel and Distributed Systems,
IEEE Transactions on, On page(s): 316 - 330
Volume: 20, Issue: 3, March 2009
[7] Mangen, Nir, et al. "Interconnect-Power
Dissipation in a Microprocessor." SLIP (2004): 7-13.
Print.

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