Instruction set reference [by allen bradley]

Allen-Bradley

PLC-5
Programmable
Instruction
Controllers Set Reference

Important User Information 6ROLG VWDWH HTXLSPHQW KDV RSHUDWLRQDO FKDUDFWHULVWLFV GLIIHULQJ IURP
WKRVH RI HOHFWURPHFKDQLFDO HTXLSPHQW ³6DIHW *XLGHOLQHV IRU WKH
$SSOLFDWLRQ ,QVWDOODWLRQ DQG 0DLQWHQDQFH RI 6ROLG 6WDWH RQWUROV´
3XEOLFDWLRQ 6*,

GHVFULEHV VRPH LPSRUWDQW GLIIHUHQFHV EHWZHHQ
VROLG VWDWH HTXLSPHQW DQG KDUGZLUHG HOHFWURPHFKDQLFDO GHYLFHV
%HFDXVH RI WKLV GLIIHUHQFH DQG DOVR EHFDXVH RI WKH ZLGH YDULHW RI
XVHV IRU VROLG VWDWH HTXLSPHQW DOO SHUVRQV UHVSRQVLEOH IRU DSSOLQJ
WKLV HTXLSPHQW PXVW VDWLVI WKHPVHOYHV WKDW HDFK LQWHQGHG DSSOLFDWLRQ
RI WKLV HTXLSPHQW LV DFFHSWDEOH
,Q QR HYHQW ZLOO WKH $OOHQ%UDGOH RPSDQ EH UHVSRQVLEOH RU OLDEOH
IRU LQGLUHFW RU FRQVHTXHQWLDO GDPDJHV UHVXOWLQJ IURP WKH XVH RU
DSSOLFDWLRQ RI WKLV HTXLSPHQW
7KH H[DPSOHV DQG GLDJUDPV LQ WKLV PDQXDO DUH LQFOXGHG VROHO IRU
LOOXVWUDWLYH SXUSRVHV %HFDXVH RI WKH PDQ YDULDEOHV DQG UHTXLUHPHQWV
DVVRFLDWHG ZLWK DQ SDUWLFXODU LQVWDOODWLRQ WKH $OOHQ%UDGOH
RPSDQ FDQQRW DVVXPH UHVSRQVLELOLW RU OLDELOLW IRU DFWXDO XVH
EDVHG RQ WKH H[DPSOHV DQG GLDJUDPV
1R SDWHQW OLDELOLW LV DVVXPHG E $OOHQ%UDGOH RPSDQ ZLWK
UHVSHFW WR XVH RI LQIRUPDWLRQ FLUFXLWV HTXLSPHQW RU VRIWZDUH
GHVFULEHG LQ WKLV PDQXDO
5HSURGXFWLRQ RI WKH FRQWHQWV RI WKLV PDQXDO LQ ZKROH RU LQ SDUW
ZLWKRXW ZULWWHQ SHUPLVVLRQ RI WKH $OOHQ%UDGOH RPSDQ LV
SURKLELWHG
7KURXJKRXW WKLV PDQXDO ZH XVH QRWHV WR PDNH RX DZDUH RI
VDIHW FRQVLGHUDWLRQV

$77(17,21 ,GHQWLILHV LQIRUPDWLRQ DERXW SUDFWLFHV
RU FLUFXPVWDQFHV WKDW FDQ OHDG WR SHUVRQDO LQMXU RU
GHDWK SURSHUW GDPDJH RU HFRQRPLF ORVV

$WWHQWLRQV KHOS RX
‡ LGHQWLI D KD]DUG
‡ DYRLG WKH KD]DUG
‡ UHFRJQL]H WKH FRQVHTXHQFHV
,PSRUWDQW ,GHQWLILHV LQIRUPDWLRQ WKDW LV HVSHFLDOO LPSRUWDQW IRU
VXFFHVVIXO DSSOLFDWLRQ DQG XQGHUVWDQGLQJ RI WKH SURGXFW

@‡ur…r‡Ãv†ÃhÃ…rtv†‡r…rqÃ‡…hqr€h…xÃ‚sÃD‡ryÃ8‚…ƒ‚…h‡v‚ÃYr…‚‘Ã8‚…ƒ‚…h‡v‚ÃhqÃ9 vtv‡hyÃ

@„ˆvƒ€r‡Ã8‚…ƒ‚…h‡v‚

9h‡hÃCvtuh’ÃQyˆ†Ã9CÃQG8ÃQG 8$ÃQG8$ Ã$!Ã$!%Ã$Ã$#Ã$#%Ã$#GÃ$%Ã$%GÃ

$'Ã$'%Ã$!@Ã$#@ÃhqÃ$'@Ãh…rÃ‡…hqr€h…x†Ã‚sÃS‚pxryyÃ6ˆ‡‚€ h‡v‚

6yyr7…hqyr’Ãv†ÃhÃ‡…hqr€h…xÃ‚sÃS‚pxryyÃ6ˆ‡‚€ h‡v‚ÃhÃp‚…rÃiˆ†vr††Ã‚sÃS‚pxryyÃD‡r…h‡v‚hyÃ

8‚…ƒ‚…h‡v‚

PLC-5 Instruction Set Alphabetical Listing

For this For this For this For this
See Page: See Page: See Page: See Page:
Instruction: Instruction: Instruction: Instruction:

ABL 17-51 CMP 3-3 JSR 13-12 RES 2-25

ACB 17-71 COP 9-20 LBL 13-5 RET 13-12

ACI 17-91 COS 4-211 LEQ 3-9 RTO 2-13
1
ACN 17-10 CPT 4-5 LES 3-10 SBR 13-12

ACS 4-131 CTD 2-20 LFL 11-51 SDS 18-2

ADD 4-14 CTU 2-18 LFU 11-51 SFR 13-231

AEX 17-111 DDT 10-2 LIM 3-11 SIN 4-271

AFI 13-19 DEG 6-51 LN 4-231 SQI 12-2

AHL 17-121 DFA 18-3 LOG 4-241 SQL 12-2

AIC 17-141 DIV 4-22 MCR 13-3 SQO 12-2

AND 5-2 DTR 10-8 MEQ 3-13 SQR 4-28
1
ARD 17-15 EOT 13-24 MOV 7-4 SRT 4-291

ARL 17-181 EQU 3-6 MSG 16-2 STD 4-311

ASC 17-211 FAL 9-2 MUL 4-25 SUB 4-34

ASN 4-151 FBC 10-2 MVM 7-5 TAN 4-351

ASR 17-221 FFL 11-5 NEG 4-26 TND 13-19

ATN 4-161 FFU 11-5 NEQ 3-15 TOD 6-3

AVE 4-171 FLL 9-21 NOT 5-4 TOF 2-9

AWA 17-231 FOR 13-8 NXT 13-8 TON 2-5

AWT 17-261 FRD 6-4 ONS 13-20 UID 13-251

BRK 13-8 FSC 9-15 OR 5-6 UIE 13-261

BSL 11-2 GEQ 3-7 OSF 13-221 XIC 1-3

BSR 11-2 GRT 3-8 OSR 13-211 XIO 1-4
2
BTD 7-2 IDI 1-10 OTE 1-5 XOR 5-8

BTR 15-4 IDO 1-112 OTL 1-6 XPY 4-361
1
BTW 15-4 IIN 1-8 OTU 1-7 Enhanced PLC -5 processors
only.
CIO 15-252 IOT 1-9 PID NO TAG 2
6200 programming software
with ControlNet PLC-5
CLR 4-20 JMP 13-5 RAD 6-61 processors only

1785-6.1 November 1998


6HH 7DEOH $ IRU JXLGHOLQHV RQ FKRRVLQJ WKH DSSURSULDWH LQVWUXFWLRQ IRU
WKH RSHUDWLRQ RX ZDQW WR SHUIRUP 7DEOH % OLVWV VRPH H[DPSOHV
Table A
Choosing an Instruction Category

If You Want to Perform Use this Instruction Category:
this Operation:

examine, check or control 2-state device or condition bit level
multiple 2-state devices or conditions multi-bit

move, copy, change, analog values, codes element level
compute, compare multiple sets of values file instructions

convert conversion instructions

time or delay timer

count counter

shift or track bit shift

sequence sequencer

PID PID

message sending/receiving message

transfer data to/from modules block transfer or ControlNet transfer

diagnostics, fault handling diagnostics

control the flow of your program program control

Table B
Example Operations

If Your Application Calls for Operations such as: Use:

detecting when a limit switch closes bit level

changing the temperature preset element level

transfer analog data block transfer

turn on a motor 10 seconds after a pump is activated timing

move 1 of 3 recipes into a work area multi-element

keep track of parts as they move from station to station shifting

keep track of total parts in a bin counting

1785-6.1 November 1998

Summary of Changes

Summary of Changes
New Information Added to 7KH OLVW EHORZ VXPPDUL]HV WKH FKDQJHV WKDW KDYH EHHQ PDGH WR WKLV
this Manual PDQXDO VLQFH WKH ODVW SULQWLQJ

For this Update Information: See Chapter:

Converting non-decimal numbers with the FRD instruction 6

How non-existing, indirect addresses affect the COP and 9
FLL instructions

How the .POS value operates in sequencer instructions 12

Using a RET instruction 13

Using the PID bias term 14

Using the no zero crossing (.NOZC) and no back calculation 14
(.NOBC) features in the PD control block

Clarification to error code 89 for MSG instruction 16

Ethernet PLC-5 processors now support SLC Typed Read and 16
SLC Typed Write MSG instructions

Configuring a multihop MSG instruction over Ethernet or 16
over ControlNet

Monitoring the status of the .EN bit in a continuous 16
MSG instruction

7R KHOS RX ILQG QHZ LQIRUPDWLRQ DQG XSGDWHG LQIRUPDWLRQ LQ WKLV
UHOHDVH RI WKH PDQXDO ZH KDYH LQFOXGHG FKDQJH EDUV DV VKRZQ WR WKH
OHIW RI WKLV SDUDJUDSK

1785-6.1 November 1998

Summary of Changes

1RWHV

1785-6.1 November 1998

Preface

Preface
Conventions 7KLV PDQXDO XVHV WKH IROORZLQJ FRQYHQWLRQV
‡ 8QOHVV RWKHUZLVH VWDWHG

References to: Include these Allen-Bradley Processors:

Classic PLC-5 processors PLC-5/10™, -5/12™, -5/15™, -5/25™, and -5/VME™ processors.

Enhanced PLC-5 processors PLC-5/11™, -5/20™, -5/30™, -5/40™, -5/40L™, -5/60™,
-5/60L™, and -5/80™ processors.
Note: Unless otherwise specified, Enhanced PLC-5 processors include
Ethernet PLC-5, ControlNet PLC-5, Protected PLC-5 and VME PLC-5
processors.

Ethernet PLC-5 processors PLC-5/20E™, -5/40E™, and -5/80E™ processors.

ControlNet PLC-5 processors PLC-5/20C™, -5/40C™, -5/46C™, and -5/80C™ processors.
1
Protected PLC-5 processors PLC-5/26™, -5/46™, and -5/86™ processors.

VME PLC-5 processors PLC-5/V30™, -5/V40™, -5/V40L™, and -5/V80™ processors. See the
PLC-5/VME VMEbus Programmable Controllers User Manual for more
information.
Ã
Q…‚‡rp‡rqÃQG8$Ãƒ…‚pr††‚…†Ãhy‚rÃq‚Ã‚‡Ãr†ˆ…rÃQG8$Ã†’†‡r€Ã†rpˆ…v‡’ÃT’†‡r€Ã†rpˆ…v‡’Ãv†ÃhÃp‚€ivh‡v‚Ã‚sÃ
‡urÃQ…‚‡rp‡rqÃQG8$Ãƒ…‚pr††‚…Ã‡urÃ†‚s‡h…rÃhqÃ’‚ˆ…Ãhƒƒyvph‡v‚Ãr‘ƒr…‡v†rÃ

‡ :RUGV LQ VTXDUH EUDFNHWV UHSUHVHQW DFWXDO NHV WKDW RX SUHVV
)RU H[DPSOH
Enter]; [F1] – Online Programming/Documentation
‡ :RUGV WKDW GHVFULEH LQIRUPDWLRQ WKDW RX KDYH WR SURYLGH DUH
VKRZQ LQ LWDOLFV )RU H[DPSOH LI RX KDYH WR WSH D ILOH QDPH WKLV
LV VKRZQ DV
filename
‡ 0HVVDJHV DQG SURPSWV WKDW WKH WHUPLQDO GLVSODV DUH VKRZQ DV
Press a function key

1785-6.1 November 1998

Preface

1RWHV

1785-6.1 November 1998

Table of Contents

Relay-Type Instructions Chapter 1
XIC, XIO, OTE, OTL, OTU, IIN, IOT, Using Relay-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IDI, IDO I/O Image Files in Data Storage . . . . . . . . . . . . . . . . . . . . . 1-2
Rung Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Examine On (XIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Examine Off (XIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Energize (OTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Latch (OTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Unlatch (OTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Immediate Input (IIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Immediate Output (IOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Immediate Data Input (IDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Immediate Data Output (IDO) . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Using IDI and IDO Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Timer Instructions TON, TOF, Chapter 2
RTO Counter Instructions CTU, Using Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CTD Reset RES Using Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Timer Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Timer On Delay (TON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Timer Off Delay (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Retentive Timer On (RTO) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Count Up (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Count Down (CTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timer and Counter Reset (RES). . . . . . . . . . . . . . . . . . . . . . 2-20

1785-6.1 November 1998

toc–2 Table of Contents

Compare Instructions Chapter 3
CMP, EQU, GEQ, GRT, LEQ, LES, LIM, Using Compare Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
MEQ, NEQ Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Compare (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Entering the CMP Expression. . . . . . . . . . . . . . . . . . . . . . . 3-2
Determining the Length of an Expression. . . . . . . . . . . . . . 3-3
Equal to (EQU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than or Equal to (GEQ). . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than (GRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than or Equal to (LEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than (LES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Limit Test (LIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Mask Compare Equal to (MEQ) . . . . . . . . . . . . . . . . . . . . . . . 3-9
Not Equal to (NEQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Compute Instructions Chapter 4
CPT, ACS, ADD, ASN, ATN, AVE, Using Compute Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CLR, COS, DIV, LN, LOG, MUL, NEG, Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Data Types and the Compute Instruction . . . . . . . . . . . . . . . . 4-3
SIN, SRT, SQR, STD, SUB, TAN, XPY Using Floating Point Data Types . . . . . . . . . . . . . . . . . . . . . . 4-4
Compute (CPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Entering the CPT Expression . . . . . . . . . . . . . . . . . . . . . . . 4-5
Determining the Length of an Expression. . . . . . . . . . . . . . 4-7
Determining the Order of Operation . . . . . . . . . . . . . . . . . . 4-8
Expression Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Entering the Destination . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Using CPT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Arc Cosine (ACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Addition (ADD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Arc Sine (ASN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Arc Tangent (ATN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Average File (AVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Clear (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Cosine (COS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Divide (DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Natural Log (LN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Log to the Base 10 (LOG). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Multiply (MUL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Negate (NEG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Sine (SIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Square Root (SQR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

1785-6.1 November 1998

Table of Contents toc–3

Sort File (SRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Standard Deviation (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Subtract (SUB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Tangent (TAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
X to the Power of Y (XPY). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33

Logical Instructions Chapter 5
AND, NOT, OR, XOR Using Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 5-1
AND Operation (AND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
NOT Operation (NOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
OR Operation (OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Exclusive OR Operation (XOR) . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Conversion Instructions Chapter 6
FRD and TOD, DEG and RAD Using the Conversion Instructions . . . . . . . . . . . . . . . . . . . . . 6-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 6-1
Convert to BCD (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Convert from BCD (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Degree (DEG)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-3
Radian (RAD)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-4

Bit Modify and Move Instructions Chapter 7
BTD, MOV, MVM Using Bit Modify and Move Instructions . . . . . . . . . . . . . . . . . 7-1
Bit Distribute (BTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Move (MOV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Masked Move (MVM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

File Instruction Concepts Chapter 8
Concepts of File Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Using the Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Manipulating File Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Choosing Modes of Block Operation . . . . . . . . . . . . . . . . . . . 8-5
All Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Numerical Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Incremental Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Special Case, Numerical Mode with Words Per Scan = 1. . 8-8

1785-6.1 November 1998


File Instructions Chapter 9
FAL, FSC, COP, FLL Using File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
File Arithmetic and Logic (FAL) . . . . . . . . . . . . . . . . . . . . . . . 9-2
FAL Copy Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
FAL Arithmetic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Upper and Lower Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
FAL Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
FAL Convert Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
File Search and Compare (FSC) . . . . . . . . . . . . . . . . . . . . . . 9-14
FSC Search and Compare Operations . . . . . . . . . . . . . . . . . 9-17
Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Search Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Copy (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
File Fill (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

Diagnostic Instructions Chapter 10
FBC, DDT, DTR Using Diagnostic Instructions . . . . . . . . . . . . . . . . . . . . . . . 10-1
File Bit Comparison (FBC) and Diagnostic Detect (DDT) . . . . 10-2
Selecting the Search Mode . . . . . . . . . . . . . . . . . . . . . . . 10-2
One Mismatch at a Time . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
All Per Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Data Transitional (DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Shift Register Instructions Chapter 11
BSL, BSR, FFL, FFU, LFL, LFU Applying Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Using Bit Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Using FIFO and LIFO Instructions . . . . . . . . . . . . . . . . . . . . . 11-5

Sequencer Instructions Chapter 12
SQO, SQI, SQL Applying Sequencers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Using Sequencer Instructions . . . . . . . . . . . . . . . . . . . . . . . 12-2
Resetting the Position of SQO . . . . . . . . . . . . . . . . . . . . . 12-6
Using SQI Without SQO . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

1785-6.1 November 1998


Program Control Instructions MCR, Chapter 13
JMP, LBL, FOR, NXT, BRK, JSR, Selecting Program Flow Instructions . . . . . . . . . . . . . . . . . . 13-1
SBR, RET, TND, AFI, ONS, OSR, OSF, Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Jump (JMP) and Label (LBL) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
SFR, EOT, UIE, UID Using JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Using LBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
For Next Loop (FOR, NXT), Break (BRK) . . . . . . . . . . . . . . . . 13-5
Using FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Using BRK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Using NXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Jump to Subroutine (JSR), Subroutine (SBR),
and Return (RET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Passing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Using JSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using SBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Temporary End (TND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Always False (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
One Shot (ONS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
One Shot Rising (OSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
One Shot Falling (OSF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Sequential Function Chart Reset (SFR). . . . . . . . . . . . . . . . 13-17
End of Transition (EOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
User Interrupt Disable (UID) . . . . . . . . . . . . . . . . . . . . . . . . 13-19
User Interrupt Enable (UIE). . . . . . . . . . . . . . . . . . . . . . . . . 13-20

Process Control Instruction PID Chapter 14
Using PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
PID Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Using PID Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Conversion of Gain Constants . . . . . . . . . . . . . . . . . . . . . 14-3
Integral Term Implementation . . . . . . . . . . . . . . . . . . . . . 14-3
Derivative Term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Setting Input/Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Implementing Scaling to Engineering Units . . . . . . . . . . . . . 14-5
Setting the Dead Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using No Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Selecting the Derivative Term (Acts on PV or Error) . . . . . . . 14-7

1785-6.1 November 1998


Setting Output Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Using Output Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Anti-Reset Windup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Using a Manual Mode Operation (Bumpless Transfer) . . . 14-8
Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Feedforward or Output Biasing . . . . . . . . . . . . . . . . . . . . . . 14-9
Resume Last State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
PID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Using No Back Calculation. . . . . . . . . . . . . . . . . . . . . . . 14-11
Operational Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Integer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
PD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Using an Integer Data File Type for the Control Block. . . . . 14-14
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-16
Using a PD File Type for the Control Block . . . . . . . . . . . . . 14-18
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-23
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 14-25
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Transferring Data to the PID Instruction . . . . . . . . . . . . . 14-25
Loop Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Number of PID Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Loop Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Descaling Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
PID Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Integer Block (N) Examples . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
PD Block Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Ladder Logic Simulation of a Manual Control Station . . . 14-37
Cascading Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Ratio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Process Variable Tracking . . . . . . . . . . . . . . . . . . . . . . . 14-39
PID Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40

1785-6.1 November 1998


Block-Transfer Instructions Chapter 15
BTR and BTW and ControlNet I/O Using Block Transfer and ControlNet I/O
Transfer Instruction CIO Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Using Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . 15-1
Block-Transfer Read (BTR) and Block-Transfer Write (BTW). 15-3
Block-Transfer Request Queue . . . . . . . . . . . . . . . . . . . . 15-3
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Requested Word Count (.RLEN) . . . . . . . . . . . . . . . . . . . . 15-8
Transmitted Word Count (.DLEN) . . . . . . . . . . . . . . . . . . . 15-8
File Number (.FILE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Element Number (.ELEM). . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 15-10
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 15-12
Block Transfer Timing – Classic PLC-5 Processors . . . . . . 15-13
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Waiting Time in the Queue. . . . . . . . . . . . . . . . . . . . . . . 15-13
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Block Transfer Timing – Enhanced PLC-5 Processors . . . . 15-14
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Waiting Time in the Holding Area . . . . . . . . . . . . . . . . . . 15-14
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Example Bidirectional Alternating Block-Transfer. . . . . . 15-16
Example Bidirectional Alternating Repeating
Block-Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Example Bidirectional Continuous Block-Transfer . . . . . 15-18
Example Directional Non-Continuous Block-Transfer . . . 15-19
Example Directional Repeating Block Transfer . . . . . . . . 15-19
Example Directional Continuous Block-Transfer . . . . . . . 15-20
Example Buffering Block Transfer-Data . . . . . . . . . . . . . 15-21
ControlNet I/O Transfer (CIO) Instruction . . . . . . . . . . . . . . 15-22
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Using the CIO Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Using the CT Control Block . . . . . . . . . . . . . . . . . . . . . . 15-25

1785-6.1 November 1998


Message Instruction MSG Chapter 16
Using the Message Instruction. . . . . . . . . . . . . . . . . . . . . . . 16-1
Message (MSG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
MSG Data Entry Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Using the Message Instruction for Ethernet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Using the Message Instruction for PLC-5 Ethernet Interface
Module Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Configuring an Ethernet Multihop MSG Instruction. . . . . . . . 16-9
Using the Message Instruction for ControlNet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Configuring a ControlNet Multihop MSG Instruction . . . . . . 16-11
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Error Code (.ERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Requested Length (.RLEN) . . . . . . . . . . . . . . . . . . . . . . . 16-13
Transmitted Length (.DLEN) . . . . . . . . . . . . . . . . . . . . . . 16-13
Communication Command . . . . . . . . . . . . . . . . . . . . . . 16-14
External Data Table Addresses. . . . . . . . . . . . . . . . . . . . 16-15
PLC-2 to PLC-5 Compatibility Files . . . . . . . . . . . . . . . . 16-15
Sending SLC Typed Logical Read and Typed Logical
Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
Monitoring a Message Instruction . . . . . . . . . . . . . . . . . . . 16-17
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 16-18
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 16-19
MSG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22

1785-6.1 November 1998


ASCII Instructions Chapter 17
ABL, ACB, ACI, ACN, AEX, AIC, AHL, Using ASCII Instructions
ARD, ARL, ASC, ASR, AWA, AWT Enhanced PLC-5 Processors Only . . . . . . . . . . . . . . . . . . . . 17-1
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Length (.LEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Position (.POS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Using Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Test Buffer for Line (ABL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Number of Characters in Buffer (ACB) . . . . . . . . . . . . . . . . . 17-5
ASCII String to Integer (ACI) . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
ASCII String Concatenate (ACN) . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII String Extract (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII Set or Reset Handshake Lines (AHL). . . . . . . . . . . . . . 17-8
ASCII Integer to String (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
ASCII Read Characters (ARD). . . . . . . . . . . . . . . . . . . . . . . 17-10
ASCII Read Line (ARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
ASCII String Search (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
ASCII String Compare (ASR). . . . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write with Append (AWA) . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write (AWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

Custom Application Routine Chapter 18
Instructions SDS, DFA Chapter Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Smart Directed Sequencer (SDS) Overview . . . . . . . . . . . . . 18-2
Programming the SDS Instruction . . . . . . . . . . . . . . . . . . 18-2
Diagnostic Fault Annunciator (DFA) Overview . . . . . . . . . . . 18-3
Programming the DFA Instruction . . . . . . . . . . . . . . . . . . 18-3

1785-6.1 November 1998


Instruction Timing and Appendix A-1
Memory Requirements Instruction Timing and Memory Requirements. . . . . . . . . . . . A-1
Timing for Enhanced PLC-5 Processors. . . . . . . . . . . . . . . . . A-2
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . A-2
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Timing for Classic PLC-5 Processors . . . . . . . . . . . . . . . . . . A-10
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . A-10
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Program Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
Direct and Indirect Elements: Enhanced PLC-5 Processors . A-17
Direct and Indirect Elements: Classic PLC-5 Processors . . . A-18
Indirect Bit or Elements Addresses: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19
Additional Timing Considerations: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

SFC Reference Appendix B-1
Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
SFC Status Information in the Processor Status File. . . . . . . . B-1
Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Dynamic Constraints – Classic PLC-5 Processors Only . . . . . B-5
Scanning Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Step and Transition Scanning . . . . . . . . . . . . . . . . . . . . . . B-7
Selected Branch Scanning. . . . . . . . . . . . . . . . . . . . . . . . . B-8
Simultaneous Branch Scanning . . . . . . . . . . . . . . . . . . . . . B-9
SFC Example and Scan Sequence . . . . . . . . . . . . . . . . . . B-11
Run Times – Classic PLC-5 Processors . . . . . . . . . . . . . . . . B-12
Using Sequence Diagrams to Determine Run Time . . . . . B-13
Using Equations to Determine Run Time . . . . . . . . . . . . . B-14

Valid Data Types for Appendix C-1
Instruction Operands Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Instruction Operands and Valid Data Types . . . . . . . . . . . . . . C-1

1785-6.1 November 1998

Chapter 1
Relay-Type Instructions XIC, XIO, OTE,
OTL, OTU, IIN, IOT, IDI, IDO
Using Relay-Type Instructions 8VH UHODWSH LQVWUXFWLRQV WR PRQLWRU DQG FRQWURO WKH VWDWXV RI ELWV LQ
WKH GDWD WDEOH VXFK DV LQSXW ELWV RU WLPHU FRQWUROZRUG ELWV 7KH UHOD
LQVWUXFWLRQV OHW RX

If You Want to: Use this Instruction: Found on Page:

Examine a bit for an ON condition XIC 1-3

Examine a bit for an OFF condition XIO 1-3

Hold a bit ON or OFF (non-retentive) OTE 1-4

Latch a bit to ON (retentive) OTL 1-4

Unlatch a bit to OFF (retentive) OTU 1-5

Immediately update input image bits IIN 1-6

Immediately update outputs IOT 1-7

Immediately perform an update of IDI 1-8
the ControlNet™ data input file from
the ControlNet memory buffers.

Immediately perform an update of IDO 1-8
the ControlNet memory buffers from
the source file before the next
output-image update

:LWK WKHVH LQVWUXFWLRQV RX FDQ DGGUHVV ELWV LQ DOO VHFWLRQV RI GDWD
VWRUDJH EXW WKH H[DPSOHV LQ WKLV FKDSWHU RQO VKRZ KRZ WR DGGUHVV
ELWV LQ WKH ,2 LPDJH ILOHV
)RU PRUH LQIRUPDWLRQ RQ WKH RSHUDQGV DQG YDOLG GDWD WSHVYDOXHV RI
HDFK RSHUDQG

XVHG E WKH LQVWUXFWLRQV GLVFXVVHG LQ WKLV FKDSWHU VHH
$SSHQGL[
,I RX XVH UHODWSH LQVWUXFWLRQ 27( 27/ RU 278

ZLWK LQGLUHFW
DGGUHVVHV WR VHW RU UHVHW D ELW LQ WKH FRQWURO ILOH RI D EORFNWUDQVIHU RU
PHVVDJH LQVWUXFWLRQ WKHUH PD EH FRQIOLFWLQJ UHVXOWV (YHQ WKRXJK
WKH ELW LQVWUXFWLRQ LV H[HFXWHG WR VHW RU UHVHW D ELW LWV UHVXOW PLJKW EH
RYHUZULWWHQ E WKH EORFNWUDQVIHU RU PHVVDJH RSHUDWLRQ WKDW VHWV RU
UHVHWV WKH VDPH ELW 7KHVH DUH DVQFKURQRXV RSHUDWLRQV 7KH ODVW
RSHUDWLRQ WR VHW RU UHVHW WKH ELW LV WKH YDOXH WKDW LV VDYHG LQ WKH
GDWD WDEOH

1785-6.1 November 1998

1-2 Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO

I/O Image Files in Data Storage
7KH LQSXW LPDJH ILOH LQ WKH SURFHVVRU VWRUHV WKH VWDWXV RI LQSXW VHQVRUV
FRQQHFWHG WR LQSXW PRGXOH WHUPLQDOV

If the Input Sensor Is: Then Its Corresponding Input Image Bit Is:

closed (on) on (1)

open (off) off (0)

RX SURJUDP LQVWUXFWLRQV LQ ODGGHU ORJLF WR PRQLWRU ELWV 8VH D
ORJLFDO DGGUHVV IRU WKH ELW
7KH RXWSXW LPDJH ILOH FRQWUROV WKH VWDWXV RI DFWXDWRUV ZLUHG WR RXWSXW
PRGXOH WHUPLQDOV

If the Output Image Bit Is: Then Its Corresponding Output Is:

on (1) energized (on)

off (0) de-energized (off)

RX SURJUDP LQVWUXFWLRQV LQ ODGGHU ORJLF WR FRQWURO ELWV

Rung Logic
$V HDFK FRQGLWLRQLQJ LQVWUXFWLRQ LV H[HFXWHG WKH DGGUHVVHG ELW LV
H[DPLQHG WR VHH LI LW PDWFKHV D FHUWDLQ FRQGLWLRQ RQ RU RII

,I D
FRPSOHWH SDWK RI WUXH FRQGLWLRQV H[DPLQHG IRU DUH IRXQG WKH UXQJ
LV VHW WR WUXH 7KH UXQJ PXVW FRQWDLQ D FRQWLQXRXV SDWK RI WUXH
LQVWUXFWLRQV IURP WKH VWDUW RI WKH UXQJ WR WKH RXWSXW IRU WKH RXWSXW
WR EH HQDEOHG

1785-6.1 November 1998

Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO 1-3

Examine On (XIC)

Description: :KHQ D GHYLFH FORVHV LWV FLUFXLW WKH PRGXOH ZKRVH LQSXW WHUPLQDO LV
ZLUHG WR WKH GHYLFH GHWHFWV WKH FORVHG FLUFXLW 7KH SURFHVVRU UHIOHFWV
WKLV 21 VWDWH LQ WKH GDWD WDEOH :KHQ WKH SURFHVVRU ILQGV DQ ;,
LQVWUXFWLRQ WKDW DGGUHVVHV WKH ELW WKDW FRUUHVSRQGV WR WKH LQSXW
Example:
WHUPLQDO WKH SURFHVVRU GHWHUPLQHV ZKHWKHU WKH GHYLFH LV 21 FORVHG

I:012 ,I WKH SURFHVVRU ILQGV DQ 21 VWDWH LW VHWV WKH ORJLF IRU WKLV LQVWUXFWLRQ
WUXH LI WKH SURFHVVRU ILQGV DQ 2)) VWDWH LW VHWV WKH ORJLF IRU WKH
07 LQVWUXFWLRQ QRW WUXH
If you find an ON condition at bit I:012/07 in
the input table, set this instruction true. ,I WKH ;, LQVWUXFWLRQ LV WKH RQO FRQGLWLRQLQJ LQVWUXFWLRQ RQ WKH UXQJ
This bit corresponds to input terminal 7 of a WKH SURFHVVRU HQDEOHV WKH RXWSXW LQVWUXFWLRQ ZKHQ WKH ;, LQVWUXFWLRQ
module in I/O group 2 of I/O rack 1. If the input LV WUXH LQSXW FORVHG

7KH SURFHVVRU GLVDEOHV DQ RXWSXW LQVWUXFWLRQ
circuit is true, the instruction is true.
ZKHQ WKH ;, LQVWUXFWLRQ LV IDOVH LQSXW RSHQ

7KH H[DPLQHRQ LQVWUXFWLRQ LV WUXH RU IDOVH GHSHQGLQJ RQ ZKHWKHU WKH
SURFHVVRU ILQGV DQ 21 RU 2)) FRQGLWLRQ DW WKH DGGUHVVHG ELW

If the Bit Is: Then the Instruction Is: Bit Logic State:

on true 1

off false 0

Examine Off (XIO)

Description: :KHQ D GHYLFH RSHQV LWV FLUFXLW WKH PRGXOH ZKRVH LQSXW WHUPLQDO LV
ZLUHG WR WKH GHYLFH GHWHFWV DQ RSHQ FLUFXLW 7KH SURFHVVRU UHIOHFWV
WKLV 2)) VWDWH LQ WKH GDWD WDEOH :KHQ WKH SURFHVVRU ILQGV DQ ;,2
Example: LQVWUXFWLRQ WKDW DGGUHVVHV WKH ELW WKDW FRUUHVSRQGV WR WKH LQSXW
WHUPLQDO WKH SURFHVVRU GHWHUPLQHV ZKHWKHU WKH GHYLFH LV 2))
I:012
RSHQ

,I WKH SURFHVVRU ILQGV DQ 2)) VWDWH LW VHWV WKH ORJLF IRU WKLV
07
LQVWUXFWLRQ WUXH ,I WKH SURFHVVRU ILQGV DQ 21 VWDWH LW VHWV WKH ;,2
LQVWUXFWLRQ WR IDOVH
If you find an OFF condition at bit I:012/07 in
the input table, set this instruction true. ,I WKH ;,2 LQVWUXFWLRQ LV WKH RQO FRQGLWLRQLQJ LQVWUXFWLRQ RQ WKH UXQJ
This bit corresponds to input terminal 7 of a WKH SURFHVVRU HQDEOHV WKH RXWSXW LQVWUXFWLRQ ZKHQ WKH ;,2 LQVWUXFWLRQ
module in I/O group 2 of I/O rack 1. If the input LV WUXH LQSXW RSHQ

circuit is false, the instruction is true.
7KH H[DPLQH RII LQVWUXFWLRQ LV WUXH RU IDOVH GHSHQGLQJ RQ ZKHWKHU WKH
SURFHVVRU ILQGV DQ 2)) RU 21 FRQGLWLRQ DW WKH DGGUHVVHG ELW

If the Bit Is: Then the Instruction Is: Bit Logic State:

off true 0

on false 1

1785-6.1 November 1998


Energize (OTE)

Description: 8VH WKH 27( LQVWUXFWLRQ WR FRQWURO D ELW LQ PHPRU ,I WKH ELW
FRUUHVSRQGV WR DQ RXWSXW PRGXOH WHUPLQDO WKH GHYLFH ZLUHG WR WKLV
WHUPLQDO LV HQHUJL]HG ZKHQ WKH LQVWUXFWLRQ LV HQDEOHG DQG
Example: GHHQHUJL]HG ZKHQ WKH LQVWUXFWLRQ LV GLVDEOHG ,I WKH LQSXW FRQGLWLRQV
WKDW SUHFHGH WKH 27( LQVWUXFWLRQ DUH WUXH WKH SURFHVVRU HQDEOHV WKH
O:013 27( LQVWUXFWLRQ ,I WKH LQSXW FRQGLWLRQV WKDW SUHFHGH WKH 27(
LQVWUXFWLRQ DUH IDOVH WKH SURFHVVRU GLVDEOHV WKH 27( LQVWUXFWLRQ
01 :KHQ UXQJ FRQGLWLRQV EHFRPH IDOVH WKH FRUUHVSRQGLQJ GHYLFH
Turn ON bit O:013/01 of the output image table if GHHQHUJL]HV
the rung is true. Turn it OFF if the rung is false.
$Q 27( LQVWUXFWLRQ LV VLPLODU WR D UHOD FRLO 7KH 27( LQVWUXFWLRQ LV
This bit corresponds to output terminal 01 of a
module in /O group 3 of I/O rack 1. FRQWUROOHG E SUHFHGLQJ LQSXW LQVWUXFWLRQV WKH UHOD FRLO LV FRQWUROOHG
E FRQWDFWV LQ LWV KDUGZLUHG UXQJ
7KH 27( LQVWUXFWLRQ WHOOV WKH SURFHVVRU WR FRQWURO WKH DGGUHVVHG ELW
EDVHG RQ WKH UXQJ FRQGLWLRQ

If the Rung Is: Then the Processor Turns the Bit: Bit Logic State:

true on 1

false off 0

Latch (OTL)

Description: 7KH 27/ LQVWUXFWLRQ LV D UHWHQWLYH RXWSXW LQVWUXFWLRQ WKDW FDQ RQO
L WXUQ RQ D ELW LW FDQQRW WXUQ RII D ELW

7KLV LQVWUXFWLRQ LV XVXDOO XVHG
LQ SDLUV ZLWK DQ 278 XQODWFK

LQVWUXFWLRQ ZLWK ERWK LQVWUXFWLRQV
Example: DGGUHVVLQJ WKH VDPH ELW
O:013
:KHQ RX DVVLJQ DQ DGGUHVV WR DQ 27/ LQVWUXFWLRQ WKDW FRUUHVSRQGV
L
01
WR D WHUPLQDO RI DQ RXWSXW PRGXOH WKH RXWSXW GHYLFH ZLUHG WR WKLV
WHUPLQDO LV HQHUJL]HG ZKHQ WKH SURFHVVRU VHWV HQDEOHV

WKH ELW LQ
Turn ON bit O:013/01 of the output image table SURFHVVRU PHPRU ,I WKH LQSXW FRQGLWLRQV WKDW SUHFHGH WKH 27/
if the rung is true.
This bit corresponds to output terminal 1 of a
LQVWUXFWLRQ DUH WUXH WKH SURFHVVRU HQDEOHV WKH 27/ LQVWUXFWLRQ :KHQ
module in I/O group 3 of I/O rack 1. UXQJ FRQGLWLRQV EHFRPH IDOVH DIWHU EHLQJ WUXH

WKH ELW UHPDLQV VHW
DQG WKH FRUUHVSRQGLQJ RXWSXW GHYLFH UHPDLQV HQHUJL]HG 8VH WKH 278
LQVWUXFWLRQ WR WXUQ 2)) WKH ELW RX ODWFKHG RQ ZLWK WKH 27/
LQVWUXFWLRQ

1785-6.1 November 1998


:KHQ HQDEOHG WKH ODWFK LQVWUXFWLRQ WHOOV WKH SURFHVVRU WR WXUQ RQ WKH
DGGUHVVHG ELW 7KHUHDIWHU WKH ELW UHPDLQV RQ UHJDUGOHVV RI WKH UXQJ
FRQGLWLRQ XQWLO WKH ELW LV WXUQHG RII WSLFDOO E DQ XQODWFK 278

LQVWUXFWLRQ LQ DQRWKHU UXQJ

If the Rung Is: Then the Processor Turns the Bit:

true on

false no change

:KHQ WKH SURFHVVRU FKDQJHV IURP 5XQ WR 3URJUDP PRGH RU ZKHQ WKH
SURFHVVRU ORVHV SRZHU DQG WKHUH LV EDWWHU EDFNXS

WKH ODVW WUXH 27/
LQVWUXFWLRQ FRQWLQXHV WR FRQWURO WKH ELW LQ PHPRU 7KH ODWFKHG RXWSXW
GHYLFH LV HQHUJL]HG HYHQ WKRXJK WKH UXQJ FRQGLWLRQV WKDW FRQWURO WKH
LQVWUXFWLRQ PD KDYH JRQH IDOVH
,PSRUWDQW 7KH 27/ LQVWUXFWLRQ LV UHWHQWLYH :KHQ WKH SURFHVVRU
ORVHV SRZHU LV VZLWFKHG WR 3URJUDP PRGH RU 7HVW
PRGH RU GHWHFWV D PDMRU IDXOW RXWSXWV JR RII EXW WKH
VWDWHV RI UHWHQWLYH RXWSXWV DUH UHWDLQHG LQ PHPRU
:KHQ WKH SURFHVVRU UHVXPHV RSHUDWLRQ LQ 5XQ PRGH
UHWHQWLYH RXWSXWV LPPHGLDWHO UHWXUQ WR WKHLU SUHYLRXV
VWDWHV 1RQUHWHQWLYH RXWSXWV VXFK DV 27( RXWSXWV DUH
UHVHW

Unlatch (OTU)

Description: 7KH 278 LQVWUXFWLRQ LV D UHWHQWLYH RXWSXW LQVWUXFWLRQ WKDW FDQ RQO
WXUQ RII D ELW LW FDQQRW WXUQ RQ D ELW

7KLV LQVWUXFWLRQ LV XVXDOO XVHG
U
LQ SDLUV ZLWK DQ 27/ RXWSXW ODWFK

LQVWUXFWLRQ ZLWK ERWK LQVWUXFWLRQV
DGGUHVVLQJ WKH VDPH ELW 7KH 278 LQVWUXFWLRQ WXUQV 2)) WKH ELW
Example: ZKLFK ZDV WXUQHG 21 ODWFKHG

E WKH 27/ LQVWUXFWLRQ
O:013
:KHQ WKH SURFHVVRU FKDQJHV IURP 5XQ WR 3URJUDP PRGH RU ZKHQ WKH
U
SURFHVVRU ORVHV SRZHU DQG WKHUH LV EDWWHU EDFNXS

WKH ELW LV UHWDLQHG
01
LQ WKH VWDWH VHW E WKH ODVW UXQJ RI WKH ODWFKXQODWFK SDLU WKDW ZDV WUXH
Turn OFF bit O:013/01 of the output image table
if the rung is true. 7KH XQODWFK LQVWUXFWLRQ WHOOV WKH SURFHVVRU WR WXUQ RII WKH DGGUHVVHG ELW
This bit corresponds to output terminal 1 of a EDVHG RQ WKH UXQJ FRQGLWLRQ 7KHUHDIWHU WKH ELW UHPDLQV RII
module in I/O group 3 in I/O rack 1. UHJDUGOHVV RI WKH UXQJ FRQGLWLRQ XQWLO LW LV WXUQHG RQ WSLFDOO E D
27/ LQVWUXFWLRQ LQ DQRWKHU UXQJ

If the Rung is: Then the Processor Turns the Bit:

true off

false no change

1785-6.1 November 1998


Immediate Input (IIN)

Description: 7KH ,,1 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW ZKHQ HQDEOHG
XSGDWHV D ZRUG RI LQSXWLPDJH ELWV EHIRUH WKH QH[W UHJXODU
IIN LQSXWLPDJH XSGDWH
Example: )RU LQSXWV LQ WKH ORFDO FKDVVLV WKH SURJUDP VFDQ LV LQWHUUXSWHG
RRG ZKLOH WKH LQSXWV RI WKH DGGUHVVHG ,2 JURXS DUH H[DPLQHG 7KLV
IIN VHWV WKH LQSXWLPDJH ELWV WR WKH FXUUHQW VWDWHV RI WKH LQSXWV EHIRUH
Where: WKH SURJUDP VFDQ FRQWLQXHV ,I WKH SURJUDP UHDFKHV DQ HQDEOHG
RR = I/O rack number ,,1 LQVWUXFWLRQ ZKLOH D EORFNWUDQVIHU ZLWK WKH ORFDO FKDVVLV LV LQ
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20
00-07 PLC-5/25, -5/30
SURJUHVV WKH SURFHVVRU FRPSOHWHV WKH EORFNWUDQVIHU EHIRUH H[HFXWLQJ
000-177 PLC-5/40, -5/40L WKH ,,1 LQVWUXFWLRQ
000-277 PLC-5/60, -5/60L, -5/80
G = I/O group number (0 - 7) )RU LQSXWV LQ D UHPRWH FKDVVLV WKH SURJUDP VFDQ LV LQWHUUXSWHG RQO
001 WR XSGDWH WKH LQSXW LPDJH ZLWK WKH ODWHVW VWDWHV RI WKH LQSXWV DV IRXQG
IIN LQ WKH UHPRWH ,2 EXIIHU IURP WKH PRVW UHFHQW UHPRWH ,2 VFDQ

7KH
When the input conditions are true, update the LQSXWV DUH QRW VFDQQHG EHIRUH WKH SURJUDP VFDQ FRQWLQXHV
input image word corresponding to I/O rack 0,
group 1. 3ODFH WKH UXQJ ZLWK WKH ,,1 LQVWUXFWLRQ LPPHGLDWHO EHIRUH UXQJV WKDW
H[DPLQH FULWLFDO LQSXW ELWV XSGDWHG E WKH ,,1 LQVWUXFWLRQ
)RU WKH ,,1 LQVWUXFWLRQ RX RQO QHHG WR HQWHU WKH ,2 UDFN QXPEHU
DQG WKH ,2 JURXS QXPEHU RX GR QRW HQWHU D ILOH QXPEHU

$77(17,21 'R QRW HQWHU DQ DGGUHVV WKDW LQFOXGHV D
ILOH QXPEHU VXFK DV , 7KH SURFHVVRU LQWHUSUHWV WKH
ELW SDWWHUQ IRXQG DW WKDW DGGUHVV DV WKH ,2 UDFN DQG ,2
JURXS QXPEHU RI WKH LQSXWV WR XSGDWH 8QH[SHFWHG
RSHUDWLRQ ZLOO UHVXOW ZLWK SRVVLEOH GDPDJH WR HTXLSPHQW
DQG LQMXU WR SHUVRQQHO

)RU PRUH LQIRUPDWLRQ RQ ,2 VFDQQLQJ DQG EORFNWUDQVIHUV VHH
FKDSWHU

1785-6.1 November 1998


Immediate Output (IOT)

Description: 7KH ,27 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW ZKHQ HQDEOHG
IOT
XSGDWHV DQ ,2 JURXS RI RXWSXWV EHIRUH WKH QH[W QRUPDO RXWSXW
LPDJH XSGDWH
Example:
)RU RXWSXWV LQ WKH ORFDO FKDVVLV WKH SURJUDP VFDQ LV LQWHUUXSWHG ZKLOH
RRG
WKH RXWSXWV RI WKH DGGUHVVHG ,2 JURXS DUH H[DPLQHG 7KLV VHWV WKH
IOT
RXWSXW FLUFXLWV WR WKH FXUUHQW VWDWHV RI WKH RXWSXW ELWV LQ WKH RXWSXW
Where:
LPDJH WDEOH EHIRUH WKH SURJUDP VFDQ FRQWLQXHV ,I WKH SURJUDP
RR = I/O rack number
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20 UHDFKHV DQ HQDEOHG ,27 LQVWUXFWLRQ ZKLOH D EORFNWUDQVIHU LV LQ
00-07 PLC-5/25, -5/30 SURJUHVV WKH SURFHVVRU FRPSOHWHV WKH EORFNWUDQVIHU EHIRUH H[HFXWLQJ
000-177 PLC-5/40, -5/40L
000-277 PLC-5/60, -5/60L, -5/80 WKH ,27 LQVWUXFWLRQ
G = I/O group number (0 - 7)
)RU RXWSXWV LQ D UHPRWH FKDVVLV WKH SURJUDP VFDQ LV LQWHUUXSWHG RQO
001 WR XSGDWH WKH UHPRWH ,2 EXIIHU ZLWK WKH FXUUHQW VWDWHV RI WKH
IOT
RXWSXWLPDJH ELWV 7KLV PDNHV WKHVH VWDWHV LPPHGLDWHO DYDLODEOH IRU
When the input conditions are true, update the WKH QH[W UHPRWH ,2 VFDQ ZKLOH WKH SURJUDP VFDQ FRQWLQXHV 7KH
output image word corresponding to I/O rack 0,
group 1.
RXWSXWV DUH QRW VFDQQHG EHIRUH WKH SURJUDP VFDQ FRQWLQXHV
3ODFH WKH UXQJ ZLWK WKH ,27 RXWSXW LQVWUXFWLRQ LPPHGLDWHO DIWHU
UXQJV WKDW FRQWURO FULWLFDO RXWSXW LPDJH ELWV WR EH XSGDWHG E WKH
,27 LQVWUXFWLRQ
)RU WKH ,27 LQVWUXFWLRQ RX RQO QHHG WR HQWHU WKH ,2 UDFN QXPEHU
DQG WKH ,2 JURXS QXPEHU RX GR QRW QHHG WR HQWHU WKH ILOH QXPEHU

$77(17,21 'R QRW HQWHU DQ DGGUHVV WKDW LQFOXGHV D
ILOH QXPEHU VXFK DV 2 7KH SURFHVVRU LQWHUSUHWV WKH
ELW SDWWHUQ IRXQG DW WKDW DGGUHVV DV WKH ,2 UDFN DQG ,2
JURXS QXPEHU RI WKH RXWSXWV WR EH XSGDWHG 8QH[SHFWHG
RSHUDWLRQ ZLOO UHVXOW ZLWK SRVVLEOH GDPDJH WR HTXLSPHQW
DQG LQMXU WR SHUVRQQHO

)RU PRUH LQIRUPDWLRQ RQ ,2 VFDQQLQJ DQG EORFNWUDQVIHUV VHH
FKDSWHU

1785-6.1 November 1998


Immediate Data Input (IDI)

Description: :KHQ WKH UXQJ JRHV WUXH WKH ,', LQVWUXFWLRQ SHUIRUPV DQ LPPHGLDWH
IDI
XSGDWH RI WKH RQWURO1HW GDWD LQSXW ILOH IURP WKH RQWURO1HW PHPRU
IMMEDIATE DATA INPUT
EXIIHUV EHIRUH WKH QH[W QRUPDO LQSXWLPDJH XSGDWH ZKLFK RFFXUV DW
Data file offset 232

Length 10
WKH HQG RI WKH SURJUDP VFDQ

Destination N10:232
7R SURJUDP DQ ,', LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ LQIRUPDWLRQ WKDW LW VWRUHV LQ LWV FRQWURO EORFN
‡ 'DWD ILOH RIIVHW VSHFLILHV WKH RIIVHW LQWR WKH 'DWD ,QSXW )LOH ',)

ZKHUH ZRUGV DUH UHDG ± FDQ EH DQ LPPHGLDWH YDOXH

RU D
ORJLFDO DGGUHVV WKDW VSHFLILHV WKH GDWD LPDJH ILOH RIIVHW
‡ /HQJWK VSHFLILHV WKH QXPEHU RI ZRUGV WR EH WUDQVIHUUHG ± DQ
LPPHGLDWH YDOXH

RU D ORJLFDO DGGUHVV WKDW VSHFLILHV WKH
QXPEHU RI ZRUGV WR EH WUDQVIHUUHG
‡ 'HVWLQDWLRQ VSHFLILHV D GDWD WDEOH DGGUHVV WR EH XVHG DV WKH
GHVWLQDWLRQ RI WKH ZRUGV WR EH WUDQVIHUUHG
,PSRUWDQW 7KH 'HVWLQDWLRQ VKRXOG EH WKH PDWFKLQJ GDWDWDEOH
DGGUHVV LQ WKH 'DWD ,QSXW )LOH ',)

H[FHSW ZKHQ RX
XVH WKH LQVWUXFWLRQ WR HQVXUH GDWDEORFN LQWHJULW LQ WKH
FDVH RI 6HOHFWDEOH 7LPHG ,QWHUUXSWV 67,V

)RU PRUH
LQIRUPDWLRQ VHH SDJH

Immediate Data Output (IDO)

Description: :KHQ WKH UXQJ JRHV WUXH WKH ,'2 LQVWUXFWLRQ SHUIRUPV DQ LPPHGLDWH
IDO
XSGDWH RI WKH RQWURO1HW PHPRU EXIIHUV IURP WKH VRXUFH ILOH EHIRUH
IMMEDIATE DATA OUTPUT WKH QH[W RXWSXWLPDJH XSGDWH VHQGLQJ WKH XSGDWHG GDWD RXWSXW ILOH
LQIRUPDWLRQ DFURVV WKH RQWURO1HW QHWZRUN WR WKH DSSURSULDWH
Data file offset 232

Length 10

Source N7:232
RQWURO1HW GHYLFH
7R SURJUDP DQ ,'2 LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ LQIRUPDWLRQ WKDW LW VWRUHV LQ LWV FRQWURO EORFN
‡ 'DWD ILOH RIIVHW VSHFLILHV WKH RIIVHW LQWR WKH 'DWD 2XWSXW )LOH
'2)

ZKHUH ZRUGV DUH ZULWWHQ ± FDQ EH DQ LPPHGLDWH YDOXH

RU D ORJLFDO DGGUHVV WKDW VSHFLILHV WKH GDWD LPDJH
ILOH RIIVHW
‡ /HQJWK VSHFLILHV WKH QXPEHU RI ZRUGV WR EH WUDQVIHUUHG ± DQ
LPPHGLDWH YDOXH

RU D ORJLFDO DGGUHVV WKDW VSHFLILHV WKH
QXPEHU RI ZRUGV WR EH WUDQVIHUUHG
‡ 6RXUFH VSHFLILHV D GDWD WDEOH DGGUHVV WR EH XVHG DV WKH VRXUFH RI
WKH ZRUGV WR EH WUDQVIHUUHG
,PSRUWDQW 7KH 6RXUFH VKRXOG EH WKH PDWFKLQJ GDWDWDEOH DGGUHVV LQ
WKH 'DWD 2XWSXW )LOH '2)

H[FHSW ZKHQ RX XVH WKH
LQVWUXFWLRQ WR HQVXUH GDWDEORFN LQWHJULW LQ WKH FDVH RI
6HOHFWDEOH 7LPHG ,QWHUUXSWV 67,V

)RU PRUH
LQIRUPDWLRQ VHH SDJH

1785-6.1 November 1998


Using IDI and IDO Instructions RX FDQ XVH WKH ,', DQG ,'2 LQVWUXFWLRQV IRU LPPHGLDWH GDWD LQSXW
DQG RXWSXW RQ RQWURO1HW
)RU PRUH GHWDLOHG LQIRUPDWLRQ DERXW ZULWLQJ ODGGHU SURJUDPV VHH
RXU SURJUDPPLQJ PDQXDO
,PSRUWDQW %H FDUHIXO ZKHQ XVLQJ 6HOHFWDEOH 7LPHG ,QWHUUXSWV
67,V

ZLWK D SURJUDP RQ D RQWURO1HW QHWZRUN

$ 6HOHFWDEOH 7LPHG ,QWHUUXSW 67,

SHULRGLFDOO LQWHUUXSWV SULPDU
SURJUDP H[HFXWLRQ LQ RUGHU WR UXQ D VXESURJUDP WR FRPSOHWLRQ ,I DQ
67, RFFXUV ZKLOH D QRUPDO RQWURO1HW QRQGLVFUHWH ,2 WUDQVIHU RU D
RQWURO1HW ,PPHGLDWH 'DWD ,2 LQVWUXFWLRQ ,', RU ,'2

LV LQ
SURJUHVV DQG WKH ERWK RSHUDWH RQ WKH VDPH VHW RI GDWD WKH LQWHJULW RI
WKDW EORFN RI GDWD LV MHRSDUGL]HG
7R HQVXUH GDWDEORFN LQWHJULW ZULWH RXU 67, URXWLQH VR WKDW LW
RSHUDWHV RQ LWV RZQ FRS RI WKH GDWD EORFN WKDW LW QHHGV 8VH
RQWURO1HW ,PPHGLDWH 'DWD ,2 LQVWUXFWLRQV ,', DQG ,'2

ZLWKLQ
RXU 67, WR FRS WKH QHHGHG EORFN RI GDWD RXW WR DQG EDFN IURP D
WHPSRUDU ORFDWLRQ WKDW LV GLIIHUHQW IURP WKDW XVHG E WKH QRUPDO
GDWD WDEOH
)RU GHWDLOHG LQIRUPDWLRQ RQ 67,V VHH RXU VRIWZDUH XVHU PDQXDO

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 2
Timer Instructions TON, TOF, RTO
Counter Instructions CTU, CTD
Reset RES
Using Timers and Counters 7LPHUV DQG FRXQWHUV OHW RX FRQWURO RSHUDWLRQV EDVHG RQ WLPH RU
QXPEHU RI HYHQWV 7DEOH $ OLVWV WKH DYDLODEOH WLPHU DQG FRXQWHU
LQVWUXFWLRQV
Table 2.A
Available Timer and Counter Instructions


Delay turning on an output TON 2-4

Delay turning off an output TOF 2-7

Time an event retentively RTO 2-10

Count up CTU 2-15

Count down CTD 2-17

Reset a counter, timer, or counter RE 2-20
instruction

HDFK RSHUDQG

$SSHQGL[

Using Timers
%HIRUH RX SURJUDP WLPHU LQVWUXFWLRQV RX QHHG WR XQGHUVWDQG WKH
SDUDPHWHUV WKDW RX HQWHU IRU WLPHU LQVWUXFWLRQV DQG KRZ WLPHU
DFFXUDF ZRUNV

1785-6.1 November 1998

2-2 Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES

Entering Parameters 7R SURJUDP D WLPHU LQVWUXFWLRQ SURYLGH WKH SURFHVVRU ZLWK WKH
TON IROORZLQJ LQIRUPDWLRQ
TIMER ON DELAY EN
Timer
‡ 7LPHU LV WKH WLPHU FRQWURO DGGUHVV LQ WKH WLPHU 7

DUHD RI GDWD
Time base DN VWRUDJH 8VH WKH IROORZLQJ DGGUHVV IRUPDW
Preset
Accum T f : s

timer structure number (0-999)

timer file number (3-999)
timer (file type)

,PSRUWDQW RX FDQ XVH DQ WLPHU ILOH QXPEHU IURP WR
KRZHYHU WKH GHIDXOW WLPHU ILOH QXPEHU LV ,I RX ZDQW
WR VSHFLI D WLPHU ILOH QXPEHU DV DQ ILOH EHWZHHQ DQG
RWKHU WKDQ WKH GHIDXOW

RX PXVW ILUVW GHOHWH WKH
HQWLUH GHIDXOW ILOH IRU WKDW QXPEHU DQG WKHQ FUHDWH WKH
WLPHU ILOH )RU H[DPSOH LI RX ZDQW D WLPHU ILOH QXPEHU
DV ILOH RX PXVW ILUVW GHOHWH WKH HQWLUH GHIDXOW ELQDU
ILOH DQG WKHQ FUHDWH WKH WLPHU ILOH DV ILOH

7R DFFHVV D WLPHU VWDWXV ELW SUHVHW RU DFFXPXODWHG YDOXH VWRUHG DW WKH
WLPHU FRQWURO DGGUHVV XVH WKH IROORZLQJ DGGUHVV IRUPDW

Status Bit Preset Accumulated Value

Tf:s.sb Tf:s.PRE Tf:s.ACC

7KH VE VSHFLILHV D VWDWXV ELW PQHPRQLF VXFK DV '1
,PSRUWDQW 7KH SURFHVVRU VWRUHV WLPHU VWDWXV ELWV DQG WKH SUHVHW DQG
DFFXPXODWHG YDOXHV LQ D ELW VWRUDJH VWUXFWXUH WKUHH
ELW ZRUGV

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
T4:0
EN TT DN internal use only Control word
for T4:0
preset value (16 bits)

accumulated value (16 bits)

T4:1 EN TT DN internal use only Control word
for T4:1
preset value (16 bits)

T4:2 .
.
.

1785-6.1 November 1998

Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES 2-3

‡ 7LPH %DVH GHWHUPLQHV KRZ WKH WLPHU RSHUDWHV 7DEOH % OLVWV WKH
SRVVLEOH WLPH EDVHV
Table 1.B
Available Time Base Values

Enter This Time Base: The Accumulated Value Range Is:

1 second to 32,767 time-base intervals (to 9.1hours)

0.01 seconds (10ms) to 32,767 time-base intervals (to 5.5
minutes)

‡ 3UHVHW VSHFLILHV WKH YDOXH ZKLFK WKH WLPHU PXVW UHDFK EHIRUH WKH
SURFHVVRU VHWV WKH GRQH ELW '1

RX PXVW HQWHU D SUHVHW YDOXH
IURP 7KH SURFHVVRU VWRUHV WKH SUHVHW YDOXH DV D ELW
LQWHJHU YDOXH
,PSRUWDQW 7KH 3UHVHW YDOXH RSHUDWHV GLIIHUHQWO LI RX DUH XVLQJ D
72) LQVWUXFWLRQ 6HH SDJH IRU PRUH LQIRUPDWLRQ

‡ $FFXPXODWHG 9DOXH LV WKH QXPEHU RI WLPH LQFUHPHQWV WKH
LQVWUXFWLRQ KDV FRXQWHG :KHQ HQDEOHG WKH WLPHU XSGDWHV WKLV
YDOXH FRQWLQXDOO 7SLFDOO HQWHU ]HUR ZKHQ SURJUDPPLQJ WKH
LQVWUXFWLRQ ,I RX HQWHU D YDOXH WKH LQVWUXFWLRQ VWDUWV FRXQWLQJ
WLPH EDVH LQWHUYDOV IURP WKDW YDOXH ,I WKH WLPHU LV UHVHW WKH
DFFXPXODWHG YDOXH LV ]HUR 7KH UDQJH IRU WKH DFFXPXODWHG YDOXH LV
7KH SURFHVVRU VWRUHV WKH DFFXPXODWHG YDOXH DV D ELW
LQWHJHU
,PSRUWDQW 7KH $FFXPXODWHG YDOXH RSHUDWHV GLIIHUHQWO LI RX DUH
XVLQJ D 72) LQVWUXFWLRQ 6HH SDJH IRU PRUH
LQIRUPDWLRQ

Timer Accuracy 7LPHU DFFXUDF UHIHUV WR WKH OHQJWK RI WLPH EHWZHHQ WKH PRPHQW WKH
SURFHVVRU HQDEOHV D WLPHU LQVWUXFWLRQ DQG WKH PRPHQW WKH SURFHVVRU
FRPSOHWHV WKH WLPHG LQWHUYDO 7LPHU DFFXUDF GHSHQGV RQ WKH
SURFHVVRU FORFN WROHUDQFH DQG WKH WLPH EDVH 7KH FORFN WROHUDQFH LV
± 7KLV PHDQV WKDW D WLPHU FRXOG WLPH RXW HDUO RU ODWH E
VHFRQGV PV

IRU D VHFRQG WLPH EDVH RU VHFRQG IRU D VHFRQG
WLPH EDVH
7KH VHFRQG WLPHU PDLQWDLQV DFFXUDF ZLWK D SURJUDP VFDQ RI XS
WR VHFRQGV WKH VHFRQG WLPHU PDLQWDLQV DFFXUDF ZLWK D SURJUDP
VFDQ RI XS WR VHFRQGV ,I RXU SURJUDPV FDQ H[FHHG RU
VHFRQGV UHSHDW WKH WLPHU LQVWUXFWLRQ UXQJ VR WKDW WKH UXQJ LV VFDQQHG
ZLWKLQ WKHVH OLPLWV
7KH GLVSODHG DFFXPXODWHG YDOXH RI D WLPHU VKRZV DFWXDO WLPH EXW LV
GHSHQGHQW RQ 57 XSGDWH WLPH 7KH DFFXPXODWHG YDOXH PLJKW DSSHDU
WR EH OHVV WKDQ WKH SUHVHW ZKHQ WKH GRQH ELW LV VHW

1785-6.1 November 1998


Timer On Delay (TON)

Description: 8VH WKH 721 LQVWUXFWLRQ WR WXUQ DQ RXWSXW RQ RU RII DIWHU WKH WLPHU KDV
EHHQ RQ IRU D SUHVHW WLPH LQWHUYDO 7KH 721 LQVWUXFWLRQ VWDUWV
TON
TIMER ON DELAY EN
DFFXPXODWLQJ WLPH ZKHQ WKH UXQJ JRHV WUXH DQG FRQWLQXHV XQWLO RQH
Timer RI WKH IROORZLQJ KDSSHQV
Time base DN
Preset
‡ WKH DFFXPXODWHG YDOXH HTXDOV LWV SUHVHW YDOXH
Accum ‡ WKH UXQJ JRHV IDOVH
‡ D UHVHW LQVWUXFWLRQ UHVHWV WKH WLPHU
‡ WKH 6) VWHS JRHV LQDFWLYH
‡ WKH SURFHVVRU UHVHWV WKH DFFXPXODWHG YDOXH ZKHQ WKH UXQJ
FRQGLWLRQV JR IDOVH UHJDUGOHVV RI ZKHWKHU WKH WLPHU WLPHG
RXW RU QRW

Using Status Bits
([DPLQH VWDWXV ELWV LQ WKH ODGGHU SURJUDP WR WULJJHU VRPH HYHQW 7KH
SURFHVVRU FKDQJHV WKH VWDWHV RI VWDWXV ELWV ZKHQ WKH SURFHVVRU UXQV
WKLV LQVWUXFWLRQ RX DGGUHVV VWDWXV ELWV E PQHPRQLF

This Bit: Is Set When: Indicates: And Remains Set Until One of the
Following Occurs:

Timer Enable.EN (bit 15) the rung goes true that the timer is enabled • the rung goes false
• a reset instruction resets the timer
• the SFC step goes inactive

Timer Timing Bit .TT (bit 14) the rung goes true that a timing operation is • the rung goes false
in progress • the .DN bit is set (.ACC = .PRE)
• the associated SFC step goes inactive

Timer Done Bit .DN (bit 13) the accumulated value is that a timing operation • the rung goes false
equal to the preset value is complete • a reset instruction resets the timer

1785-6.1 November 1998


,I RX VHW WKH GRQH ELW '1 XVLQJ DQ 27( LQVWUXFWLRQ IRU H[DPSOH
RX FDQ SDXVH WKH WLPHU 7KH (1 DQG 77 ELWV UHPDLQ VHW EXW WKH
DFFXPXODWHG YDOXH GRHV QRW LQFUHPHQW 7LPLQJ UHVXPHV ZKHQ RX
FOHDU WKH '1 ELW ,I WKH UXQJ JRHV IDOVH ZKLOH WKH WLPHU LV SDXVHG WKH
WLPHU UHVHWV DV QRUPDO
,I RX FKDQJH WR 3URJUDP PRGH RU WKH SURFHVVRU ORVHV SRZHU
EHIRUH WKH LQVWUXFWLRQ UHDFKHV WKH SUHVHW YDOXH WKH IROORZLQJ
RFFXUV
‡ WLPHU HQDEOH (1

ELW UHPDLQV VHW
‡ WLPHU WLPLQJ 77

ELW UHPDLQV VHW
‡ DFFXPXODWHG $

YDOXH UHPDLQV WKH VDPH
7KHQ ZKHQ RX VZLWFK EDFN WR 5XQ PRGH RU 7HVW PRGH RU SRZHU
LV UHVWRUHG WKH IROORZLQJ KDSSHQV

Condition: Result:

If the rung is true: .EN bit remains set
.TT bit remains set
.DN bit remains reset
.ACC value is reset and starts counting up

If the rung is false: .EN bit is reset
.TT bit is reset
.DN bit is reset
.ACC value is reset

Figure 2.1
Example TON Ladder Diagram

I:012 TON
TIMER ON DELAY EN
10 When the input condition is true, the Timer T4:0
processor increments the accumulated value
of T4:0 in 1-second increments. Time base 1.0 DN
Preset 180
Accum 0

T4:0 Sets the output while the timer is timing O:013

TT 01

T4:0 Sets the output when the timer is done timing O:013

DN 02

When bit I:012/10 is set, the processor starts T4:0. The accumulated value increments in 1-second intervals.
T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE) T4:0.TT is reset (so O:013/01 and the associated output device is
de-energized) and T4:0.DN is set (so O:013/02 is set and the associated output device is energized). When the
accumulated value reaches 180, the .DN bit is set. Or if the rung goes false, the timer is reset.

1785-6.1 November 1998


Figure 2.2
Example TON Timing Diagram
ON
Rung Condition OFF

ON
Timer Enable Bit
OFF

ON
Timer Timing Bit OFF

ON
Timer Done Bit
OFF

Output Device ON
(Controlled by Done Bit) OFF

3 minutes ON
Delay
Timer Accumulated Value 2 minutes
(Accumulator)

180
120
0
Timer Preset = 180 16649

1785-6.1 November 1998


Timer Off Delay (TOF)

Description: 8VH WKH 72) LQVWUXFWLRQ WR WXUQ DQ RXWSXW RQ RU RII DIWHU LWV UXQJ KDV
EHHQ RII IRU D SUHVHW WLPH LQWHUYDO 7KH 72) LQVWUXFWLRQ VWDUWV
TOF
DFFXPXODWLQJ WLPH ZKHQ WKH UXQJ JRHV IDOVH DQG FRQWLQXHV WLPLQJ
TIMER OFF DELAY
Timer
EN
XQWLO RQH RI WKH IROORZLQJ FRQGLWLRQV RFFXU
Time base DN
‡ WKH DFFXPXODWHG YDOXH HTXDOV LWV SUHVHW YDOXH
Preset
Accum ‡ WKH UXQJ JRHV WUXH
‡ D UHVHW LQVWUXFWLRQ UHVHWV WKH WLPHU
7KH SURFHVVRU UHVHWV WKH DFFXPXODWHG YDOXH ZKHQ WKH UXQJ FRQGLWLRQV
JR WUXH UHJDUGOHVV RI ZKHWKHU WKH WLPHU WLPHG RXW RU QRW

Using Status Bits
WKLV LQVWUXFWLRQ RX DGGUHVV WKH VWDWXV ELWV E PQHPRQLF

This Bit: Is Set When: And Remains Set Until One of the
Following Occurs:

Timer Enable .EN (bit 15) the rung goes true • the rung goes false
• the SFC step goes inactive

Timer Timing Bit .TT (bit 14) the rung goes false and the • the rung goes true
accumulated value is less than • the .DN bit is set (.ACC = .PRE)
the preset • a reset instruction resets the timer

Timer Done Bit .DN (bit 13) the rung goes true • the accumulated value is equal to the
preset value

1785-6.1 November 1998


,I RX FKDQJH WR 3URJUDP PRGH RU WKH SURFHVVRU ORVHV SRZHU RU
WKH SURFHVVRU IDXOW LQWHUUXSWV WKH 72) LQVWUXFWLRQ EHIRUH LW
UHDFKHV WKH SUHVHW YDOXH WKH IROORZLQJ RFFXUV
‡ WLPHU HQDEOH (1

ELW UHPDLQV UHVHW
‡ WLPHU WLPLQJ 77

ELW UHPDLQV VHW
‡ WLPHU GRQH '1

7KHQ LI RX VZLWFK WR 5XQ PRGH RU 7HVW PRGH WKH IROORZLQJ
KDSSHQV

Condition: Result:

If the rung is true: .EN bit is set
.TT bit is reset
.DN bit remains set
.ACC value is cleared

.TT bit is reset
.DN bit is reset
.ACC value equals PRE value
(the timer does not start timing)

$77(17,21 %HFDXVH WKH 5(6 LQVWUXFWLRQ UHVHWV WKH
DFFXPXODWHG YDOXH GRQH ELW DQG WLPLQJ ELWV RI D WLPLQJ
LQVWUXFWLRQ GR QRW XVH WKH 5(6 LQVWUXFWLRQ WR UHVHW D 72)
WLPHU

'XULQJ SUHVFDQ WKH IROORZLQJ KDSSHQV
‡ WLPHU WLPLQJ 77

ELW LV FOHDUHG
‡ DFFXPXODWHG $

YDOXH LV HTXDO WR WKH SUHVHW YDOXH

1785-6.1 November 1998


Figure 2.3
Example TOF Ladder Diagram

I:012 TOF
TIMER OFF DELAY EN
10 Timer T4:0
When the input goes false, the processor starts
incrementing the accumulated value in T4:0 in Time base 1.0 DN
1-second increments until the input goes true.
Preset 180
Accum 0

T4:0 Sets the output while the timer is timing O:013

TT 01

T4:0 Resets the output when the timer is done timing O:013

DN 02

When bit I:012/10 is reset, the processor starts timer T4:0. The accumulated value increments by 1-second intervals as long as the
rung remains false. T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE), T4:0.TT is reset (so O:013/01 is reset and the associated output device is de-energized)
and T4:0.DN is reset (so O:013/02 is reset and the associated output device is de-energized). When the accumulated value reaches
180 or when the rung conditions go true, the timer stops.
Figure 2.4
Example TOF Timing Diagram
ON
Rung Condition OFF

ON
Timer Enable Bit
OFF
ON
Timer Timing Bit
OFF

ON
Timer Done Bit
OFF

Output Device ON
(Controlled by Done Bit)
OFF
OFF Delay
2 minutes 3 minutes

Time 180

120

Timer Accumulated Value
(Accumulator) 0

1785-6.1 November 1998


Retentive Timer On (RTO)

Description: 8VH WKH 572 LQVWUXFWLRQ WR WXUQ DQ RXWSXW RQ RU RII DIWHU LWV WLPHU KDV
EHHQ RQ IRU D SUHVHW WLPH LQWHUYDO 7KH 572 LQVWUXFWLRQ OHWV WKH WLPHU
RTO
RETENTIVE TIMER ON
VWRS DQG VWDUW ZLWKRXW UHVHWWLQJ WKH DFFXPXODWHG YDOXH
EN
Timer
7KH 572 LQVWUXFWLRQ EHJLQV WLPLQJ ZKHQ LWV UXQJ JRHV WUXH $V ORQJ
Time base DN
DV WKH UXQJ UHPDLQV WUXH WKH WLPHU XSGDWHV WKH DFFXPXODWHG YDOXH
Preset
Accum
HDFK SURJUDP VFDQ XQWLO LW UHDFKHV WKH SUHVHW YDOXH 7KH 572
LQVWUXFWLRQ UHWDLQV LWV DFFXPXODWHG YDOXH HYHQ LI RQH RI WKH IROORZLQJ
RFFXUV
‡ WKH UXQJ JRHV IDOVH
‡ RX FKDQJH WR 3URJUDP PRGH
‡ WKH SURFHVVRU IDXOWV RU ORVHV SRZHU
:KHQ WKH SURFHVVRU UHVXPHV RSHUDWLRQ RU WKH UXQJ JRHV WUXH WLPLQJ
FRQWLQXHV IURP WKH UHWDLQHG DFFXPXODWHG YDOXH % UHWDLQLQJ LWV
DFFXPXODWHG YDOXH UHWHQWLYH WLPHUV PHDVXUH WKH FXPXODWLYH SHULRG
GXULQJ ZKLFK LWV UXQJ LV WUXH
,PSRUWDQW 7R UHVHW WKH UHWHQWLYH WLPHU¶V DFFXPXODWHG YDOXH DQG
VWDWXV ELWV DIWHU WKH 572 UXQJ JRHV IDOVH RX PXVW
SURJUDP D UHVHW LQVWUXFWLRQ 5(6 ZLWK WKH VDPH DGGUHVV
LQ DQRWKHU UXQJ

Using Status Bits

This Bit: Is Set When: Indicates: And Remains Set Until One of the
Following Occurs:

Timer Enable Bit .EN (bit 15) the rung goes true that a timing operation is • the rung goes false
in progress • a reset instruction resets the timer

Timer Timing Bit .TT (bit 14) the rung goes true that a timing operation is • the rung goes false
in progress • the .DN bit is set
• the accumulated value is equal to
the preset value (.ACC=.PRE)

Timer Done Bit .DN (bit 13) the accumulated value is that a timing operation • the .DN bit is reset with the
equal to the preset value is complete RES instruction.

1785-6.1 November 1998


,I RX FKDQJH WR 3URJUDP PRGH RU WKH SURFHVVRU ORVHV SRZHU RU
D SURFHVVRU IDXOW LQWHUUXSWV WKH 572 LQVWUXFWLRQ WKH IROORZLQJ
RFFXUV
‡ WLPHU HQDEOH (1

:KHQ RX VZLWFK EDFN WR 5XQ PRGH RU 7HVW PRGH WKH IROORZLQJ
KDSSHQV

Condition: Result:

If the rung is true: .EN bit remains set
.TT bit remains set
.ACC value continues timing

.TT bit is reset
.DN bit remains the same
.ACC value remains the same

Figure 2.5
Example RTO Ladder Diagram

I:012 RTO
RETENTIVE TIMER ON EN
10 Timer T4:10
When the input is true, the processor starts incrementing
the accumulated value of T4:10 in 1-second increments. Time base 1.0 DN
The timer values remain when the input goes false. Preset 180
Accum 0

I:017 Resets the timer T4:10
RES
12

1785-6.1 November 1998


Figure 2.6
Retentive Timer Timing Diagram
ON
Rung Condition OFF

ON
Timer Enable Bit
OFF
ON
Reset Pulse
OFF

ON
Timer Timing Bit
OFF

ON
Timer Done Bit
OFF

ON

Output Device OFF
(Controlled by Done Bit)
180
120
100
Timer Accumulated Value
(Accumulator) 40
0

1785-6.1 November 1998


Using Counters %HIRUH XVLQJ FRXQWHU LQVWUXFWLRQV RX QHHG WR XQGHUVWDQG WKH
CTU
SDUDPHWHUV WKDW RX HQWHU
COUNT UP CU
Counter Entering Parameters
Preset DN
Accum 7R SURJUDP D FRXQWHU LQVWUXFWLRQ SURYLGH WKH SURFHVVRU ZLWK WKH IROORZLQJ
LQIRUPDWLRQ
‡ RXQWHU LV WKH FRXQWHU FRQWURO DGGUHVV LQ WKH FRXQWHU

DUHD RI
GDWD VWRUDJH 8VH WKH IROORZLQJ DGGUHVV IRUPDW
C f : s

counter structure number (0-999)

counter file number (3-999)
counter (file type)

,PSRUWDQW RX FDQ XVH DQ FRXQWHU ILOH QXPEHU IURP WR
KRZHYHU WKH GHIDXOW FRXQWHU ILOH QXPEHU LV ,I RX
ZDQW WR VSHFLI D FRXQWHU ILOH QXPEHU DV DQ ILOH
EHWZHHQ DQG RWKHU WKDQ WKH GHIDXOW

RX PXVW
ILUVW GHOHWH WKH HQWLUH GHIDXOW ILOH IRU WKDW QXPEHU DQG
WKHQ FUHDWH WKH FRXQWHU ILOH )RU H[DPSOH LI RX ZDQW D
FRXQWHU ILOH QXPEHU DV ILOH RX PXVW ILUVW GHOHWH WKH
HQWLUH GHIDXOW ELQDU ILOH DQG WKHQ FUHDWH WKH FRXQWHU ILOH
DV ILOH

7R DFFHVV D FRXQWHU VWDWXV ELW SUHVHW YDOXH RU DFFXPXODWHG YDOXH XVH
WKH IROORZLQJ DGGUHVV IRUPDW

Status Bit Preset Accumulated Value

Cf:s.bb Cf:s.PRE Cf:s.ACC

7KH EE LV D VWDWXV ELW PQHPRQLF VXFK DV '1
,PSRUWDQW 7KH SURFHVVRU VWRUHV FRXQWHU VWDWXV ELWV DQG WKH SUHVHW
DQG DFFXPXODWHG YDOXHV LQ D VWRUDJH VWUXFWXUH ELWV ±
WKUHH ELW ZRUGV

LQ WKH GDWD WDEOH
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
C5:0
CU CD DN OV UN internal use only Control word
preset (16 bits) for C5:0

C5:1 CU CD DN OV UN internal use only Control word
for C5:1
preset (16 bits)

C5:2 .
.
.

1785-6.1 November 1998


‡ 3UHVHW VSHFLILHV WKH YDOXH ZKLFK WKH FRXQWHU PXVW UHDFK EHIRUH LW
VHWV WKH GRQH ELW '1 (QWHU D SUHVHW YDOXH IURP ± XS WR
7KH SUHVHW YDOXH LV VWRUHG DV D ELW LQWHJHU YDOXH
1HJDWLYH YDOXHV DUH VWRUHG LQ WZRV FRPSOHPHQW IRUP
‡ $FFXPXODWHG 9DOXH LV WKH FXUUHQW FRXQW EDVHG RQ WKH QXPEHU RI
WLPHV WKH UXQJ JRHV IURP IDOVH WR WUXH 7KH DFFXPXODWHG YDOXH LV
VWRUHG DV D ELW LQWHJHU YDOXH 1HJDWLYH YDOXHV DUH VWRUHG LQ
WZRV FRPSOHPHQW IRUP 7KH UDQJH RI WKH DFFXPXODWHG YDOXH LV ±
WR 7SLFDOO RX HQWHU D ]HUR YDOXH ZKHQ
SURJUDPPLQJ FRXQWHU LQVWUXFWLRQV ,I RX HQWHU D QRQ]HUR YDOXH
WKH LQVWUXFWLRQ VWDUWV FRXQWLQJ IURP WKDW YDOXH ,I WKH FRXQWHU LV
UHVHW WKH DFFXPXODWHG YDOXH LV VHW WR ]HUR

1785-6.1 November 1998


Count Up (CTU)

Description: 7KH 78 LQVWUXFWLRQ FRXQWV XSZDUG RYHU D UDQJH RI ± WR
CTU
(DFK WLPH WKH UXQJ JRHV IURP IDOVH WR WUXH WKH 78
COUNT UP CU LQVWUXFWLRQ LQFUHPHQWV WKH DFFXPXODWHG YDOXH E RQH FRXQW :KHQ
Counter WKH DFFXPXODWHG YDOXH HTXDOV RU H[FHHGV WKH SUHVHW YDOXH WKH
Preset DN 78 LQVWUXFWLRQ VHWV D GRQH ELW '1 ZKLFK RXU ODGGHU SURJUDP FDQ
Accum
XVH WR LQLWLDWH VRPH DFWLRQ VXFK DV FRQWUROOLQJ D VWRUDJH ELW RU DQ
RXWSXW GHYLFH
7KH DFFXPXODWHG YDOXH RI D FRXQWHU LV UHWHQWLYH 7KH FRXQW LV UHWDLQHG
XQWLO UHVHW E D UHVHW LQVWUXFWLRQ 5(6

WKDW KDV WKH VDPH DGGUHVV DV
WKH FRXQWHU

Using Status Bits
SURFHVVRU FKDQJHV WKH VWDWHV RI VWDWXV ELWV ZKHQ WKH SURFHVVRU UXQV WKH
78 LQVWUXFWLRQ RX DGGUHVV WKH VWDWXV ELWV E PQHPRQLF

This Bit: Is Set: And Remains Set Until One of the Following Occurs:

Count Up when the rung goes true to indicate the • the rung goes false
Enable Bit .CU (bit 15) instruction has increased its count • a RES instruction resets the .DN bit
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.

Count Up when the accumulated value is greater than or • the accumulated value counts below the preset, either
Done Bit .DN (bit 13) equal to the preset value by using a CTD instruction to count down or changing
the accumulated value
• a RES instruction resets the .DN bit

Count Up when the up counter has exceeded the upper • a RES instruction resets the .DN bit
Overflow Bit .OV (bit 12) limit of +32,767 and has wrapped around to – • counting back down to 32,767 with a CTD instruction
32,768. The CTU counts up from there. with the same address

$77(17,21 3ODFH FULWLFDO FRXQWHUV RXWVLGH DQ 05
]RQH RU MXPSHG VHFWLRQV RI ODGGHU SURJUDP WR JXDUG
DJDLQVW LQYDOLG UHVXOWV WKDW FRXOG OHDG WR GDPDJHG
HTXLSPHQW RU SHUVRQQHO LQMXU

1785-6.1 November 1998


Figure 2.7
Example CTU Ladder Diagram
I:012 CTU
COUNT UP CU
10 Each time the input goes false to true, Counter C5:0
the processor increments the counter
by 1. Preset 4 DN
Accum 0

C5:0 Tells when the count is reached (ACC or = PRE) O:020

01
DN
C5:0 Tells when the counter overflows +32,767 O:021

02
OV
I:017 Reset the counter C5:0
RES
12

Figure 2.8
Example CTU Timing Diagram
Counter preset = 4 counts

Rung condition that ON
controls counter OFF

ON
Count-up enable bit
OFF

Rung condition that ON
controls reset instruction
OFF

ON
Done Bit
OFF

Output instruction on rung ON
controlled by counter
OFF
4
3
2
1 0

Counter Accumulated Value 0 16636

1785-6.1 November 1998


Count Down (CTD)

Description: 7KH 7' LQVWUXFWLRQ FRXQWV GRZQZDUG RYHU D UDQJH RI WR
CTD
± (DFK WLPH WKH UXQJ JRHV IURP IDOVH WR WUXH WKH 7'
COUNT DOWN CD
LQVWUXFWLRQ GHFUHPHQWV WKH DFFXPXODWHG YDOXH E RQH FRXQW 7KH
Counter GRQH ELW '1 LV VHW DV ORQJ DV WKH DFFXPXODWHG YDOXH LV JUHDWHU WKDQ RU
Preset DN HTXDO WR WKH SUHVHW YDOXH :KHQ WKH DFFXPXODWHG YDOXH LV OHVV WKDQ WKH
Accum SUHVHW YDOXH WKH GRQH ELW '1 LV UHVHW ZKLFK RXU ODGGHU SURJUDP FDQ
XVH WR LQLWLDWH VRPH DFWLRQ VXFK DV FRQWUROOLQJ D VWRUDJH ELW RU DQ
RXWSXW GHYLFH
7KH DFFXPXODWHG YDOXH RI D FRXQWHU LV UHWHQWLYH 7KH FRXQW LV UHWDLQHG
XQWLO UHVHW E D UHVHW LQVWUXFWLRQ 5(6

WKDW KDV WKH VDPH DGGUHVV DV
WKH 7' LQVWUXFWLRQ

Using Status Bits

This Bit: Is Set: And Remains Set Until One of the Following Occurs:

Count Down when the rung goes true to indicate that the • the rung goes false
Enable Bit .CD (bit 14) counter is enabled as a down-counter. • a RES instruction resets the .DN bit
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.

Count Down when the accumulated value is greater than or • the accumulated value counts below the preset
Done Bit .DN (bit 13) equal to the preset value. • another instruction changes the accumulated value
• a RES instruction resets the .DN bit

Count Down by the processor to show that the down • a RES instruction resets the .DN bit
Underflow Bit (.UN) (Bit 11) counter went below the lower limit of –32,768 • count back up to -32,768 with a CTU instruction
and has wrapped around to +32,767. The CTD
instruction counts down from there.

$77(17,21 3ODFH FULWLFDO FRXQWHUV RXWVLGH DQ 05
]RQH RU MXPSHG VHFWLRQV RI ODGGHU SURJUDP WR JXDUG
DJDLQVW LQYDOLG UHVXOWV WKDW FRXOG OHDG WR GDPDJHG
HTXLSPHQW RU SHUVRQQHO LQMXU

1785-6.1 November 1998


Figure 2.9
Example CTD Ladder Diagram

I:012 CTD
COUNT DOWN CD
10 Each time the input goes from false to true, Counter C5:0
the processor decrements the counter by 1.
Preset 4 DN
Accum 8


DN 01
C5:0 Tells when the counter underflows -32,768 O:021

UN 02

I:017 Resets the counter C5:0
RES
12
Figure 2.10
Example CTD Timing Diagram
Counter preset = 4 counts
Counter accumulated = 8
ON
Rung condition that
controls counter OFF

Count-up enable bit

Rung condition that
controls reset instruction

Done Bit

Output instruction on rung
controlled by counter

8
7
Counter Accumulated Value 6
5
4
3

0
16637

1785-6.1 November 1998


Figure 2.11
Example CTU and CTD Logic Diagram
I:012 CTU
Count up pushbutton
COUNT UP CU
10 Counter C5:0
Preset 4 DN
Accum 0

I:012 CTD
Count down pushbutton
COUNT DOWN CD
11 Counter C5:0
Preset 4
DN
Accum 0


DN 01
C5:0 Tells when the counter overflows +32,767 O:013

OV 02
C5:0 Tells when the counter underflows -32,768 O:013

UN 03
RES
12
Figure 2.12
Example CTU and CTD Timing Diagram
ON
Count Up Pushbutton
OFF

ON
Count Down Pushbutton OFF

ON
Reset Pulse
OFF

ON
Done Bit
OFF

5
4 4
3 3 3
2 2 2
1 1 1
0 0
Counter Accumulated Value
Count Up Preset = 4
Count Down Preset = 4 16652

1785-6.1 November 1998


Timer and Counter Reset (RES)

Description: 7KH 5(6 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW UHVHWV D WLPHU RU
FRXQWHU 7KH 5(6 LQVWUXFWLRQ H[HFXWHV ZKHQ LWV UXQJ LV WUXH
RES
When Using a RES Instruction for a: The Processor Resets the:

Timer .ACC value
(Do not use a RES instruction for a TOF.) .EN bit
.TT bit
.DN bit

Counter .ACC value
.EN bit
.OV or .UN bit
.DN bit

,I WKH FRXQWHU UXQJ LV HQDEOHG WKH 8 RU ' ELW ZLOO EH UHVHW DV ORQJ
DV WKH 5(6 LQVWUXFWLRQ LV HQDEOHG
,PSRUWDQW RX FDQ XVH D QHJDWLYH SUHVHW YDOXH LQ D 78 RU 7'
LQVWUXFWLRQ LI RX LQWHQG WR XVH WKH 5(6 LQVWUXFWLRQ
+RZHYHU QRWH WKDW WKH 5(6 LQVWUXFWLRQ VHWV WKH
DFFXPXODWHG YDOXH WR ]HUR ZKLFK PD VHW WKH '1 ELW
DQG SUHYHQW WKH 78 RU 7' LQVWUXFWLRQ IURP RSHUDWLQJ
WKH QH[W WLPH LW LV HQDEOHG

$77(17,21 %HFDXVH WKH 5(6 LQVWUXFWLRQ UHVHWV WKH
DFFXPXODWHG YDOXH '1 ELW DQG 77 ELW RI D WLPLQJ
LQVWUXFWLRQ GR QRW XVH WKH 5(6 LQVWUXFWLRQ WR UHVHW D 72)
LQVWUXFWLRQ XQSUHGLFWDEOH PDFKLQH RSHUDWLRQ RU LQMXU
WR SHUVRQQHO PD RFFXU

Figure 2.13
Example RES Ladder Diagram

I:012 CTD
COUNT DOWN CD
10 Each time the input goes from false to true, the Counter C5:0
processor decrements the counter by 1.
Preset 4 DN
Accum 8


DN 01

RES
12

1785-6.1 November 1998

Chapter 3
Compare Instructions CMP, EQU, GEQ,
GRT, LEQ, LES, LIM, MEQ, NEQ
Using Compare Instructions 7KH FRPSDULVRQ LQVWUXFWLRQV OHW RX FRPSDUH YDOXHV XVLQJ DQ
H[SUHVVLRQ RU D VSHFLILF FRPSDULVRQ LQVWUXFWLRQ 7DEOH $ OLVWV WKH
DYDLODEOH FRPSDUH LQVWUXFWLRQV
Table 3.A
Available Compare Instructions

Use the On
If You Want to:
Instruction: Page:

Compare values based on an expression CMP 3-2

Test whether two values are equal EQU 3-5

Test whether one value is greater than or equal to a GEQ 3-5
second value

Test whether one value is greater than a second value GRT 3-6

Test whether one value is less than or equal to a LEQ 3-6
second value

Test whether one value is less than a second value LES 3-7

Test whether one value is between two other values LIM 3-7

Pass two values through a mask and test whether MEQ 3-9
they are equal

Test whether one value is not equal to a second value NEQ 3-10

,PSRUWDQW RX FDQ FRPSDUH YDOXHV RI GLIIHUHQW GDWD WSHV VXFK DV
IORDWLQJ SRLQW DQG LQWHJHU RX VKRXOG XVH %' DQG
$6,, YDOXHV IRU GLVSOD SXUSRVHV ,I RX HQWHU %' RU
$6,, YDOXHV WKH SURFHVVRU WUHDWV WKRVH YDOXHV DV
LQWHJHUV )RU H[DPSOH LI WKH YDOXH DW 1 LV
GHFLPDO

WKH
FRPSDULVRQ RI 1 ' HYDOXDWHV DV IDOVH 7KH LQ
%' WUDQVODWHV WR WKH LQ
GHFLPDO WUDQVODWHV WR

7KH SDUDPHWHUV RX HQWHU DUH SURJUDP FRQVWDQWV RU ORJLFDO DGGUHVVHV
RI WKH YDOXHV RX ZDQW WR FRPSDUH
HDFK RSHUDQG

$SSHQGL[

1785-6.1 November 1998

3-2 Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ

Using Arithmetic Status Flags 7KH DULWKPHWLF VWDWXV IODJV DUH LQ ZRUG ELWV LQ WKH SURFHVVRU
VWDWXV ILOH 6

0RQLWRU WKHVH ELWV LI RX SHUIRUP DQ DULWKPHWLF
IXQFWLRQ ZLWKLQ WKH 03 LQVWUXFWLRQ 7DEOH % OLVWV WKH VWDWXV ELWV
Table 3.B
Arithmetic Status Bits

This Bit: Description:

S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)

Compare (CMP) 7KH 03 LQVWUXFWLRQ FRPSDUHV YDOXHV DQG SHUIRUPV ORJLFDO
FRPSDULVRQV

Description: 7KH 03 LQVWUXFWLRQ LV DQ LQSXW LQVWUXFWLRQ WKDW SHUIRUPV D
CMP FRPSDULVRQ RQ DULWKPHWLF RSHUDWLRQV RX VSHFLI LQ WKH H[SUHVVLRQ
COMPARE :KHQ WKH SURFHVVRU ILQGV WKH H[SUHVVLRQ LV WUXH WKH UXQJ JRHV WUXH
Expression 2WKHUZLVH WKH UXQJ LV IDOVH :LWK (QKDQFHG 3/ SURFHVVRUV RX
FDQ HQWHU PXOWLSOH RSHUDQGV FRPSOH[ H[SUHVVLRQ

7KH H[HFXWLRQ WLPH RI D 03 LQVWUXFWLRQ LV ORQJHU WKDQ WKH H[HFXWLRQ
WLPH RI RQH RI WKH RWKHU FRPSDULVRQ LQVWUXFWLRQV HJ *57 /(4
HWF

$ 03 LQVWUXFWLRQ DOVR XVHV PRUH ZRUGV LQ RXU SURJUDP ILOH
WKDQ WKH FRUUHVSRQGLQJ FRPSDULVRQ LQVWUXFWLRQ

Entering the CMP Expression
7KH H[SUHVVLRQ GHILQHV WKH RSHUDWLRQV RX ZDQW WR SHUIRUP 'HILQH
WKH H[SUHVVLRQ ZLWK RSHUDWRUV DQG DGGUHVVHV RU SURJUDP FRQVWDQWV
:LWK (QKDQFHG 3/ SURFHVVRUV RX FDQ HQWHU FRPSOH[
H[SUHVVLRQV 7DEOH OLVWV YDOLG RSHUDWLRQV IRU DQ H[SUHVVLRQ WKH
IROORZLQJ OLVW SURYLGHV JXLGHOLQHV IRU ZULWLQJ H[SUHVVLRQV
‡ 2SHUDWRUV VPEROV

GHILQH WKH RSHUDWLRQV
‡ $GGUHVVHV FDQ EH GLUHFW LQGLUHFW RU LQGH[HG DGGUHVVHV

‡ :LWK (QKDQFHG 3/ SURFHVVRUV SURJUDP FRQVWDQWV FDQ EH
LQWHJHU RU IORDWLQJSRLQW QXPEHUV LI RX HQWHU RFWDO YDOXHV XVH D
OHDGLQJ 2 LI RX HQWHU KH[DGHFLPDO YDOXHV XVH D OHDGLQJ +
LI RX HQWHU ELQDU YDOXHV XVH D OHDGLQJ %

Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ 3-3

Table 3.C
Valid Operations for Use in a CMP Expression

Type Operator Description Example Operation

Comparison = equal to if A = B, then ...

not equal to if A B, then ...

less than if A B, then ...

= less than or equal to if A = B, then ...

greater than if A B, then ...

= greater than or equal to if A = B, then ...

Arithmetic + add 2 + 3 Enhanced PLC-5 processor:
2+3+7

– subtract 12 – 5

* multiply 5 * 2 PLC-5/30, -5/40, -5/60,
-5/80: 6 * (5 * 2)

| (vertical bar) divide 24 | 6

– negate – N7:0

SQR square root SQR N7:0

** exponential 10**3
(x to the power of y) (Enhanced PLC-5 processors only)

Conversion FRD convert from BCD FRD N7:0
to binary

TOD convert from binary TOD N7:0
to BCD

Determining the Length of an Expression
(QKDQFHG 3/ SURFHVVRUV VXSSRUW FRPSOH[ LQVWUXFWLRQV XS WR D
WRWDO RI FKDUDFWHUV LQFOXGLQJ VSDFHV DQG SDUHQWKHVHV

'HSHQGLQJ
RQ WKH RSHUDWRU WKH SURFHVVRU LQVHUWV FKDUDFWHUV EHIRUHDIWHU WKH
RSHUDWRU LQ RXU H[SUHVVLRQ WR IRUPDW WKH H[SUHVVLRQ IRU HDVLHU
LQWHUSUHWDWLRQ 8VH 7DEOH ' WR GHWHUPLQH WKH QXPEHU RI FKDUDFWHUV
HDFK RSHUDWRU XVHV LQ DQ H[SUHVVLRQ
,PSRUWDQW RX FDQQRW HQWHU IORDWLQJ SRLQW QXPEHUV LQ VFLHQWLILF
QRWDWLRQ ZLWK QHJDWLYH H[SRQHQWV LQ FRPSOH[
H[SUHVVLRQV ,QVWHDG XVH WKH GHFLPDO HTXLYDOHQW RU SXW
WKH QXPEHU LQ D IORDWLQJ SRLQW ILOH DQG XVH WKH GDWD
DGGUHVV LQ WKH FRPSOH[ H[SUHVVLRQ

1785-6.1 November 1998


:LWK WKH 03 LQVWUXFWLRQ D PD[LPXP RI FKDUDFWHUV RI WKH
H[SUHVVLRQ FDQ EH GLVSODHG ,I WKH H[SUHVVLRQ RX HQWHU LV QHDU WKLV
FKDUDFWHU PD[LPXP ZKHQ RX DFFHSW WKH UXQJ FRQWDLQLQJ WKH
LQVWUXFWLRQ WKH SURFHVVRU PD H[SDQG LW EHRQG FKDUDFWHUV :KHQ
RX WU WR HGLW WKH H[SUHVVLRQ RQO WKH ILUVW FKDUDFWHUV DUH
GLVSODHG DQG WKH UXQJ LV GLVSODHG DV DQ HUURU UXQJ 7KH SURFHVVRU
GRHV FRQWDLQ WKH FRPSOHWH H[SUHVVLRQ KRZHYHU DQG WKH LQVWUXFWLRQ
UXQV SURSHUO
7R DYRLG WKLV GLVSOD SUREOHP H[SRUW WKH SURFHVVRU PHPRU ILOH DQG
PDNH RXU HGLWV LQ WKH 3 WH[W ILOH 7KHQ LPSRUW WKLV WH[W ILOH )RU
PRUH LQIRUPDWLRQ RQ LPSRUWLQJH[SRUWLQJ SURFHVVRU PHPRU ILOHV VHH
RXU SURJUDPPLQJ PDQXDO
Table 3.D
Character Lengths for Operators

Uses this Number
This Operation: Using this Operator:
of Characters:

math binary +, –, *, | 3

OR, ** 4

AND, XOR 5

math unary – (negate) 2

LN 3

FRD, TOD, DEG, RAD, SQR, NOT, LOG, SIN, 4
COS, TAN, ASN, ACS, ATN

comparative =, , 3

, =, = 4

Example:
CMP O:013
COMPARE
Expression 01

(N7:0 + N7:1) (N7:2 + N7:3)

The CMP instruction tells an Enhanced PLC-5 processor: if the sum of the values in N7:0 and N7:1 is greater than the sum of the
values in N7:2 and N7:3, set output bit O:013/01. (The total number of characters used in this expressions is 3.)

)RU PRUH LQIRUPDWLRQ RQ HQWHULQJ FRPSOH[ H[SUHVVLRQV VHH FKDSWHU

1785-6.1 November 1998


Equal to (EQU)

Description: 8VH WKH (48 LQVWUXFWLRQ WR WHVW ZKHWKHU WZR YDOXHV DUH HTXDO
6RXUFH $ DQG 6RXUFH % FDQ HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ
EQU
YDOXHV
EQUAL
Source A
Source B

Example:

EQU O:013
EQUAL
Source A N7:5 01
Source B N7:10

If the value in N7:5 is equal to the value in N7:10, set output bit O:013/01.

)ORDWLQJ SRLQW YDOXHV DUH UDUHO DEVROXWHO HTXDO ,I RX QHHG WR
GHWHUPLQH WKH HTXDOLW RI IORDWLQJ SRLQW YDOXHV XVH WKH /,0
LQVWUXFWLRQ LQVWHDG RI WKH (48

)RU LQIRUPDWLRQ RQ WKH /,0
LQVWUXFWLRQ VHH SDJH

Greater than or Equal to (GEQ)

Description: 8VH WKH *(4 LQVWUXFWLRQ WR WHVW ZKHWKHU RQH YDOXH 6RXUFH $

LV
GEQ JUHDWHU WKDQ RU HTXDO WR DQRWKHU YDOXH 6RXUFH %

6RXUFH $ DQG
GREATER THAN OR EQUAL 6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV
Source A

Source B

Example:

GEQ O:013
GREATER THAN OR EQUAL
Source A N7:5 01

Source B N7:10

If the value in N7:5 is greater than or equal to the value in N7:10, set output bit O:013/01.

1785-6.1 November 1998


Greater than (GRT)

Description: 8VH WKH *57 LQVWUXFWLRQ WR WHVW ZKHWKHU RQH YDOXH 6RXUFH $

LV
GRT
JUHDWHU WKDQ DQRWKHU YDOXH 6RXUFH %

6RXUFH $ DQG 6RXUFH % FDQ
GREATER THAN OR EQUAL
HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV
Source A

Source B

Example:

GRT O:013
GREATER THAN
Source A N7:5 01

Source B N7:10

If the value in N7:5 is greater than the value in N7:10, set output bit O:013/01.

Less than or Equal to (LEQ)

Description: 8VH WKH /(4 LQVWUXFWLRQ WR WHVW ZKHWKHU RQH YDOXH 6RXUFH $

LV OHVV
LEQ
WKDQ RU HTXDO WR DQRWKHU YDOXH 6RXUFH %

6RXUFH $ DQG 6RXUFH % FDQ
LESS THAN OR EQUAL
HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV
Source A
Source B

Example:

LEQ O:013
LESS THAN OR EQUAL
Source A N7:5 01

Source B N7:10

If the value in N7:5 is less than or equal to the value in N7:10, set output bit O:013/01.

1785-6.1 November 1998


Less than (LES)

Description: 8VH WKH /(6 LQVWUXFWLRQ WR WHVW ZKHWKHU RQH YDOXH 6RXUFH $

LV OHVV
LES WKDQ DQRWKHU YDOXH 6RXUFH %

6RXUFH $ DQG 6RXUFH % FDQ EH YDOXHV
LESS THAN RU DGGUHVVHV WKDW FRQWDLQ YDOXHV
Source A
Source B

Example:

LES O:013
LESS THAN
Source A N7:5 01

Source B N7:10

If the value in N7:5 is less than the value in N7:10, set output bit O:013/01.

Limit Test (LIM)

Description: 7KH /,0 LQVWUXFWLRQ LV DQ LQSXW LQVWUXFWLRQ WKDW WHVWV IRU YDOXHV LQVLGH
LIM RI RU RXWVLGH RI D VSHFLILHG UDQJH 7KH LQVWUXFWLRQ LV IDOVH XQWLO LW
LIMIT TEST (CIRC) GHWHFWV WKDW WKH WHVW YDOXH LV ZLWKLQ FHUWDLQ OLPLWV 7KHQ WKH LQVWUXFWLRQ
Low limit JRHV WUXH :KHQ WKH LQVWUXFWLRQ GHWHFWV WKDW WKH WHVW YDOXH JRHV RXWVLGH
Test FHUWDLQ OLPLWV LW JRHV IDOVH
High limit

RX FDQ XVH WKH /,0 LQVWUXFWLRQ WR WHVW LI DQ DQDORJ LQSXW YDOXH LV
ZLWKLQ VSHFLILHG OLPLWV

Entering Parameters
7R SURJUDP WKH /,0 LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ

Parameter: Definition:

Low Limit a constant or an address from which the instruction reads the
lower range of the specified limit range. The address contains an
integer or floating-point value.

Test Value the address that contains the integer or floating-point value you
examine to see whether the value is inside or outside the
specified limit range.

High Limit a constant or an address from which the instruction reads the
upper range of the specified limit range. The address contains an
integer or floating-point value.

1785-6.1 November 1998


LIM Example Using Integer: ‡ ,I YDOXH /RZ /LPLW ≤ YDOXH +LJK /LPLW :KHQ WKH SURFHVVRU
GHWHFWV WKDW WKH YDOXH RI % 7HVW

LV HTXDO WR RU EHWZHHQ OLPLWV WKH
LQVWUXFWLRQ LV WUXH LI YDOXH 7HVW LV RXWVLGH WKH OLPLWV WKH
LQVWUXFWLRQ LV IDOVH
false -------true------ false
from -32,768 . . . . . . . . . . . . A ................C .......... to +32,767
value B

‡ ,I YDOXH /RZ /LPLW ≥ YDOXH +LJK /LPLW :KHQ WKH SURFHVVRU
GHWHFWV WKDW WKH YDOXH RI 7HVW LV HTXDO WR RU RXWVLGH WKH OLPLWV WKH
LQVWUXFWLRQ LV WUXH LI YDOXH 7HVW LV EHWZHHQ EXW QRW HTXDO WR HLWKHU
OLPLW WKH LQVWUXFWLRQ LV IDOVH
true ------false------ true
from -32,768 . . . . . . . . . . . . C A . . . . . . . . . . . . to +32,767
value B value B

Example (when the Low Limit is less
than the High Limit):

LIM O:013
LIMIT TEST (CIRC)
Low lim N7:10 01

Test N7:15
High lim N7:20

If the value in N7:15 is greater than or equal to the value in N7:10 and less than or equal to the value in
N7:20, set output bit O:013/01.

1785-6.1 November 1998


Mask Compare Equal to (MEQ)

Description: 7KH 0(4 LQVWUXFWLRQ LV DQ LQSXW LQVWUXFWLRQ WKDW FRPSDUHV D YDOXH
MEQ IURP D VRXUFH DGGUHVV ZLWK GDWD DW D FRPSDUH DGGUHVV DQG DOORZV
MASKED EQUAL SRUWLRQV RI WKH GDWD WR EH PDVNHG ,I WKH GDWD DW WKH VRXUFH DGGUHVV
Source PDWFKHV WKH GDWD DW WKH FRPSDUH DGGUHVV ELWEELW OHVV PDVNHG ELWV

Mask WKH LQVWUXFWLRQ LV WUXH 7KH LQVWUXFWLRQ JRHV IDOVH DV VRRQ DV LW GHWHFWV D
Compare PLVPDWFK
RX FDQ XVH WKH 0(4 LQVWUXFWLRQ WR H[WUDFW IRU FRPSDULVRQ

ELW GDWD
VXFK DV VWDWXV RU FRQWURO ELWV IURP DQ HOHPHQW WKDW FRQWDLQV ELW DQG
ZRUG GDWD

Entering Parameters
7R SURJUDP WKH 0(4 LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU
ZLWK WKH IROORZLQJ


Source a program constant or data address from which the instruction reads an
image of the value. The source remains unchanged.

Mask specifies which bits to pass or block. A mask passes data when the
mask bits are set (1); a mask blocks data when the mask bits are reset
(0). The mask must be the same element size (16-bits) as the source
and compare address. In order for bits to be compared, you must set (1)
mask bits; bits in the compare address that correspond to zeros (0) in
the mask are not compared. If you want the ladder program to change
the mask value, store the mask at a data address. Otherwise, enter a
hexadecimal value for a constant mask value. If you enter a hexadecimal
value that starts with a letter (such a F800), enter the value with a
leading zero. For example, type 0F800

Compare specifies whether you want the ladder program to vary the compare
value, or a program constant for a fixed reference. Use 16-bit elements,
the same as the source.

Example: Source 01010101 01011111
Mask 11111111 11110000
Compare 01010101 0101xxxx
Result The instruction is true because
reference bits xxxx are not compared.

MEQ O:013
MASKED EQUAL
01
Source N7:5
Mask N7:6
Compare N7:10

The processor passes the value in N7:5 through the mask in N7:6. It then passes the value in N7:10 through the mask
in N7:6. If the two masked values are equal, set output bit O:013/01

1785-6.1 November 1998


Not Equal to (NEQ)

Description: 8VH WKH 1(4 LQVWUXFWLRQ WR WHVW ZKHWKHU WZR YDOXHV DUH QRW HTXDO
NEQ 6RXUFH $ DQG 6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV
NOT EQUAL
Source A
Source B

Example:

NEQ O:013
NOT EQUAL
Source A N7:5 01

Source B N7:10

If the value in N7:5 is not equal to the value in N7:10, set output bit O:013/01.

1785-6.1 November 1998

Chapter 4
Compute Instructions CPT, ACS, ADD,
ASN, ATN, AVE, CLR, COS, DIV, LN, LOG,
MUL, NEG, SIN, SRT, SQR, STD, SUB,
TAN, XPY
Using Compute Instructions 7KH FRPSXWH LQVWUXFWLRQV HYDOXDWH DULWKPHWLF RSHUDWLRQV XVLQJ DQ
H[SUHVVLRQ RU D VSHFLILF DULWKPHWLF LQVWUXFWLRQ 7DEOH $ OLVWV WKH
DYDLODEOH FRPSXWH LQVWUXFWLRQV
Table 4.A
Available Compute Instructions

Use this Found on
If You Want to:
Instruction: Page:

Evaluate an expression CPT 4-5

Take the arc cosine of a number ACS* 4-11

Add two values ADD 4-12

Take the arc sine of a number ASN* 4-13

Take the arc tangent of a number ATN* 4-14

Calculate the average for a set of values AVE* 4-15

Clear an address word (set all bits to zero) CLR 4-17

Take the cosine of a number COS* 4-18

Divide two values DIV 4-19

Take the natural log of a number LN* 4-20

Take the log of a number LOG* 4-21

* Only Enhanced PLC-5 processors support this instruction.

(Continued)

1785-6.1 November 1998

4-2 Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY

Use this Found on
If You Want to:
Instruction: Page:

Multiply two values MUL 4-22

Take the opposite sign of a value NEG 4-23

Take the sine of a number SIN* 4-24

Take the square root of a value SQR 4-25

Sort a set of values into ascending order SRT* 4-26

Calculate the standard deviation for a set of values STD* 4-28

Subtract two values SUB 4-31

Take the tangent of a number TAN* 4-32

Raise a number to a power XPY* 4-33

* Only Enhanced PLC-5 processors support this instruction.

HDFK RSHUDQG

$SSHQGL[

Using Arithmetic Status Flags 7KH DULWKPHWLF VWDWXV IODJV DUH LQ ZRUG ELWV LQ WKH SURFHVVRU
VWDWXV ILOH 6

7DEOH % OLVWV WKH VWDWXV ELWV
Table 4.B
Arithmetic Status Bits


S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)

1785-6.1 November 1998

Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY 4-3

Data Types and the RX FDQ FRPSXWH YDOXHV RI GLIIHUHQW GDWD WSHV VXFK DV IORDWLQJ SRLQW
Compute Instruction DQG LQWHJHU ,I RX XVH D IORDWLQJSRLQW DV WKH VRXUFH XVH D
IORDWLQJSRLQW DV WKH GHVWLQDWLRQ RWKHUZLVH WKH GHVWLQDWLRQ YDOXH ZLOO
EH URXQGHG
RX VKRXOG XVH %' DQG $6,, YDOXHV IRU GLVSOD SXUSRVHV ,I RX
HQWHU %' RU $6,, YDOXHV WKH SURFHVVRU WUHDWV WKRVH YDOXHV DV
LQWHJHUV
RI WKH YDOXHV RX ZDQW

If You are Using this Processor: The Processor Rounds:

Classic PLC-5 the final value of a mathematical operation before
storing the final result. The processor rounds to
the nearest whole number: The processor rounds
values of 0.5-0.9 up to the next whole number; the
processor rounds values of 0.1- 0.4 down to the
closest whole number. If this value is greater than
32,767 or less than –32,768, the overflow status
bit is set.

Enhanced PLC-5 down if the value is 0.5, up if the value is 0.5,
and to the nearest even number if the value is =
0.5. If this value is greater than 32,767 or less
than –32,768, the processor “wraps” negative
(32,767, –32,768, –32,767, –32,766, etc.). For
example, if you have an ADD instruction with a
result greater than 32,767, the overflow bit is set,
the sign bit is set, and the result is negative:
32,767 + 5 = –32,764.

,PSRUWDQW ,I RX DUH XVLQJ DQ (QKDQFHG 3/ SURFHVVRU DQG DQ
DULWKPHWLF RSHUDWLRQ JHQHUDWHV DQ RYHUIORZ WKH XSSHU
ELWV DUH ORVW EXW WKH ORZHU ELWV DUH FRUUHFW ,I RX WKHQ
SHUIRUP D ORJLFDO RSHUDWLRQ RQ WKH ORZHU ZRUG $1' RU
25

RX FDQ JHW WKH SURSHU UHVXOW $OVR XVLQJ WKH FDUU
ELW RX FDQ GR PXOWLZRUG DULWKPHWLF LH DGG WZR
ELW ZRUGV


)RU H[DPSOH LI YDOXH 1 DQG 1
YDOXH 1 DQG 1
UHVXOW 1 DQG 1
DQG RX ZDQW WR DGG YDOXH WR YDOXH RXU ODGGHU SURJUDP ZRXOG EH

I:012 ADD
]
] ADD
10 Add the lower words of value1 and value2. Source A N7:1
Source B N7:3
Dest N7:5

I:012 AND
ADD
]
] BITWISE AND
10 Capture the carry bit. S:0
Source A
Source B 1
Dest N7:4

I:012 ADD
]
] ADD
10 Add the high word of value1 to the carry bit.
Source A N7:0
Source B N7:4
Dest N7:4

I:012 ADD
]
]
ADD
10 Add the high word of value2 to this sum. Source A N7:2
Source B N7:4
Dest N7:4

Using Floating Point Data Types )RU DQ (QKDQFHG 3/ SURFHVVRU LI RX XVH IORDWLQJ SRLQW GDWD
WSHV DQG WKH UHVXOW LV WRR ODUJH RU LI LW LV XQGHILQHG LH QDWXUDO ORJ RI

WKH SURFHVVRU VHWV WKH RYHUIORZ ELW
,I WKH UHVXOW LW WRR ODUJH D !+INF! LV GLVSODHG LI WKH UHVXOW WR WRR
VPDOO D !-INF! LV GLVSODHG ,I WKH YDOXH LV QRW D QXPEHU !NAN!
LV GLVSODHG
,PSRUWDQW ,I RX DUH XVLQJ IORDWLQJ SRLQW DQG WKH QXPEHU LV JUHDWHU
WKDQ RU OHVV WKDQ ± RX PXVW XVH D
GHFLPDO SRLQW ,I RX GR QRW XVH D GHFLPDO SRLQW WKH
HUURU INVALID OPERAND DSSHDUV

:KHQ RX XVH FRPSOH[ H[SUHVVLRQV LI DQ RSHUDQG LV IORDWLQJ
SRLQW WKH HQWLUH H[SUHVVLRQ LV HYDOXDWHG DV IORDWLQJ SRLQW 6HH WKH
H[DPSOH LQ WKH ³([SUHVVLRQ ([DPSOHV´ VHFWLRQ RQ SDJH IRU
PRUH LQIRUPDWLRQ

1785-6.1 November 1998


Compute (CPT) 7KH 37 LQVWUXFWLRQ SHUIRUPV FRS DULWKPHWLF ORJLFDO DQG
FRQYHUVLRQ RSHUDWLRQV

Description: 7KH 37 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW SHUIRUPV WKH
CPT
RSHUDWLRQV RX GHILQH LQ WKH H[SUHVVLRQ DQG ZULWHV WKH UHVXOW LQWR WKH
COMPUTE
GHVWLQDWLRQ DGGUHVV 7KH 37 LQVWUXFWLRQ FDQ DOVR FRS GDWD IURP RQH
Destination
DGGUHVV WR DQRWKHU DQG DXWRPDWLFDOO FRQYHUWV WKH GDWD WSH DW WKH
VRXUFH DGGUHVV WR WKH GDWD WSH RX VSHFLI LQ WKH GHVWLQDWLRQ DGGUHVV
Expression

7KH H[HFXWLRQ WLPH RI D 37 LQVWUXFWLRQ LV ORQJHU WKDQ WKH H[HFXWLRQ
WLPH RI DQ DULWKPHWLF ORJLF RU PRYH LQVWUXFWLRQ LH $'' $1'
029 HWF

7KH 37 LQVWUXFWLRQ DOVR XVHV PRUH ZRUGV LQ RXU
SURJUDP ILOH
$IWHU HDFK 37 LQVWUXFWLRQ LV SHUIRUPHG WKH DULWKPHWLF VWDWXV ELWV LQ
WKH VWDWXV ILOH RI WKH GDWD WDEOH DUH XSGDWHG WKH VDPH DV WKH
FRUUHVSRQGLQJ DULWKPHWLF ORJLF RU PRYH LQVWUXFWLRQ )RU H[DPSOH
UHIHU WR WKH GHVFULSWLRQ RI WKH $'' LQVWUXFWLRQ WR VHH KRZ WKH VWDWXV
ELWV DUH XSGDWHG DIWHU D 37 DGG

LQVWUXFWLRQ LV H[HFXWHG

Entering the CPT Expression
7KH H[SUHVVLRQ GHILQHV WKH RSHUDWLRQV RX ZDQW WR SHUIRUP RX
GHILQH WKH H[SUHVVLRQ ZLWK RSHUDWRUV DQG DGGUHVVHV RU SURJUDP
FRQVWDQWV :LWK (QKDQFHG 3/ SURFHVVRUV RX FDQ HQWHU FRPSOH[
H[SUHVVLRQV 7DEOH OLVWV YDOLG RSHUDWLRQV IRU DQ H[SUHVVLRQ WKH
IROORZLQJ OLVW SURYLGHV JXLGHOLQHV IRU ZULWLQJ H[SUHVVLRQV
‡ 2SHUDWRUV VPEROV

GHILQH WKH RSHUDWLRQV
‡ $GGUHVVHV FDQ EH GLUHFW RU LQGLUHFW ORJLFDO DGGUHVVHV

PXVW EH
HOHPHQW RU ELW OHYHO

‡ :LWK (QKDQFHG 3/ SURFHVVRUV SURJUDP FRQVWDQWV FDQ EH
LQWHJHU RU IORDWLQJSRLQW QXPEHUV LI RX HQWHU RFWDO YDOXHV XVH D
OHDGLQJ 2 LI RX HQWHU KH[DGHFLPDO YDOXHV XVH D OHDGLQJ +

‡ ([SUHVVLRQV FDQ RQO WRWDO FKDUDFWHUV LQFOXGLQJ VSDFHV DQG
SDUHQWKHVHV

1785-6.1 November 1998


Table 4.C
Valid Operations for Use in a CPT Expression


Copy none copy from A to B enter source address in the expression enter
destination address in destination

Clear none set a value to zero 0 (enter 0 for the expression)

Arithmetic + add 2+3
2+3+7 (Enhanced PLC-5 processors)

(12 – 5) – 7 (Enhanced PLC-5 processors)

* multiply 5*2
6 * (5 * 2) (Enhanced PLC-5 processors)

| (vertical bar) divide 24 | 6
(24 | 6) *2 (Enhanced PLC-5 processors)

– negate – N7:0


** exponential * 10**3
(x to the power of y)

LN natural log * LN F8:20

LOG log to the base 10* LOG F8:3

Trigonometric ACS arc cosine* ACS F8:18

ASN arc sine* ASN F8:20

ATN arc tangent * ATN F8:22

COS cosine* COS F8:14

SIN sine* SIN F8:12

TAN tangent* TAN F8:16

Bitwise AND bitwise AND D9:3 AND D10:4

OR bitwise OR D10:4 OR D10:5

XOR bitwise exclusive OR D9:5 XOR D10:4

NOT bitwise complement NOT D9:3

Conversion FRD convert from BCD FRD N7:0
to binary

to BCD

DEG convert radians DEG F8:8
to degrees*

RAD convert degrees RAD F8:10
to radians*

* Available in Enhanced PLC-5 processors only.

1785-6.1 November 1998


Determining the Length of an Expression
:LWK (QKDQFHG 3/ SURFHVVRUV RX FDQ HQWHU FRPSOH[ LQVWUXFWLRQV
XS WR D WRWDO RI FKDUDFWHUV LQFOXGLQJ VSDFHV DQG SDUHQWKHVHV

'HSHQGLQJ RQ WKH RSHUDWRU WKH SURFHVVRU LQVHUWV FKDUDFWHUV
EHIRUHDIWHU WKH RSHUDWRU LQ RXU H[SUHVVLRQ WR IRUPDW WKH H[SUHVVLRQ
IRU HDVLHU LQWHUSUHWDWLRQ 8VH 7DEOH ' EHORZ WR GHWHUPLQH WKH
QXPEHU RI FKDUDFWHUV HDFK RSHUDWRU XVHV LQ DQ H[SUHVVLRQ
:LWK WKH 37 LQVWUXFWLRQ D PD[LPXP RI FKDUDFWHUV RI WKH
H[SUHVVLRQ DUH GLVSODDEOH ,I WKH H[SUHVVLRQ RX HQWHU LV QHDU WKLV
UXQV SURSHUO
7R ZRUN DURXQG WKLV GLVSOD SUREOHP H[SRUW WKH SURFHVVRU PHPRU
ILOH DQG PDNH RXU HGLWV LQ WKH 3 WH[W ILOH 7KHQ LPSRUW WKLV
WH[W ILOH
,PSRUWDQW RX FDQQRW HQWHU IORDWLQJ SRLQW QXPEHUV LQ VFLHQWLILF
QRWDWLRQ ZLWK QHJDWLYH H[SRQHQWV LQ FRPSOH[
H[SUHVVLRQV ,QVWHDG XVH WKH GHFLPDO HTXLYDOHQW RU SXW
WKH QXPEHU LQ D IORDWLQJ SRLQW ILOH DQG XVH WKH GDWD
DGGUHVV LQ WKH FRPSOH[ H[SUHVVLRQ

Table 4.D
Character Lengths for Operators

Uses this
This Operation: Using this Operator: Number of
Characters:

math binary +, –, *, | 3

OR, ** 4

AND, XOR 5

math unary – (negate) 2

LN * 3

FRD, TOD, DEG*, RAD*, SQR, NOT, LOG*, SIN*, 4
COS*, TAN*, ASN*, ACS*, ATN*

comparative =, , 3

, =, = 4


1785-6.1 November 1998


Determining the Order of Operation
7KH RSHUDWLRQV RX ZULWH LQWR WKH H[SUHVVLRQ DUH SHUIRUPHG E WKH
SURFHVVRU LQ D SUHVFULEHG RUGHU QRW QHFHVVDULO WKH RUGHU RX ZULWH
WKHP RX FDQ RYHUULGH WKH RUGHU RI RSHUDWLRQ E JURXSLQJ WHUPV
ZLWKLQ SDUHQWKHVHV IRUFLQJ WKH SURFHVVRU WR SHUIRUP WKH RSHUDWLRQ
ZLWKLQ WKH SDUHQWKHVHV DKHDG RI RWKHU RSHUDWLRQV
2SHUDWLRQV RI HTXDO RUGHU DUH SHUIRUPHG OHIW WR ULJKW 7KH H[SUHVVLRQ
RX XVH PXVW LQFOXGH DQ RSHUDWRU 7DEOH ( VKRZV WKH RUGHU RI
RSHUDWLRQ
Table 4.E
Order of Operation for CPT Expressions

Order Operation Description

1 ** exponential (XY)
Enhanced PLC-5 processors only

2 – negate

NOT bitwise complement

3 * multiply

| divide

4 + add

– subtract

5 AND bitwise AND

6 XOR bitwise exclusive OR

7 OR bitwise OR

Expression Examples
6LQJOH 9DOXH 7KH H[SUHVVLRQ 645 1

ZLWK GHVWLQDWLRQ 1
WHOOV WKH SURFHVVRU WR WDNH WKH VTXDUH URRW RI WKH YDOXH VWRUHG DW 1
DQG VWRUH WKH UHVXOW DW 1
0XOWLSOH 9DOXHV :LWK (QKDQFHG 3/ SURFHVVRUV RX FDQ DOVR XVH
IXQFWLRQV WR RSHUDWH RQ RQH RU PRUH YDOXHV LQ WKH H[SUHVVLRQ
FRPSOH[ H[SUHVVLRQV

IRU FRPSXWH DQG FRPSDUH RSHUDWLRQV
RPSOH[ H[SUHVVLRQV FDQ EH XS WR FKDUDFWHUV ORQJ VSDFHV DQG
SDUHQWKHVHV DUH FRQVLGHUHG FKDUDFWHUV

)RU H[DPSOH RX FRXOG HQWHU
DQ H[SUHVVLRQ VXFK DV

1785-6.1 November 1998


Example:

I:012 CPT
]
] COMPUTE
10
Destination N7:20
Expression
(N7:1 * 5) | (N7:2 | 7)

If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7.
If N7:1=5 and N7:2=9, the result is 25. (The result is rounded to the nearest whole number because the constants 5 and 7
were specified as whole numbers.)

:KHQ RX XVH FRPSOH[ H[SUHVVLRQV LI DQ RSHUDQG LV IORDWLQJ SRLQW
WKH HQWLUH H[SUHVVLRQ LV HYDOXDWHG DV IORDWLQJ SRLQW

Example:

I:012 CPT
]
] COMPUTE
10 Destination N7:20
Expression
(N7:1 * 5.0) | (N7:2 | 7.0)

If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7. If N7:1=5 and
N7:2=9, the result is 19. (The result is rounded differently because the constants 5.0 and 7.0 were specified to 1 decimal place.

Entering the Destination
(QWHU D GLUHFW RU LQGLUHFW ORJLFDO DGGUHVV IRU WKH GHVWLQDWLRQ 7KH
LQVWUXFWLRQ VWRUHV WKH UHVXOW RI WKH RSHUDWLRQ LQ WKH GHVWLQDWLRQ DGGUHVV
,PSRUWDQW 7KH SURFHVVRU DXWRPDWLFDOO FRQYHUWV WKH GDWD WSH
VSHFLILHG E WKH VRXUFH DGGUHVV WR WKDW VSHFLILHG E WKH
GHVWLQDWLRQ DGGUHVV 7KH SURFHVVRU XVHV %' IRU GLVSOD
RU FRPSDWLELOLW ZLWK 3/ IDPLO SURFHVVRUV RX
PXVW SURJUDP DQ %' FRQYHUVLRQV

Using CPT Functions
8VH IXQFWLRQV WR RSHUDWH RQ RQH RU PRUH YDOXHV LQ WKH H[SUHVVLRQ RI D
37 LQVWUXFWLRQ WR SHUIRUP WKHVH WSHV RI RSHUDWLRQV
‡ FRQYHUW IURP RQH QXPEHU IRUPDW WR DQRWKHU
‡ PDQLSXODWH QXPEHUV
‡ SHUIRUP WULJRQRPHWULF IXQFWLRQV

1785-6.1 November 1998


7KH LQVWUXFWLRQ SHUIRUPV WKH IXQFWLRQV

RX VSHFLI EDVHG RQ D
PQHPRQLF :KHQ RX HQWHU WKH H[SUHVVLRQ HQWHU WKH PQHPRQLF DV
WKH SUHIL[ WR WKH DGGUHVV RI WKH YDOXH RQ ZKLFK RX ZDQW WR RSHUDWH RU
DV D SUHIL[ WR WKH YDOXH LWVHOI ZKHQ HQWHUHG DV D SURJUDP FRQVWDQW
,PSRUWDQW )ORDWLQJSRLQW QXPEHUV DUH ELW YDOXHV ,QWHJHUV DUH
ELW YDOXHV 7KH LQVWUXFWLRQ DXWRPDWLFDOO FRQYHUWV WKH
GDWD WSHV IRXQG LQ WKH H[SUHVVLRQ WR WKH GDWD WSH
VSHFLILHG E WKH GHVWLQDWLRQ DGGUHVV

$77(17,21 ,I WKH H[SUHVVLRQ RU GHVWLQDWLRQ
DGGUHVVHV UHTXLUH FRQYHUVLRQ IURP ELW WR ELW GDWD
DQG WKH YDOXH LV WRR ODUJH WKH SURFHVVRU VHWV DQ RYHUIORZ
ELW LQ 6 DQG VHWV D PLQRU IDXOW 6

7KH UHVXOWLQJ
HUURQHRXV YDOXH FRXOG OHDG WR D GDQJHURXV VLWXDWLRQ
0RQLWRU WKLV ELW LQ RXU ODGGHU SURJUDP

7DEOH ) OLVWV WKH 37 IXQFWLRQV RX FDQ XVH
Table 4.F
CPT Functions for Number Conversion

Mnemonic Title Description

RAD * radians Converts from degrees to radians

DEG * degrees Converts from radians to degrees

TOD to BCD Converts from integer to BCD (supports 4-digit BCD
numbers)

FRD from BCD Converts from BCD to integer (supports 4-digit BCD
numbers)

SQR square root Takes the square root of the number; accurate to 6
significant digits

LOG * – Log to the base 10; accurate to 6 significant digits

LN * – Natural log; accurate to 6 significant digits

SIN * sine; manipulated in radians, accurate to 6 significant digits

COS * cosine; manipulated in radians, accurate to 6 significant digits

TAN * tangent; manipulated in radians, accurate to 6 significant digits

ASN * inverse sine; manipulated in radians, accurate to 6 significant digits

ACS * inverse cosine; manipulated in radians, accurate to 6 significant digits

ATN * inverse tangent; manipulated in radians, accurate to 6 significant digits


RX FDQ XVH WKH DERYH 37 DULWKPHWLF IXQFWLRQV ZLWKLQ H[SUHVVLRQV
RU DV VWDQGDORQH LQVWUXFWLRQV VHH WKH LQGLYLGXDO LQVWUXFWLRQV
GHVFULEHG LQ WKLV FKDSWHU

1785-6.1 November 1998


Arc Cosine (ACS)
(Enhanced PLC-5 Processors Only)

Description: 8VH WKH $6 LQVWUXFWLRQ WR WDNH WKH DUF FRVLQH RI WKH VRXUFH LQ
UDGLDQV

DQG VWRUH WKH UHVXOW LQ UDGLDQV

LQ WKH 'HVWLQDWLRQ 6HH 7DEOH
ACS
* IRU VWDWXV IODJV IRU WKH $6 LQVWUXFWLRQ
ARCCOSINE

Source 7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU
Destination HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D !NAN!
UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV
DOZDV JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ RU HTXDO WR π
ZKHUH π

Table 4.G
Updating Arithmetic Status Flags for an ACS Instruction

With this Bit: The Processor:

Carry (C) always resets

Overflow (V) sets if overflow generated; otherwise resets

Zero (Z) sets if result is zero; otherwise resets

Sign (S) always resets

Example:

I:012 ACS
]
] ARCCOSINE
Source F8:19
10 0.7853982
Destination F8:20
0.6674572

If input word 12, bit 10 is set, take the arc cosine of the value in F8:19 and store the result in F8:20.

1785-6.1 November 1998


Addition (ADD)

Description: 8VH WKH $'' LQVWUXFWLRQ WR DGG RQH YDOXH 6RXUFH $

WR DQRWKHU
YDOXH 6RXUFH %

DQG SODFH WKH UHVXOW LQ WKH GHVWLQDWLRQ 6RXUFH $ DQG
ADD
6RXUFH % FDQ HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV 6HH
ADD
7DEOH + IRU VWDWXV IODJV IRU WKH $'' LQVWUXFWLRQ
Source A

Source B ,PSRUWDQW 7KH $'' LQVWUXFWLRQ H[HFXWHV RQFH HDFK VFDQ DV ORQJ DV
Destination
WKH UXQJ LV WUXH LI RX RQO ZDQW YDOXHV DGGHG RQFH
LQFOXGH WKH 216 FRPPDQG VHH FKDSWHU

Table 4.H
Updating Arithmetic Status Flags for an ADD Instruction


Carry (C) sets if carry generated; otherwise resets



Sign (S) sets if result is negative; otherwise resets

Example:

I:012 ADD
]
] ADD
10 Source A N7:3
Source B N7:4
Destination N7:20

If input word 12, bit 10 is set, add the value in N7:3 to the value in N7:4 and store the result in N7:20.

1785-6.1 November 1998


Arc Sine (ASN)

Description: 8VH WKH $61 LQVWUXFWLRQ WR WDNH WKH DUF VLQH WKH VRXUFH LQ UDGLDQV

ASN
DQG VWRUH WKH UHVXOW LQ UDGLDQV

LQ WKH 'HVWLQDWLRQ 6HH 7DEOH , IRU
ARCSINE VWDWXV IODJV IRU $61 LQVWUXFWLRQ
Source
Destination
7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU
HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D !NAN!
UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV
DOZDV JUHDWHU WKDQ RU HTXDO WR ±π DQG OHVV WKDQ RU HTXDO WR π/2
ZKHUH π

Table 4.I
Updating Arithmetic Status Flags for an ASN Instruction






Example:

I:012 ASN
]
]
ARCSINE
10 Source F8:17
0.7853982
Dest F8:18
0.9033391

If input word 12, bit 10 is set, take the arc sine of the value in F8:17 and store the result in F8:18.

1785-6.1 November 1998


Arc Tangent (ATN)

Description: 8VH WKH $71 LQVWUXFWLRQ WR WDNH WKH DUF WDQJHQW RI WKH VRXUFH LQ
UDGLDQV

LQ WKH 'HVWLQDWLRQ 7KH
ATN
UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV DOZDV JUHDWHU WKDQ RU
HTXDO WR ±π DQG OHVV WKDQ RU HTXDO WR π/2 ZKHUH π

ARCTANGENT

Source
6HH 7DEOH - IRU VWDWXV IODJV IRU $71 LQVWUXFWLRQ
Destination
Table 4.J
Updating Arithmetic Status Flags for an ATN Instruction






Example:

I:012 ATN
ARCTANGENT
]
]
10 Source F8:21
0.7853982
Destination F8:22
0.6657737

If input word 12, bit 10 is set, take the arc tangent of the value in F8:21 and store the result in F8:22.

1785-6.1 November 1998


Average File (AVE)

Description: 7KH $9( LQVWUXFWLRQ FDOFXODWHV WKH DYHUDJH RI D VHW RI YDOXHV :KHQ
AVE
WKH UXQJ JRHV IURP IDOVH WR WUXH WKH YDOXH DW WKH FXUUHQW SRVLWLRQ LV
AVERAGE FILE EN DGGHG WR WKH QH[W YDOXH ZKLFK LV DGGHG WR WKH QH[W YDOXH DQG VR RQ
File
Destination 6HH 7DEOH . IRU VWDWXV IODJV IRU $9( LQVWUXFWLRQ
Control DN
Length
Position (DFK WLPH DQRWKHU YDOXH LV DGGHG WKH SRVLWLRQ ILHOG DQG WKH VWDWXV
ZRUG 6

LV LQFUHPHQWHG 7KH ILQDO VXP LV GLYLGHG E WKH QXPEHU
RI YDOXHV DGGHG DQG WKH UHVXOW LV VWRUHG LQ WKH GHVWLQDWLRQ
Table 4.K
Updating Arithmetic Status Flags for an AVE Instruction






$Q RYHUIORZ FDQ RFFXU LI
‡ WKH LQWHUPHGLDWH VXP H[FHHGV WKH PD[LPXP IORDWLQJ SRLQW YDOXH
‡ WKH GHVWLQDWLRQ LV DQ LQWHJHU DGGUHVV DQG WKH ILQDO YDOXH LV JUHDWHU
WKDQ RU OHVV WKDQ ±
,I DQ RYHUIORZ RFFXUV WKH SURFHVVRU VWRSV WKH FDOFXODWLRQ VHWV WKH (5
ELW DQG WKH 'HVWLQDWLRQ UHPDLQV XQFKDQJHG 7KH SRVLWLRQ LGHQWLILHV
WKH HOHPHQW WKDW FDXVHG WKH RYHUIORZ :KHQ RX FOHDU WKH (5 ELW WKH
SRVLWLRQ UHVHWV WR DQG WKH DYHUDJH LV UHFDOFXODWHG
,PSRUWDQW 8VH WKH 5(6 LQVWUXFWLRQ WR FOHDU WKH VWDWXV IODJV

Entering Parameters
7R SURJUDP WKH $9( LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU
ZLWK WKH IROORZLQJ
‡ )LOH LV WKH DGGUHVV WKDW FRQWDLQV WKH ILUVW YDOXH WR EH DGGHG 7KLV
DGGUHVV FDQ EH IORDWLQJ SRLQW RU LQWHJHU
‡ 'HVWLQDWLRQ LV WKH DGGUHVV ZKHUH WKH UHVXOW RI WKH LQVWUXFWLRQ LV
VWRUHG 7KLV DGGUHVV FDQ EH IORDWLQJ SRLQW RU LQWHJHU
‡ RQWURO LV WKH DGGUHVV RI WKH FRQWURO VWUXFWXUH LQ WKH FRQWURO DUHD
5

RI SURFHVVRU PHPRU 7KH SURFHVVRU VWRUHV LQIRUPDWLRQ VXFK
DV WKH OHQJWK SRVLWLRQ DQG VWDWXV DQG XVHV WKLV LQIRUPDWLRQ WR
H[HFXWH WKH LQVWUXFWLRQ
‡ /HQJWK LV WKH QXPEHU RI ZRUGV LQ WKH ILOH

‡ 3RVLWLRQ SRLQWV WR WKH ZRUG WKDW WKH LQVWUXFWLRQ LV FXUUHQWO XVLQJ

1785-6.1 November 1998


Using Status Bits
7R XVH WKH $9( LQVWUXFWLRQ FRUUHFWO H[DPLQH VWDWXV ELWV LQ WKH
FRQWURO VWUXFWXUH $GGUHVV WKHVH ELWV E PQHPRQLF

This Bit: Is Set:

Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction
is enabled. The instruction follows the rung condition.

Done .DN (bit 13) after the instruction finishes operating. After the rung goes
false, the processor resets the .DN bit on the next false-to-true
rung transition.

Error .ER (bit 11) when the operation generates an overflow. The instruction
stops until the ladder program resets the .ER bit.

,PSRUWDQW 7KH $9( LQVWUXFWLRQ FDOFXODWHV WKH DYHUDJH XVLQJ
IORDWLQJ SRLQW UHJDUGOHVV RI WKH WSH VSHFLILHG IRU WKH ILOH
RU GHVWLQDWLRQ SDUDPHWHUV

$77(17,21 7KH $9( LQVWUXFWLRQ LQFUHPHQWV WKH
RIIVHW YDOXH VWRUHG DW 6 0DNH VXUH RX PRQLWRU RU
ORDG WKH RIIVHW YDOXH RX ZDQW SULRU WR XVLQJ DQ LQGH[HG
DGGUHVV 2WKHUZLVH XQSUHGLFWDEOH PDFKLQH RSHUDWLRQ
FRXOG RFFXU ZLWK SRVVLEOH GDPDJH WR HTXLSPHQW DQGRU
LQMXU WR SHUVRQQHO

Example:
I:012 AVE
]
] AVERAGE FILE EN
10 File #N7:1
Dest N7:0 DN
Control R6:0
Length 4
Position 0

R6:0 O:010
]
]
EN 5

R6:0 O:010
]
]
DN 7

R6:0
RES

If input word 12, bit 10 is set, the AVE instruction is enabled. The values in N7:1, N7:2, N7:3, and N7:4 are
added together and divided by 4. The result is stored in N7:0. When the calculation is complete, output
word 10, bit 7 is set. Then the RES instruction resets the status bits of the control file R6:0.

1785-6.1 November 1998


Clear (CLR)

Description: 8VH WKH /5 LQVWUXFWLRQ WR VHW DOO WKH ELWV RI D ZRUG WR ]HUR 7KH
CLR
GHVWLQDWLRQ PXVW EH D ZRUG DGGUHVV 6HH 7DEOH / IRU VWDWXV IODJV IRU
CLEAR /5 LQVWUXFWLRQ
Destination Table 4.L
Updating Arithmetic Status Flags for a CLR Instruction



Overflow (V) always resets

Zero (Z) always sets


Example:

I:012 CLR
]
]
CLEAR
10 Destination N7:3

If input word 12, bit 10 is set, clear all of the bits in N7:3 to zero.

1785-6.1 November 1998


Cosine (COS)

Description: 8VH WKH 26 LQVWUXFWLRQ WR WDNH WKH FRVLQH RI D QXPEHU 6RXUFH LQ
UDGLDQV

DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 0 IRU
COS
VWDWXV IODJV IRU 26 LQVWUXFWLRQ
COSINE

Source 7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ
Destination RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D
!INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH
'HVWLQDWLRQ LV DOZDV JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU
HTXDO WR
,PSRUWDQW )RU JUHDWHVW DFFXUDF WKH VRXUFH GDWD VKRXOG EH JUHDWHU
WKDQ RU HTXDO WR ±π DQG OHVV WKDQ RU HTXDO WR π

Table 4.M
Updating Arithmetic Status Flags for an COS Instruction






Example:

I:012 COS
]
] COSINE
10 Source F8:13
0.7853982
Destination F8:14
0.7071068

If input word 12, bit 10 is set, take the cosine of the value in F8:13 and store the result in F8:14.

1785-6.1 November 1998


Divide (DIV)

Description: 8VH WKH ',9 LQVWUXFWLRQ WR GLYLGH RQH YDOXH 6RXUFH $

E DQRWKHU
YDOXH 6RXUFH %

DQG SODFH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH $ DQG
DIV
DIVIDE
6RXUFH % FDQ HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV 6HH
Source A 7DEOH 1 IRU VWDWXV IODJV IRU ',9 LQVWUXFWLRQ
Source B
,PSRUWDQW 7KH FRPSXWH LQVWUXFWLRQV H[HFXWH IRU HDFK VFDQ DV ORQJ
Destination
DV WKH UXQJ LV WUXH LI RX RQO ZDQW YDOXHV FRPSXWHG
RQFH LQFOXGH WKH 216 FRPPDQG VHH FKDSWHU

Table 4.N
Updating Arithmetic Status Flags for a DIV Instruction



Overflow (V) sets if division by zero or if overflow generated;
otherwise resets

Zero (Z) sets if result is zero; otherwise resets;
undefined if overflow is set

Sign (S) sets if result is negative; otherwise resets;
undefined if overflow is set

Example:

I:012 DIV
]
] DIVIDE
10 Source A N7:3
Source B N7:4
Destination N7:20

If input word 12, bit 10 is set, divide the value in N7:3 by the value in N7:4 and store the result in N7:20.

1785-6.1 November 1998


Natural Log (LN)

Description: 8VH WKH /1 LQVWUXFWLRQ WR WDNH WKH QDWXUDO ORJ RI WKH YDOXH LQ WKH
LN 6RXUFH DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 2 IRU VWDWXV
NATURAL LOG IODJV IRU /1 LQVWUXFWLRQ
Source
,I WKH 6RXUFH LV HTXDO WR WKH UHVXOW LQ WKH 'HVWLQDWLRQ ZLOO EH
Destination
!-INF! LI WKH YDOXH LQ WKH 6RXUFH LV OHVV WKDQ WKH UHVXOW LQ WKH
'HVWLQDWLRQ ZLOO EH !NAN! 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV
DOZDV JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU HTXDO WR

Table 4.O
Updating Arithmetic Status Flags for an LN Instruction






Example:

I:012 LN
]
] NATURAL LOG
10 Source N7:0
5
Destination F8:20
1.609438

If input word 12, bit 10 is set, take the natural log of the value in N7:0 and store the result in F8:20.

1785-6.1 November 1998


Log to the Base 10 (LOG)

Description: 8VH WKH /2* LQVWUXFWLRQ WR WDNH WKH ORJ EDVH RI WKH YDOXH LQ WKH
LOG
6RXUFH DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 3 IRU VWDWXV
LOG BASE 10
IODJV IRU /2* LQVWUXFWLRQ
Source
,I WKH 6RXUFH LV HTXDO WR WKH UHVXOW LQ WKH 'HVWLQDWLRQ ZLOO EH
Destination
!-INF! LI WKH YDOXH LQ WKH 6RXUFH LV OHVV WKDQ WKH UHVXOW LQ WKH
'HVWLQDWLRQ ZLOO EH !NAN! 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV
DOZDV JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU HTXDO WR

Table 4.P
Updating Arithmetic Status Flags for an LOG Instruction






Example:

I:012 LOG
]
] LOG BASE 10
10 Source N7:2
5
Destination F8:3
0.6989700

If input word 12, bit 10 is set, take the log base 10 of the value in N7:2 and store the result in F8:3.

1785-6.1 November 1998


Multiply (MUL)

Description: 8VH WKH 08/ LQVWUXFWLRQ WR PXOWLSO RQH YDOXH 6RXUFH $

DQG SODFH WKH UHVXOW LQ WKH GHVWLQDWLRQ 6RXUFH $ DQG
MUL
6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV 6HH 7DEOH 4 IRU VWDWXV IODJV IRU
MULTIPLY
08/ LQVWUXFWLRQ
Source A

Source B Table 4.Q
Updating Arithmetic Status Flags for a MUL Instruction
Destination






Example:

I:012 MUL
]
] MULTIPLY
10 Source A N7:3
Source B N7:4
Destination N7:20

If input word 12, bit 10 is set, multiply the value in N7:3 by the value in N7:4 and store the result in N7:20.

1785-6.1 November 1998


Negate (NEG)

Description: 8VH WKH 1(* LQVWUXFWLRQ WR FKDQJH WKH VLJQ RI D YDOXH ,I RX QHJDWH D
QHJDWLYH YDOXH WKH UHVXOW LV SRVLWLYH LI RX QHJDWH D SRVLWLYH YDOXH
NEG
WKH UHVXOW LV QHJDWLYH 6HH 7DEOH 5 IRU VWDWXV IODJV IRU 1(*
NEGATE
LQVWUXFWLRQ
Source
Destination ,PSRUWDQW 7KH FRPSXWH LQVWUXFWLRQV H[HFXWH IRU HDFK VFDQ DV ORQJ
DV WKH UXQJ LV WUXH LI RX RQO ZDQW YDOXHV FRPSXWHG
RQFH LQFOXGH WKH 216 FRPPDQG VHH FKDSWHU

Table 4.R
Updating Arithmetic Status Flags for a NEG Instruction


Carry (C) sets if the operation generates a carry




Example:

I:012 NEG
]
] NEGATE
10 Source N7:3
Destination N7:20

If input word 12, bit 10 is set, take the opposite sign of the value in N7:3 and store the result in N7:20.

1785-6.1 November 1998


Sine (SIN)

Description: 8VH WKH 6,1 LQVWUXFWLRQ WR WDNH WKH VLQH RI D QXPEHU 6RXUFH LQ
UDGLDQV

DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 6 IRU
SIN
SINE
VWDWXV IODJV IRU 6,1 LQVWUXFWLRQ
Source
7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ
Destination
RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D
!INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH
'HVWLQDWLRQ LV DOZDV JUHDWHU WKDQ RU HTXDO WR ± DQG OHVV WKDQ RU
HTXDO WR

Table 4.S
Updating Arithmetic Status Flags for an SIN Instruction






Example:

I:012 SIN
]
] SINE
Source F8:11
10
0.7853982
Destination F8:12
0.7071068

If input word 12, bit 10 is set, take the sine of F8:11 and store the result in F8:12.

1785-6.1 November 1998


Square Root (SQR)

Description: 8VH WKH 645 LQVWUXFWLRQ WR WDNH WKH VTXDUH URRW RI D YDOXH DQG VWRUH
WKH UHVXOW LQ WKH GHVWLQDWLRQ 7KH VRXUFH FDQ EH D YDOXH RU DQ DGGUHVV
SQR
SQUARE ROOT
,I WKH VRXUFH YDOXH LV QHJDWLYH WKH SURFHVVRU WDNHV LWV DEVROXWH YDOXH
Source
DQG SHUIRUPV WKH VTXDUH URRW IXQFWLRQ 6HH 7DEOH 7 IRU VWDWXV IODJV
Destination IRU 645 LQVWUXFWLRQ
,PSRUWDQW 7KH 645 LQVWUXFWLRQ H[HFXWHV RQFH IRU HDFK VFDQ DV
ORQJ DV WKH UXQJ LV WUXH LI RX RQO ZDQW YDOXHV
FRPSXWHG RQFH LQFOXGH WKH 216 FRPPDQG VHH
FKDSWHU

Table 4.T
Updating Arithmetic Status Flags for a SQR Instruction



Overflow (V) sets if overflow generated during floating-point
to integer conversion; otherwise resets



Example:

I:012 SQR
]
] SQUARE ROOT
10 Source N7:3
Destination N7:20

If input word 12, bit 10 is set, take the square root of the value in N7:3 and store the result in N7:20.

1785-6.1 November 1998


Sort File (SRT)

Description: 7KH 657 LQVWUXFWLRQ VRUWV D VHW RI YDOXHV LQWR DVFHQGLQJ RUGHU 7KLV
LQVWUXFWLRQ LV H[HFXWHG RQ D IDOVHWRWUXH WUDQVLWLRQ
SRT
SORT FILE EN ,PSRUWDQW 0DNH VXUH WKH ILOH OHQJWK YDOXH RX VSHFLI LQ WKH
File
LQVWUXFWLRQ GRHV QRW FDXVH WKH LQGH[HG DGGUHVV WR H[FHHG
Control DN
Length WKH ILOH ERXQGV 7KH SURFHVVRU GRHV QRW FKHFN WKLV
Position
XQOHVV RX H[FHHG WKH GDWD ILOH DUHD RI PHPRU
,I WKH LQGH[HG DGGUHVV H[FHHGV WKH GDWD ILOH DUHD WKH
SURFHVVRU LQLWLDWHV D UXQWLPH HUURU DQG VHWV D PDMRU
IDXOW 7KH SURFHVVRU GRHV QRW FKHFN WR VHH ZKHWKHU WKH
LQGH[HG DGGUHVV FURVVHV ILOH WSHV VXFK DV 1 WR )

Entering Parameters
7R SURJUDP WKH 657 LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ


file the address that contains the first value to be sorted. This address can be
floating point or integer.

control the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.

length the number of words in the file (1-1000).

position points to the element that the instruction is currently using.

1785-6.1 November 1998


Using Status Bits
7R XVH WKH 657 LQVWUXFWLRQ FRUUHFWO WKH ODGGHU SURJUDP PXVW
H[DPLQH VWDWXV ELWV LQ WKH FRQWURO VWUXFWXUH RX DGGUHVV WKHVH ELWV
E PQHPRQLF

This Bit: Is Set:

Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction is
enabled. The instruction follows the rung condition.

Done .DN (bit 13) after the instruction finishes operating. After the rung goes false,
the processor resets the .DN bit on the next false-to-true rung
transition.

Error .ER (bit 11) when the length value is less than or equal to zero or when the
position value is less than zero.

$77(17,21 7KH 657 LQVWUXFWLRQ PDQLSXODWHV WKH
LQMXU WR SHUVRQQHO

Example:

I:012 SRT
]
] SORT FILE EN
10 File #N7:1
Control R6:0
Length 4 DN
Position 0

R6:0 O:010
]
]
EN 5
R6:0 O:010
]
]
DN 7

If input word 12, bit 10 is set, the SRT instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are sorted into ascending
order. When the sort operation is complete, output word 10, bit 7 is set.

1785-6.1 November 1998


Standard Deviation (STD)

Description: 7KH 67' LQVWUXFWLRQ FDOFXODWHV WKH VWDQGDUG GHYLDWLRQ RI D VHW RI
STD
YDOXHV DQG VWRUHV WKH UHVXOW LQ WKH GHVWLQDWLRQ 7KLV LQVWUXFWLRQ LV
STANDARD DEVIATION EN H[HFXWHG RQ D IDOVHWRWUXH WUDQVLWLRQ 6HH 7DEOH 8 IRU VWDWXV IODJV
File IRU 67' LQVWUXFWLRQ
Destination DN
Control
Length
7KH VWDQGDUG GHYLDWLRQ LV FDOFXODWHG DFFRUGLQJ WR WKH IROORZLQJ
Position IRUPXOD
Standard 2
Deviation =  SUM((xi – AVE(xi)) 

 (N – 1) 
:KHUH
‡ 680

± VXPPDWLRQ IXQFWLRQ RI WKH HQFORVHG YDULDEOHV
‡ $9(

± DYHUDJH IXQFWLRQ RI WKH HQFORVHG YDULDEOHV
‡ [L ± YDULDEOH HOHPHQWV RI WKH GDWD ILOH
‡ 1 ± QXPEHU RI HOHPHQWV LQ WKH GDWD ILOH
,PSRUWDQW 0DNH VXUH WKH ILOH OHQJWK YDOXH RX VSHFLI LQ WKH
LQVWUXFWLRQ GRHV QRW FDXVH WKH LQGH[HG DGGUHVV WR H[FHHG
WKH ILOH ERXQGV 7KH SURFHVVRU GRHV QRW FKHFN WKLV
XQOHVV RX XVH DQ LQGH[HG LQGLUHFW DGGUHVV RU H[FHHG WKH
GDWD ILOH DUHD RI PHPRU ,I WKH LQGH[HG DGGUHVV H[FHHGV
WKH GDWD ILOH DUHD WKH SURFHVVRU LQLWLDWHV D UXQWLPH HUURU
DQG VHWV D PDMRU IDXOW 7KH SURFHVVRU GRHV QRW FKHFN WR
VHH ZKHWKHU WKH LQGH[HG DGGUHVV FURVVHV ILOH WSHV VXFK
DV 1 WR )

Table 4.U
Updating Arithmetic Status Flags for an STD Instruction






1785-6.1 November 1998


7KHUH DUH WZR ZDV DQ RYHUIORZ FDQ RFFXU
‡ WKH LQWHUPHGLDWH VXP H[FHHGV WKH PD[LPXP IORDWLQJ SRLQW YDOXH
IORDWLQJ SRLQW YDOXHV DUH ± WR ±r±'

r'

‡ WKH GHVWLQDWLRQ LV DQ LQWHJHU DGGUHVV DQG WKH ILQDO YDOXH LV JUHDWHU
WKDQ
,I DQ RYHUIORZ RFFXUV WKH SURFHVVRU VWRSV WKH FDOFXODWLRQ VHWV WKH (5
ELW DQG OHDYHV WKH GHVWLQDWLRQ XQFKDQJHG 7KH SRVLWLRQ LGHQWLILHV WKH
HOHPHQW WKDW FDXVHG WKH RYHUIORZ :KHQ RX FOHDU WKH (5 ELW WKH
SRVLWLRQ UHVHWV WR DQG WKH VWDQGDUG GHYLDWLRQ LV UHFDOFXODWHG
,PSRUWDQW 8VH WKH 5(6 LQVWUXFWLRQ WR FOHDU WKH VWDWXV ELWV

Entering Parameters
7R SURJUDP WKH 67' LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ

Parameter: Defines:

file the address that contains the first value to be calculated. This address
can be floating point or integer.

destination the address where the result of the instruction is stored. This address
can be floating point or integer.

control the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.

length the number of words in the file (1-1000).

position points to the element that the instruction is currently using.

Using Status Bits
7R XVH WKH 67' LQVWUXFWLRQ FRUUHFWO H[DPLQH VWDWXV ELWV LQ WKH
FRQWURO VWUXFWXUH RX DGGUHVV WKHVH ELWV E PQHPRQLF

This Bit: Is Set:

Enable .EN (bit 15) on a false-to-true rung transition to indicate that the instruction
is enabled. The instruction follows the rung condition.

Done .DN (bit 13) after the instruction finishes operating. After the rung goes
false, the processor resets the .DN bit on the next false-to-true
rung transition.

Error .ER (bit 11) when the operation generates an overflow. The instruction
stops until the ladder program resets the .ER bit.

1785-6.1 November 1998


,PSRUWDQW 7KH 67' LQVWUXFWLRQ FDOFXODWHV WKH VWDQGDUG GHYLDWLRQ
XVLQJ IORDWLQJ SRLQW UHJDUGOHVV RI WKH WSH VSHFLILHG IRU
WKH ILOH RU GHVWLQDWLRQ SDUDPHWHUV

$77(17,21 7KH 67' LQVWUXFWLRQ PDQLSXODWHV WKH
LQMXU WR SHUVRQQHO

Example:

I:012 STD
]
] STANDARD DEVIATION EN
10 File #N7:1
Destination N7:0
Control R6:0 DN
Length 4
Position 0

R6:0 O:010
]
]
EN 5
R6:0 O:010
]
]
DN 7
R6:0
RES

If input word 12, bit 10 is set, the STD instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are used to calculate the
standard deviation. When the calculation is complete, output word 10, bit 7 is set. Then the RES instruction resets the status bits of
the control file R6:0.

1785-6.1 November 1998


Subtract (SUB)

Description: 8VH WKH 68% LQVWUXFWLRQ WR VXEWUDFW RQH YDOXH 6RXUFH %

IURP
SUB
DQRWKHU YDOXH 6RXUFH $

DQG SODFH WKH UHVXOW LQ WKH GHVWLQDWLRQ
SUBTRACT 6RXUFH $ DQG 6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ
Source A YDOXHV 6HH 7DEOH 9 IRU VWDWXV IODJV IRU 68% LQVWUXFWLRQ
Source B
Destination ,PSRUWDQW 7KH 68% LQVWUXFWLRQ H[HFXWHV RQFH IRU HDFK VFDQ DV
ORQJ DV WKH UXQJ LV WUXH LI RX RQO ZDQW YDOXHV
VXEWUDFWHG RQFH LQFOXGH WKH 216 FRPPDQG VHH
FKDSWHU

Table 4.V
Updating Arithmetic Status Flags for a SUB Instruction


Carry (C) sets if borrow generated; otherwise resets

Overflow (V) sets if underflow generated; otherwise resets



Example:

I:012 SUB
]
] SUBTRACT
10 Source A N7:3
Source B N7:4
Destination N7:20

If input word 12, bit 10 is set, subtract the value in N7:4 from the value in N7:3 and store the result in N7:20.

1785-6.1 November 1998


Tangent (TAN)

Description: 8VH WKH 7$1 LQVWUXFWLRQ WR WDNH WKH WDQJHQW RI D QXPEHU 6RXUFH LQ
UDGLDQV

DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH : IRU
TAN
TANGENT
VWDWXV IODJV IRU 7$1 LQVWUXFWLRQ
Source
7KH YDOXH LQ WKH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR ±
Destination
DQG OHVV WKDQ RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH
SURFHVVRU UHWXUQV D !INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ
YDOXH LQ WKH 'HVWLQDWLRQ LV DOZDV D UHDO QXPEHU

Table 4.W
Updating Arithmetic Status Flags for an TAN Instruction






Example:

I:012 TAN
]
] TANGENT
10 Source F8:15
0.7853982
Destination F8:16
1.000000

If input word 12, bit 10 is set, take the tangent of the value in F8:15 and store the result in F8:16.

1785-6.1 November 1998


X to the Power of Y (XPY)

Description: 8VH WKH ;3 LQVWUXFWLRQ WR UDLVH D YDOXH 6RXUFH $

WR D SRZHU
XPY
6RXUFH %

DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ ,I WKH YDOXH LQ
X TO POWER OF Y 6RXUFH $ LV QHJDWLYH WKH H[SRQHQW 6RXUFH %

VKRXOG EH DQ LQWHJHU
Source A YDOXH LI WKH H[SRQHQW LV QRW DQ LQWHJHU IRU H[DPSOH LI LW LV D IORDWLQJ
Source B SRLQW YDOXH

WKH RYHUIORZ ELW LV VHW DQG WKH DEVROXWH YDOXH RI WKH EDVH
Destination
LV XVHG LQ WKH FDOFXODWLRQ 6HH 7DEOH ; IRU VWDWXV IODJV IRU ;3
LQVWUXFWLRQ
7KH ;3 LQVWUXFWLRQ XVHV WKH IROORZLQJ DOJRULWKP
;3

ORJ ;

,I DQ RI WKH LQWHUPHGLDWH RSHUDWLRQV LQ WKLV DOJRULWKP SURGXFH DQ
RYHUIORZ WKH DULWKPHWLF PLQRU IDXOW ELW LV VHW 6

7KH
DULWKPHWLF VWDWXV IODJ ELW LV VHW RQO LI WKH ILQDO UHVXOW LV DQ RYHUIORZ
,PSRUWDQW .HHS LQ PLQG WKDW [ LV HTXDO WR [ LV HTXDO WR )RU
IORDWLQJ SRLQW QXPEHUV LV HTXDO WR !NAN! DQ
LQYDOLG PDWKHPDWLFDO YDOXH

DQG IRU LQWHJHUV LV HTXDO
WR ±.

Table 4.X
Updating Arithmetic Status Flags for an XPY Instruction






Example:

I:012 XPY
]
] X TO POWER OF Y
10 Source A N7:4
5
Source B N7:5
2
Destination N7:6
25

If input word 12, bit 10 is set, take the value in N7:4, raise it to the power of the value in N7:5, and stores
the result in N7:6.

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 5
Logical Instructions AND, NOT, OR, XOR
Using Logical Instructions 7KHVH LQVWUXFWLRQV 7DEOH $

SHUIRUP ORJLFDO RSHUDWLRQV
Table 5.A
Available Logical Instructions


Perform an AND operation AND 5-2

Perform a NOT operation NOT 5-3

Perform an OR operation OR 5-4

Perform an XOR operation XOR 5-5

7KH SDUDPHWHUV RX HQWHU DUH SURJUDP FRQVWDQWV RU GLUHFW ORJLFDO
DGGUHVVHV
HDFK RSHUDQG

$SSHQGL[

Using Arithmetic Status Flags
7KH DULWKPHWLF VWDWXV ELWV DUH LQ ZRUG ELWV LQ WKH SURFHVVRU VWDWXV
ILOH 6

7DEOH % OLVWV WKH VWDWXV IODJV
Table 5.B
Arithmetic Status Flags


S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)

1785-6.1 November 1998

5-2 Logical Instructions AND, NOT, OR, XOR

AND Operation (AND)

Description: 8VH WKH $1' LQVWUXFWLRQ WR SHUIRUP DQ $1' RSHUDWLRQ XVLQJ WKH ELWV
LQ WKH WZR VRXUFH DGGUHVVHV
AND
BITWISE AND Table 5.C
Source A Truth Table for an AND Operation
Source B
Destination
Source A Source B Result

0 0 0

1 0 0

0 1 0

1 1 1

Table 5.D
Updating Arithmetic Status Flags for an AND Instruction





Sign (S) sets if most-significant bit is set;
otherwise resets

Example:

I:012 AND
[
[
AND
10 Source A N9:3
Source B N10:4
Destination N12:3

If input word 12, bit 10 is set, the processor performs an AND
operation on N9:3 and N10:4 and stores the result in N12:3.

Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1

Destination
N12:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

1785-6.1 November 1998

Logical Instructions AND, NOT, OR, XOR 5-3

NOT Operation (NOT)

Description: 8VH WKH 127 LQVWUXFWLRQ WR SHUIRUP D 127 RSHUDWLRQ XVLQJ WKH ELWV LQ
WKH VRXUFH DGGUHVV 7KLV RSHUDWLRQ LV DOVR NQRZ DV D ELW LQYHUVLRQ
NOT
NOT ,PSRUWDQW 7KH 127 LQVWUXFWLRQ LV QRW DYDLODEOH RQ 3/
Source VHULHV $ SURFHVVRUV
Destination
Table 5.E
Truth Table for a NOT Operation

Source Result

0 1

1 0

Table 5.F
Updating Arithmetic Status Flags for a NOT Instruction





otherwise resets

Example:

I:012 NOT
[
[
NOT
10 Source N9:3
Destination N10:4

If input word 12, bit 10 is set, the processor performs a
NOT operation on N9:3 and stores the result in N10:4

Source
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

Destination
N10:4
1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1

1785-6.1 November 1998


OR Operation (OR)

Description: 8VH WKH 25 LQVWUXFWLRQ WR SHUIRUP DQ 25 RSHUDWLRQ XVLQJ WKH ELWV LQ
OR
WKH WZR VRXUFHV FRQVWDQWV RU DGGUHVVHV

BITWISE INCLUSIVE OR Table 5.G
Source A Truth Table for an OR Operation
Source B
Destination
Source A Source B Result

0 0 0

1 0 1

0 1 1

1 1 1

Table 5.H
Updating Arithmetic Status Flags for an OR Instruction





otherwise resets

Example:

I:012 OR
[
[ INCLUSIVE OR
10 Source A N9:3
Source B N10:4
Destination N12:3
If input word 12, bit 10 is set, the processor performs
an OR operation on N9:3 and N10:4 and stores the
result in N12:3.

Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1

Destination
N12:3
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1

1785-6.1 November 1998

Logical Instructions AND, NOT, OR, XOR 5-5

Exclusive OR Operation (XOR)

Description: 8VH WKH ;25 LQVWUXFWLRQ WR SHUIRUP DQ H[FOXVLYH 25 RSHUDWLRQ XVLQJ
WKH ELWV LQ WKH WZR VRXUFHV FRQVWDQWV RU DGGUHVVHV

XOR
BITWISE EXCLUSIVE OR Table 5.I
Source A Truth Table for an XOR Operation
Source B

Destination Source A Source B Result

0 0 0

1 0 1

0 1 1

1 1 0

Table 5.J
Updating Arithmetic Status Bits for an XOR Instruction





Sign (S) sets if most-significant bit is set; otherwise resets

Example:

I:012 XOR
[ EXCLUSIVE OR
[
10 Source A N9:3
Source B N10:4
If input word 12, bit 10 is set, the processor performs Destination N12:3
an XOR operation on N9:3 and N10:4 and stores the
result in N12:3.
Source A
N9:3 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

Source B
N10:4 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1

Destination
N12:3
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 6
Conversion Instructions FRD and TOD,
DEG and RAD
Using the Conversion Instructions 7KH FRQYHUVLRQ LQVWUXFWLRQV FRQYHUW LQWHJHU WR %' DQG FRQYHUW %'
WR LQWHJHU XVLQJ 72' DQG )5'

)RU H[DPSOH XVH 72' DQG )5' IRU
VLJQDOV WRIURP %' ,2 GHYLFHV IRU GLVSOD SXUSRVHV RU IRU QXPEHU
FRPSDWLELOLW ZLWK 3/ IDPLO SURFHVVRUV RX FDQ DOVR FRQYHUW
UDGLDQV WR GHJUHHV DQG GHJUHHV WR UDGLDQV XVLQJ '(* DQG 5$'

)RU
H[DPSOH RX FDQ XVH '(* DQG 5$' ZLWK WKH WULJRQRPHWULF
LQVWUXFWLRQV VHH FKDSWHU

7DEOH $ OLVWV WKH DYDLODEOH FRQYHUVLRQ LQVWUXFWLRQV
Table 6.A
Available Conversion Instructions


Convert from integer to BCD TOD 6-2

Convert from BCD to integer FRD 6-2

Convert radians to degrees DEG* 6-3

Convert degrees to radians RAD* 6-4

* These instructions are only supported by Enhanced PLC-5 processors.

RI WKH YDOXHV RX ZDQW
HDFK RSHUDQG

$SSHQGL[

Using Arithmetic Status Flags
7KH DULWKPHWLF VWDWXV IODJV DUH LQ ZRUG ELWV LQ WKH SURFHVVRU
VWDWXV ILOH 6

7DEOH % OLVWV WKH VWDWXV IODJV
Table 6.B
Arithmetic Status Flags


S:0/0 Carry (C)

S:0/1 Overflow (V)

S:0/2 Zero (Z)

S:0/3 Sign (S)

1785-6.1 November 1998

6-2 Conversion Instructions FRD and TOD, DEG and RAD

Convert to BCD (TOD)

Description: 8VH WKH 72' LQVWUXFWLRQ WR FRQYHUW DQ LQWHJHU YDOXH WR D %' YDOXH
,I WKH LQWHJHU YDOXH LV JUHDWHU WKDQ WKH SURFHVVRU VWRUHV DQG
TOD
VHWV WKH RYHUIORZ ELW ,I WKH LQWHJHU YDOXH LV QHJDWLYH WKH SURFHVVRU
TO BCD
VWRUHV LQ WKH GHVWLQDWLRQ DQG VHWV WKH RYHUIORZ DQG ]HUR VWDWXV ELWV
Source
Table 6.C
Destination
Updating Arithmetic Status Flags for a TOD Instruction



Overflow (V) sets if integer value is outside the range
0-9999; otherwise resets

Zero (Z) sets if destination value is negative or
zero; otherwise resets


Example:

I:012 TOD
]
] TO BCD
10 Source N7:3
Destination D9:3

If input word 12, bit 10 is set, convert the value in N7:3 to a BCD value and store the result in D9:3.

Convert from BCD (FRD)

Description: 8VH WKH )5' LQVWUXFWLRQ WR FRQYHUW D %' YDOXH WR DQ LQWHJHU YDOXH
RQYHUW %' YDOXHV WR LQWHJHU YDOXHV EHIRUH RX PDQLSXODWH WKRVH
FRD
YDOXHV ZLWK ODGGHU ORJLF EHFDXVH WKH SURFHVVRU WUHDWV %' YDOXHV DV
FROM BCD LQWHJHU YDOXHV 7KH DFWXDO %' YDOXH PD EH ORVW RU GLVWRUWHG
Source
Table 6.D
Destination
Updating Arithmetic Status Flags for a TOD Instruction




Zero (Z) sets if destination value is zero; otherwise resets


1785-6.1 November 1998

Conversion Instructions FRD and TOD, DEG and RAD 6-3

7KH )5' LQVWUXFWLRQ ZLOO FRQYHUW D QRQGHFLPDO QXPEHU ZLWKRXW DQ
HUURU FRQGLWLRQ )RU H[DPSOH LI D ³´ LV LQ WKH VRXUFH LW LV FRQYHUWHG
WR ³´ HYHQ WKRXJK ³´ LV QRW D YDOLG GHFLPDO QXPEHU

Example:

I:012 FRD
]
] FROM BCD
10 Source D9:3
Destination N7:3

If input word 12, bit 10 is set, convert the value in D9:3 to an integer value and store the result in N7:3.

Degree (DEG)

Description: 8VH WKH '(* LQVWUXFWLRQ WR FRQYHUW UDGLDQV 6RXUFH

WR GHJUHHV DQG
DEG
VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH WLPHV π

RADIANS TO DEGREE Table 6.E
Source Updating Arithmetic Status Flags for an DEG Instruction
Destination






Example:

I:012 DEG
]
] RADIANS TO DEGREE
10 Source F8:7
0.7853982
Destination F8:8
45

If input word 12, bit 10 is set, convert the value in F8:7 to degrees and store the result on F8:8.

1785-6.1 November 1998

6-4 Conversion Instructions FRD and TOD, DEG and RAD

Radian (RAD)

Description: 8VH WKH 5$' LQVWUXFWLRQ WR FRQYHUW GHJUHHV 6RXUFH

WR UDGLDQV DQG
RAD
VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH WLPHV π

DEGREES TO RADIANS Table 6.F
Source Updating Arithmetic Status Flags for an RAD Instruction
Destination






Example:

I:012 RAD
]
] DEGREES TO RADIANS
10 Source N7:9
45
Destination F8:10
0.7853982

If input word 12, bit 10 is set, convert the value in N7:9 to radians and store the result on F8:10.

1785-6.1 November 1998

Chapter 7
Bit Modify and Move Instructions
BTD, MOV, MVM
Using Bit Modify and Move 7KH ELW PRGLI DQG PRYH LQVWUXFWLRQV OHW RX PRGLI DQG PRYH ELWV
Instructions 7DEOH $ OLVWV WKH DYDLODEOH PRYH LQVWUXFWLRQV
Table 7.A
Available Bit Modify and Move Instructions


Move bits within a word or between words BTD 7-2

Copy the value in one word to another word MOV 7-3

Copy the desired part of a 16-bit value by MVM 7-4
masking the rest of the value with a mask

7KHVH LQVWUXFWLRQV RSHUDWH RQ ELW LQWHJHU ELQDU RU IORDWLQJ SRLQW
QXPEHUV WR PRYH RU FRS ELWV EHWZHHQ ZRUGV 7KH 090 LQVWUXFWLRQ
XVHV D PDVN WR HLWKHU SDVV RU EORFN VRXUFH GDWD ELWV $ PDVN SDVVHV
GDWD ZKHQ WKH PDVN ELWV DUH VHW

D PDVN EORFNV GDWD ZKHQ WKH
PDVN ELWV DUH UHVHW

7KH PDVN PXVW EH WKH VDPH ZRUG VL]H DV WKH
VRXUFH DQG GHVWLQDWLRQ
:KHQ URXQGLQJ IORDWLQJ SRLQW QXPEHUV GXULQJ D PRYH WR DQ LQWHJHU
ZRUG WKH SURFHVVRU GRHV QRW FRUUHFWO URXQG QXPEHUV OHVV WKDQ ±
HDFK RSHUDQG

7-2 Bit Modify and Move Instructions BTD, MOV, MVM

Bit Distribute (BTD)

Description: 7KH %7' LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW PRYHV XS WR ELWV
RI GDWD ZLWKLQ D ZRUG RU EHWZHHQ ZRUGV 7KH 6RXUFH UHPDLQV
BTD
XQFKDQJHG 7KH LQVWUXFWLRQ ZULWHV RYHU WKH 'HVWLQDWLRQ ZLWK WKH
BIT FIELD DISTRIB
VSHFLILHG ELWV ,I WKH OHQJWK RI WKH ELW ILHOG H[WHQGV EHRQG WKH
Source
Source bit
'HVWLQDWLRQ ZRUG WKH SURFHVVRU GRHV QRW VDYH WKH RYHUIORZ ELWV
Destination 7KHVH RYHUIORZ ELWV DUH ORVW WKH GR QRW ZUDS LQWR WKH QH[W ZRUG
Destination bit
Length 2Q HDFK VFDQ ZKHQ WKH UXQJ WKDW FRQWDLQV WKH %7' LQVWUXFWLRQ LV WUXH
WKH SURFHVVRU PRYHV WKH ELW ILHOG IURP WKH VRXUFH ZRUG WR WKH
GHVWLQDWLRQ ZRUG 7R PRYH GDWD ZLWKLQ D ZRUG HQWHU WKH VDPH DGGUHVV
IRU WKH VRXUFH DQG GHVWLQDWLRQ

Entering Parameters
7R SURJUDP WKH %7' LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ


Source the address of the source word in binary or integer. The source
remains unchanged.

Source bit the number of the bit (lowest bit number) in the source word from
which to start the move.

Destination the address of the destination word in a binary or integer file. The
instruction writes over any data already stored at the destination.

Destination bit the number of the bit (lowest bit number) in the destination word
where the processor starts copying the bits from the source word.

Length the number of bits to be moved.

Example:
Moving Bits Within a Word

BTD
Destination Bit Source Bit
BIT FIELD DISTRIB N70:22/10 N70:22/3
Source N70:22 15 08 07 00
Source bit 3
Destination N70:22 1 0 1 1 0 1 1 0 1 1 0 1 N70:22
Destination bit 10
Length 6

13384

1785-6.1 November 1998

Bit Modify and Move Instructions BTD, MOV, MVM 7-3

Example:
Moving Bits Between Words
BTD Source Bit
N7:020/3
BIT FIELD DISTRIB 15 08 07 00
Source N7:20 0 1 1 1 0 1 1 1 0 1 N7:20
Source bit 3
Destination N7:22
Destination bit 5 Destination Bit
Length 10 N7:022/5
15 08 07 00
0 1 1 1 0 1 1 1 0 1 N7:22

13384

,PSRUWDQW %LWV DUH ORVW LI WKH H[WHQG EHRQG WKH HQG RI WKH
GHVWLQDWLRQ ZRUG WKH ELWV DUH QRW ZUDSSHG WR WKH QH[W
KLJKHU ZRUG

Move (MOV)

Description: 7KH 029 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRSLHV WKH 6RXUFH
DGGUHVV WR D 'HVWLQDWLRQ $V ORQJ DV WKH UXQJ UHPDLQV WUXH WKH
MOV
LQVWUXFWLRQ PRYHV WKH GDWD HDFK VFDQ
MOVE
Source 7DEOH % GHVFULEHV KRZ WKH SURFHVVRU XSGDWHV WKH DULWKPHWLF VWDWXV
Destination IODJV
Table 7.B
Updating Arithmetic Status Flags for a MOV Instruction



Overflow (V) sets if overflow generated during floating
point-to-integer conversion; otherwise resets



Example: 7R SURJUDP WKLV LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK WKH
IROORZLQJ
MOV
MOVE
Source N7:0 Parameter: Definition:
Destination N7:2
source is a program constant or data address from which the instruction
reads an image of the value.
You can also use a symbol, as long as the symbol name is more
than 1 character. The source remains unchanged.

destination the data address to which the instruction writes the result of
the operation. The instruction writes over any data stored at
the destination.

1785-6.1 November 1998


Masked Move (MVM)

Description: 7KH 090 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRSLHV WKH 6RXUFH
WR D 'HVWLQDWLRQ DQG DOORZV SRUWLRQV RI WKH GDWD WR EH PDVNHG $V
MVM
ORQJ DV WKH UXQJ UHPDLQV WUXH WKH LQVWUXFWLRQ PRYHV GDWD HDFK VFDQ
MASKED MOVE
Source RX FDQ XVH WKH 090 LQVWUXFWLRQ WR FRS ,2 LPDJH ELQDU RU
Mask
LQWHJHU YDOXHV )RU H[DPSOH XVH 090 WR H[WUDFW ELW GDWD VXFK DV
Destination
VWDWXV RU FRQWURO ELWV IURP DQ HOHPHQW WKDW FRQWDLQV ELW DQG ZRUG GDWD
7DEOH GHVFULEHV KRZ WKH SURFHVVRU XSGDWHV WKH DULWKPHWLF
VWDWXV IODJV
Table 7.C
Updating Arithmetic Status Flags for a MVM Instruction






Entering Parameters
7R SURJUDP WKLV LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ


Source a program constant or data address from which the instruction reads an
image of the value. The source remains unchanged.

Mask an address or hexadecimal value that specifies which bits to pass or
block.
You must set (1) mask bits to move data. Moved data overwrites
destination data. Bits at the destination that correspond to zeros in the
mask are not altered.
If you want the ladder program to change the mask value, store the mask
at a data address. When you enter a value in this field, make sure that
you include the data type, file number and word number. For example,
type B100:0.
Otherwise, enter a hexadecimal value for a constant mask value. For
example, type F800.

Destination the data address to which the instruction writes the result of the
operation. The instruction writes over any data stored at the destination.

Example:

1785-6.1 November 1998

Bit Modify and Move Instructions BTD, MOV, MVM 7-5

MVM Destination
MASKED MOVE N7:2 Before Move
Source N7:0
Mask 1111000011110000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Destination N7:2

Source Mask
N7:0 F0F0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

Destination
N7:2 After Move
0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1
13360

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 8
File Instruction Concepts
Concepts of File Operation 7KLV FKDSWHU SUHVHQWV FRQFHSWV RI EORFN RSHUDWLRQ IRU WKH )LOH
$ULWKPHWLF DQG /RJLFDO )$/

LQVWUXFWLRQV
7KH )$/ LQVWUXFWLRQ SHUIRUPV DULWKPHWLF DQG ORJLFDO RSHUDWLRQV RQ
EORFNV RI ZRUGV 7KH )6 LQVWUXFWLRQ SHUIRUPV FRPSDULVRQ
RSHUDWLRQV RQ EORFNV RI ZRUGV )RU VSHFLILF LQIRUPDWLRQ DERXW WKH
)$/ RU )6 LQVWUXFWLRQ VHH FKDSWHU
HDFK RSHUDQG

$SSHQGL[

Entering Parameters RX QHHG WR SURYLGH WKH SURFHVVRU ZLWK WKH IROORZLQJ LQIRUPDWLRQ
FAL ZKHQ RX HQWHU D ILOH LQVWUXFWLRQ
FILE ARITH/LOGICAL EN
Control
Length Parameter: Definition:
DN
Position
Mode Control the address of the control structure in a control type (R) file. The
Destination ER
processor uses this information to run the instruction. See “Using the
Expression
Control Structure” on page 8-2.

Length the number of words in the data block on which the file instruction
operates. Enter any decimal number 1-1000.

Position the current word within the data block that the processor is accessing.
You generally enter a zero to start at the beginning of a block.

Mode the number of file words operated on each time the rung is scanned in
the program. The mode lets you distribute operation on the complete
block of words. Specify one of the following:
• for All mode, type an A
• for Numerical mode, type a decimal number (1-1000)
• for Incremental mode, type an I
For more information about the different modes, see “Choosing Modes of
Block Operation” on page 8-5.

Destination the address where the processor stores the result of the operation. The
instruction converts to the data type specified by the destination address.

Expression contains addresses, program constants, and operators that specify the
source of data and the operations to be performed.
If you enter the index prefix (#) for a destination or expression address,
the processor accepts it as the address of the first word of a block to be
operated upon. The processor assigns and uses the offset value in
module status to process the block address. If you omit the # prefix, the
processor accepts this as the address of a single work to be operated
upon.

1785-6.1 November 1998

8-2 File Instruction Concepts

,PSRUWDQW 0DNH VXUH WKH LQGH[ YDOXH SRVLWLYH RU QHJDWLYH

GRHV
QRW FDXVH WKH LQGH[HG DGGUHVV WR H[FHHG WKH ILOH WSH
ERXQGDU 7KH SURFHVVRU GRHV QRW FKHFN WKLV XQOHVV RX
XVH DQ LQGH[HG LQGLUHFW DGGUHVV RU H[FHHG WKH GDWD WDEOH
DUHD RI PHPRU ,I WKH LQGH[HG DGGUHVV H[FHHGV WKH GDWD
WDEOH DUHD WKH SURFHVVRU LQLWLDWHV D UXQWLPH HUURU DQG
VHWV D PDMRU IDXOW 7KH SURFHVVRU GRHV QRW FKHFN WR VHH
ZKHWKHU WKH LQGH[HG DGGUHVV FURVVHV ILOH WSHV VXFK DV
1 WR )

$77(17,21 ,QVWUXFWLRQV ZLWK D VLJQ LQ DQ DGGUHVV
PDQLSXODWH WKH RIIVHW YDOXH VWRUHG DW 6 0DNH VXUH
RX PRQLWRU RU ORDG WKH RIIVHW YDOXH RX ZDQW SULRU WR
XVLQJ DQ LQGH[HG DGGUHVV 2WKHUZLVH XQSUHGLFWDEOH
PDFKLQH RSHUDWLRQ FRXOG RFFXU ZLWK SRVVLEOH GDPDJH WR
HTXLSPHQW DQGRU LQMXU WR SHUVRQQHO

)RU PRUH LQIRUPDWLRQ RQ LQGH[HG DGGUHVVLQJ VHH WKH FKDSWHU RQ
DGGUHVVLQJ GDWD WDEOH ILOHV LQ RXU VRIWZDUH XVHU PDQXDO

Using the Control Structure 7KH FRQWURO VWUXFWXUH ILOH WSH 5

FRQWUROV WKH RSHUDWLRQ RI WKH ILOH
LQVWUXFWLRQ 6LPLODU WR D FRXQWHU LW FRQWUROV WKH ILOH E OHQJWK SRVLWLRQ
DQG VWDWXV DQG FRQWURO ELWV )LJXUH

RX HQWHU WKH FRQWURO
VWUXFWXUH DGGUHVV IRU H[DPSOH 5

LQ WKH RQWURO ILHOG ZKHQ RX
SURJUDP D )$/ RU )6 LQVWUXFWLRQ
Figure 8.1
Example Control File R6:0
Memory Control Structure Address

Status
Length R6:0
Position
Status
Length R6:1
Position
Status
Length R6:2

Position
13370

$77(17,21 'R QRW XVH WKH VDPH FRQWURO DGGUHVV IRU
PRUH WKDQ RQH LQVWUXFWLRQ 'XSOLFDWLRQ RI D FRQWURO
DGGUHVV FRXOG UHVXOW LQ XQSUHGLFWDEOH RSHUDWLRQ SRVVLEO
FDXVLQJ GDPDJH WR HTXLSPHQW DQGRU LQMXU WR SHUVRQQHO

1785-6.1 November 1998

File Instruction Concepts 8-3

7KH FRQWURO VWUXFWXUH VWRUHV WKH IROORZLQJ LQIRUPDWLRQ
‡ 6WDWXV ELWV
‡ /HQJWK /(1

RI WKH ZRUGV WKDW WKH SURFHVVRU LV RSHUDWLQJ RQ
7KH )$/ LQVWUXFWLRQ DQG )6 LQVWUXFWLRQ HDFK KDV LWV RZQ VHW RI
VWDWXV ELWV 6HH FKDSWHU IRU WKH )$/ RU )6 LQVWUXFWLRQ IRU D
GHVFULSWLRQ RI WKHVH VWDWXV ELWV

Manipulating File Data 7SLFDO GDWD PDQLSXODWLRQV ZLWK ILOH LQVWUXFWLRQV LQFOXGH
‡ RSLQJ GDWD IURP D
‡ VRXUFH ZRUG WR D GHVWLQDWLRQ EORFN
‡ VRXUFH EORFN WR D GHVWLQDWLRQ EORFN
‡ VRXUFH EORFN WR D GHVWLQDWLRQ ZRUG
‡ 2SHUDWLQJ RQ GDWD IURP PXOWLSOH VRXUFHV VXFK DV
‡ VRXUFH ZRUGV
‡ VRXUFH EORFNV
‡ 6WRULQJ WKH UHVXOW LQ D
‡ GHVWLQDWLRQ EORFN
‡ GHVWLQDWLRQ ZRUG
7KH SUHIL[ IRU D GHVWLQDWLRQ RU H[SUHVVLRQ DGGUHVV HVWDEOLVKHV LW DV
WKH DGGUHVV RI WKH ILUVW ZRUG RI D EORFN WR EH RSHUDWHG XSRQ 7KH
DEVHQFH RI WKH SUHIL[ HVWDEOLVKHV LW DV WKH DGGUHVV RI D VLQJOH ZRUG WR
EH RSHUDWHG XSRQ

FAL
Control R6:5
Length 4
Position 0 DN
Mode ALL
Dest #N28:0 The # prefix for the destination address and the
ER absence of a # prefix for the expression address
Expression N27:3
establish this as a word-to-block operation.
FAL
Control R6:5
Length 4
DN
Position 0
Mode ALL
Dest N28:0 ER The absence of a # prefix for the destination
Expression #N27:3 address and the # prefix for the expression address
establish this as a block-to-word operation.
FAL
Control R6:5
Length 4
DN
Position 0
Mode ALL
Dest #N28:0 ER The # prefix for the destination address and the
Expression #N27:3 # prefix for the expression address establish this
as a block-to-block operation.

1785-6.1 November 1998


7KH IROORZLQJ H[DPSOH VKRZV JHQHULF GDWD PDQLSXODWLRQV XVHG ZLWK
ILOH LQVWUXFWLRQV ( H[SUHVVLRQ ' GHVWLQDWLRQ [ RSHUDWLRQ

Moving Data
E D E D E D

Word to Block Block to Block Block to Word

Operating on Data
E D E D

Block x Word = Result Word x Block = Result

E D E D

Word x Word = Result Block x Block = Result

E D E D

Word x Block = Result Block x Word = Result

E D

16617a
Block x Block = Result

1785-6.1 November 1998


Choosing Modes of Block 7KH EORFN PRGH WHOOV WKH SURFHVVRU KRZ WR GLVWULEXWH WKH EORFN
Operation RSHUDWLRQ RYHU RQH RU PRUH SURJUDP VFDQV 6HOHFW RQH RI WKH
IROORZLQJ PRGHV

All Mode
,Q WKH $OO PRGH WKH HQWLUH ILOH LV RSHUDWHG RQ EHIRUH FRQWLQXLQJ RQ WR
WKH QH[W UXQJ RI WKH SURJUDP 7SH DQ $ IRU WKH PRGH SDUDPHWHU
ZKHQ RX HQWHU WKH LQVWUXFWLRQ
Word
Data File One Scan
512

14 Word File

525

16639

2SHUDWLRQ EHJLQV ZKHQ WKH UXQJ JRHV IURP QRW WUXH WR WUXH 7KH
SRVLWLRQ 326

YDOXH LQ WKH FRQWURO VWUXFWXUH SRLQWV WR WKH ZRUG LQ WKH
GDWD EORFN WKDW WKH LQVWUXFWLRQ LV FXUUHQWO XVLQJ 2SHUDWLRQ VWRSV
ZKHQ WKH IXQFWLRQ FRPSOHWHV RU ZKHQ WKH SURFHVVRU GHWHFWV DQ HUURU
7KH IROORZLQJ WLPLQJ GLDJUDP VKRZV WKH UHODWLRQVKLS EHWZHHQ VWDWXV
ELWV DQG LQVWUXFWLRQ RSHUDWLRQ :KHQ WKH LQVWUXFWLRQ H[HFXWLRQ LV
FRPSOHWH WKH GRQH ELW LV WXUQHG RQ 7KH GRQH DQG HQDEOH ELWV DUH QRW
WXUQHG RII DQG WKH SRVLWLRQ YDOXH LV QRW ]HURHG XQWLO WKH UXQJ
FRQGLWLRQV DUH QR ORQJHU WUXH 2QO WKHQ FDQ DQRWKHU RSHUDWLRQ EH
WULJJHUHG E D QRWWUXHWRWUXH WUDQVLWLRQ RI WKH UXQJ FRQGLWLRQV
One
program
scan

Condition of rung that
controls file/block instruction

Enable (bit 15)

Done (bit 13)
The processor turns
off status bits and
zeroes position value.
Execution of the instruction
16640
Operation complete

1785-6.1 November 1998


Numerical Mode
1XPHULFDO PRGH GLVWULEXWHV WKH ILOH RSHUDWLRQ RYHU D QXPEHU RI
SURJUDP VFDQV 7R VHOHFW WKH QXPHULFDO PRGH HQWHU WKH QXPEHU RI
ZRUGV SHU VFDQ

IRU WKH PRGH SDUDPHWHU ZKHQ RX HQWHU WKH
ILOH LQVWUXFWLRQ 7KH QXPEHU RI ZRUGV RX HQWHU PXVW EH OHVV WKDQ RU
HTXDO WR WKH ILOH OHQJWK
([HFXWLRQ LV WULJJHUHG ZKHQ WKH UXQJ FRQGLWLRQV JR IURP QRW WUXH
WR WUXH 2QFH WULJJHUHG WKH LQVWUXFWLRQ LV H[HFXWHG FRQWLQXDOO HDFK
WLPH WKH UXQJ LV VFDQQHG LQ WKH SURJUDP IRU WKH QXPEHU RI VFDQV
QHFHVVDU WR FRPSOHWH RSHUDWLRQ RQ WKH HQWLUH ILOH 2QFH WULJJHUHG
UXQJ ORJLF FDQ FKDQJH UHSHDWHGO ZLWKRXW LQWHUUXSWLQJ H[HFXWLRQ RI
WKH LQVWUXFWLRQ
(DFK WLPH WKH UXQJ LV VFDQQHG WKH LQVWUXFWLRQ RSHUDWHV RQ WKH QXPEHU
RI ZRUGV HTXDO WR WKH UDWH RX HQWHUHG IRU WKH PRGH YDOXH XQWLO LW KDV
RSHUDWHG RQ WKH QXPEHU RI ZRUGV RX VSHFLILHG E WKH OHQJWK YDOXH ,Q
WKH ODVW VFDQ RI WKH UXQJ WKH SURFHVVRU PD RSHUDWH RQ OHVV WKDQ WKH
QXPEHU RI ZRUGV RX HQWHUHG

File
Word
Scan #1
512

5 words
Scan #1 516 Scan #2
517
14-Word Block 5 words

Scan #2 521 Scan #3
522
Remaining
4 words
Scan #3 525

16641

,PSRUWDQW $YRLG XVLQJ WKH UHVXOWV RI D ILOH LQVWUXFWLRQ RSHUDWLQJ LQ
QXPHULF PRGH XQWLO WKH GRQH ELW LV VHW EHFDXVH WKH GDWD
ZLOO EH LQFRPSOHWH
ELWV DQG LQVWUXFWLRQ RSHUDWLRQ
Rung is true at completion Rung is not true at completion
Multiple program
scans Multiple program
scans
controls file instruction

Enable (bit 15)

Done (bit 13)

Execution of instruction

Operation complete The processor turns off Operation complete The processor
enable and done bit and turns off done
zeroes position value. bit and zeroes
position value.
16642

1785-6.1 November 1998


:KHQ WKH LQVWUXFWLRQ H[HFXWLRQ LV FRPSOHWH WKH GRQH ELW LV WXUQHG RQ
,I WKH UXQJ LV WUXH DW FRPSOHWLRQ WKH HQDEOH ELW DQG GRQH ELW DUH QRW
WXUQHG RII XQWLO WKH UXQJ LV QR ORQJHU WUXH :KHQ WKH UXQJ LV QR ORQJHU
WUXH WKHVH ELWV DUH WXUQHG RII DQG WKH SRVLWLRQ YDOXH LV ]HURHG
,I WKH UXQJ LV QRW WUXH DW FRPSOHWLRQ WKH HQDEOH ELW LV WXUQHG RII
LPPHGLDWHO DQG RQH VFDQ DIWHU WKH HQDEOH ELW LV WXUQHG RII WKH GRQH
ELW LV WXUQHG RII DQG WKH SRVLWLRQ YDOXH LV ]HURHG
2QO DIWHU WKH HQDEOH DQG GRQH ELWV DUH WXUQHG RII FDQ DQRWKHU
RSHUDWLRQ EH WULJJHUHG E D QRWWUXHWRWUXH WUDQVLWLRQ RI WKH
UXQJ FRQGLWLRQV

Incremental Mode
,QFUHPHQWDO PRGH PDQLSXODWHV RQH ZRUG RI WKH ILOH HDFK WLPH WKH
UXQJ JRHV IURP QRW WUXH WR WUXH 7SH DQ , IRU WKH PRGH SDUDPHWHU
ZKHQ RX HQWHU WKH LQVWUXFWLRQ
File
Word
File Word
1-Word Operation 1st Rung Enable
Word #0 512
1-Word Operation 2nd Rung Enable
Word #1 513
1-Word Operation 3rd Rung Enable
Word #2 514
Word #3 515
Word File

Word #12 524
1-Word Operation 14th Rung Enable
Word #13 (last word) 525

16

ELWV DQG LQVWUXFWLRQ RSHUDWLRQ
One or more
program
scans
controls file instruction

Enable (bit 15)

Done (bit 13)

Execution of instruction

The processor The processor turns
turns off enable bit. off status bits and
Operation complete zeroes position value.
16644

1785-6.1 November 1998


([HFXWLRQ RFFXUV RQO LQ D SURJUDP VFDQ LQ ZKLFK WKH UXQJ JRHV IURP
QRW WUXH WR WUXH (DFK WLPH WKLV GRHV RFFXU RQO RQH ZRUG RI WKH ILOH LV
RSHUDWHG RQ 7KH HQDEOH ELW LV RQ ZKHQ UXQJ ORJLF LV WUXH 7KH GRQH ELW
LV WXUQHG RQ ZKHQ WKH ODVW ZRUG LQ WKH ILOH KDV EHHQ RSHUDWHG RQ :KHQ
WKH ODVW ZRUG LQ WKH ILOH KDV EHHQ RSHUDWHG RQ DQG WKH UXQJ JRHV IURP
WUXH WR QRW WUXH WKH HQDEOH DQG GRQH ELWV DUH WXUQHG RII DQG WKH
SRVLWLRQ YDOXH LV ]HURHG ,I WKH UXQJ UHPDLQV WUXH IRU PRUH WKDQ RQH
SURJUDP VFDQ WKH ILOH LQVWUXFWLRQ LV QRW H[HFXWHG LQ VXEVHTXHQW VFDQV
DIWHU WKH WUDQVLWLRQ
,PSRUWDQW ,I RX DUH RSHUDWLQJ RQ DQ HQWLUH ILOH DYRLG XVLQJ WKH
UHVXOWV RI D ILOHEORFN LQVWUXFWLRQ XVLQJ LQFUHPHQWDO
PRGH XQWLO WKH GRQH ELW LV RQ WKH GDWD ZLOO
EH LQFRPSOHWH

Special Case, Numerical Mode with Words Per Scan = 1
7KH GLIIHUHQFH EHWZHHQ QXPHULFDO PRGH ZLWK D UDWH RI ZRUG SHU
VFDQ DQG LQFUHPHQWDO PRGH LV
‡ 1XPHULFDO PRGH ZLWK DQ QXPEHU RI ZRUGV SHU VFDQ RQO RQH
QRWWUXHWRWUXH UXQJ WUDQVLWLRQ LV UHTXLUHG IRU FRQWLQXDO H[HFXWLRQ
RI WKH LQVWUXFWLRQ XQWLO RSHUDWLRQ LV FRPSOHWH RQ WKH HQWLUH ILOH
‡ ,QFUHPHQWDO PRGH UHTXLUHV D QRWWUXHWRWUXH UXQJ WUDQVLWLRQ IRU
HDFK ZRUG LQ WKH ILOH

1785-6.1 November 1998

Chapter 9
File Instructions FAL, FSC, COP, FLL
Using File Instructions 7KH ILOH LQVWUXFWLRQV SHUIRUP RSHUDWLRQV RQ ILOH GDWD DQG FRPSDUH ILOH
GDWD 7DEOH $ OLVWV WKH DYDLODEOH ILOH LQVWUXFWLRQV
Table 9.A
Available File Instructions

Found on
If You Want to: Use this Operation:
Page:

Perform arithmetic, logic, shift, and FAL 9-2
function operations on file data

Perform search and compare operations on FSC 9-14
file data

Copy the contents of a file into another file COP 9-19

Fill a file with specific values FLL 9-20

,I RX KDYH QRW DOUHDG GRQH VR UHYLHZ WKH EDVLF FRQFHSWV RI ILOH
RSHUDWLRQ LQ WKH SUHYLRXV FKDSWHU )RU PRUH LQIRUPDWLRQ RQ XVLQJ
LQGH[HG DGGUHVVHV VHH RXU VRIWZDUH XVHU PDQXDO
HDFK RSHUDQG

9-2 File Instructions FAL, FSC, COP, FLL

File Arithmetic and Logic (FAL) 7KH )$/ LQVWUXFWLRQ SHUIRUPV FRS DULWKPHWLF ORJLF DQG IXQFWLRQ
RSHUDWLRQV RQ WKH GDWD VWRUHG LQ ILOHV 7KH )$/ LQVWUXFWLRQ SHUIRUPV
WKH VDPH RSHUDWLRQV DV WKH 37 LQVWUXFWLRQ 7KH GLIIHUHQFH LV WKDW WKH
)$/ LQVWUXFWLRQ SHUIRUPV RSHUDWLRQV RQ PXOWLSOH ZRUGV ZKLOH WKH
37 LQVWUXFWLRQ KDQGOHV VLQJOH ZRUGV

Description: 7KH )$/ LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW SHUIRUPV WKH
FAL RSHUDWLRQV GHILQHG E VRXUFH DGGUHVVHV DQG RSHUDWRUV RX ZULWH
FILE ARITH/LOGICAL EN LQ WKH H[SUHVVLRQ 7KH LQVWUXFWLRQ ZULWHV WKH UHVXOWV LQWR D
Control
Length GHVWLQDWLRQ DGGUHVV
DN
Position
Mode
ER
6HOHFW KRZ WKH SURFHVVRU GLVWULEXWHV WKH RSHUDWLRQ RYHU RQH RU PRUH
Destination
Expression SURJUDP VFDQV E RXU VHOHFWLRQ RI LQVWUXFWLRQ PRGH )RU PRUH
LQIRUPDWLRQ DERXW PRGHV RI ILOH RSHUDWLRQ VHH FKDSWHU
7KH )$/ LQVWUXFWLRQ DXWRPDWLFDOO FRQYHUWV WKH GDWD WSH DW WKH
VRXUFH DGGUHVVHV WR WKH GDWD WSH WKDW RX VSHFLI LQ WKH GHVWLQDWLRQ
DGGUHVV
RX FDQ XVH WKLV LQVWUXFWLRQ WR SHUIRUP RSHUDWLRQV VXFK DV
‡ ]HUR D ILOH
‡ FRS GDWD IURP RQH ILOH WR DQRWKHU
‡ PDNH DULWKPHWLF RU ORJLF FRPSXWDWLRQV RQ GDWD VWRUHG LQ ILOHV
‡ XQORDG D ILOH RI HUURU FRGHV RQH DW D WLPH IRU GLVSOD

$77(17,21 ,QVWUXFWLRQV ZLWK D VLJQ LQ DQ DGGUHVV
PDQLSXODWH WKH RIIVHW YDOXH VWRUHG DW 6 0DNH VXUH
RX PRQLWRU RU ORDG WKH RIIVHW YDOXH RX ZDQW SULRU WR
XVLQJ DQ LQGH[HG DGGUHVV 2WKHUZLVH XQSUHGLFWDEOH
PDFKLQH RSHUDWLRQ FRXOG RFFXU ZLWK SRVVLEOH GDPDJH WR
HTXLSPHQW DQGRU LQMXU WR SHUVRQQHO

1785-6.1 November 1998

File Instructions FAL, FSC, COP, FLL 9-3

Table 9.B
FAL Operations


Copy none copy from A to B enter source address in the expression enter
destination address in destination

Clear none set a value to zero 0 (enter 0 for the expression)

Arithmetic + add 2+3
2+3+7 (Enhanced PLC-5 processors)

(12 – 5) – 1 (Enhanced PLC-5 processors)

* multiply 5*2
6 * (5 * 2) (Enhanced PLC-5 processors)

| divide 24 | 6
(24 | 6) * 2 (Enhanced PLC-5 processors)

– negate – N7:0


** exponential 10**3
(x to the power of y) (Enhanced PLC-5 processors only)

Bitwise AND bitwise AND D9:3 AND D10:4

OR bitwise OR D9:4 OR D9:5

XOR bitwise exclusive OR D10:10 XOR D10:11

NOT bitwise complement NOT D9:4

Conversion FRD convert from BCD FRD D14:0
to binary

to BCD

1785-6.1 November 1998


Using Status Bits
7R XVH WKH )$/ LQVWUXFWLRQ FRUUHFWO H[DPLQH DQG FRQWURO VWDWXV ELWV
LQ WKH FRQWURO HOHPHQW RX DGGUHVV WKHVH ELWV E PQHPRQLF

This Bit: Is Set:

Enable .EN (bit 15) by a false-to-true rung transition and indicates the instruction is
enabled.
In incremental mode, the .EN bit follows the rung condition.
In numerical and ALL modes, the .EN bit remains set until the
instruction completes its operation, regardless of the rung
condition. The .EN bit is reset when the rung goes false and the
instruction completes its operation.

Done .DN (bit 13) after the instruction has operated on the last set of words.
In numerical mode if the instruction is false at completion, it resets
the .DN bit one program scan after the operation is complete. If
the instruction is true at completion, the .DN bit is reset when the
instruction goes false.

Error .ER (bit 11) when the operation generates an overflow. The instruction stops
until the ladder program resets the .ER bit.
When the processor detects an error, the position value stores the
number of the word that faulted.

:LWK WKH )$/ LQVWUXFWLRQ D PD[LPXP RI FKDUDFWHUV RI WKH
UXQV SURSHUO
ILOH DQG PDNH RXU HGLWV LQ WKH 3 WH[W ILOH 7KHQ LPSRUW WKLV WH[W
ILOH 6HH RXU SURJUDPPLQJ PDQXDO IRU PRUH LQIRUPDWLRQ RQ
LPSRUWLQJH[SRUWLQJ SURFHVVRU PHPRU ILOHV

1785-6.1 November 1998


FAL Copy Operations 7KH )$/ FRS RSHUDWLRQ FRSLHV GDWD
‡ EHWZHHQ ILOHV
‡ IURP D ZRUG WR D ILOH
‡ IURP D ILOH WR D ZRUG
7R FRS GDWD ZLWK WKH )$/ FRS RSHUDWLRQ HQWHU WKH VRXUFH DGGUHVV
RU SURJUDP FRQVWDQW LQ WKH H[SUHVVLRQ DQG WKH GHVWLQDWLRQ DGGUHVV LQ
WKH GHVWLQDWLRQ

File-to-File Copy Example:

FAL File #N27 File #N28
Control R6:5 9732 9732
Element 3 0 Element
Length 4
DN
Position 0 1015 1015
Mode ALL 4 1
Destination #N28:0 ER
2000 2000
Expression #N27:3 2
5
19000 19000
6 3

13366

This Parameter: Tells the Processor:

Control (R6:5) What control structure controls the operation.
This parameter is controlled by the rung condition, the state of
the .EN and .DN bits, and by the mode (incremental, numeric, or
all). It contains the location of the last value written to by the FAL
instruction.
For example, if, in incremental mode, position = 0 and length =
4, the last word written to by the FAL instruction would be word
3 since the instruction starts at location 0.

Length (4) To move four words

Position (0) To start at the source address

Mode (ALL) To execute the length in one program scan

Destination (#N28:0) Where to write the data (the # indicates that the operation is to
be performed on a file)

Expression (#N27:3) Where to read the data (the # indicates that the operation is to
be performed on a file)

:KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU UHDGV IRXU HOHPHQWV RI LQWHJHU
ILOH 1 ZRUG E ZRUG VWDUWLQJ DW HOHPHQW DQG ZULWHV WKH LPDJH WR
LQWHJHU ILOH 1 VWDUWLQJ DW HOHPHQW ,W ZULWHV RYHU DQ GDWD LQ WKH
GHVWLQDWLRQ ILOH

1785-6.1 November 1998


File-to-Word Copy Example:

1st move
FAL
2nd move Word 29:5
FILE ARITH/LOGICAL File # N29:0
EN
Control R6:6
Length 5 Word 0 Word
DN
Position 0
Mode INC 1
Destination N29:5 ER
Expression #N29:0 2

5th move
3
4th move
4 3rd move

13372


Control (R6:6) What control structure controls the operation

Length (5) To copy five words


Mode (incremental) To copy one word each time the rung goes true

Destination (N29:5) Where to write the data (word address)

Expression (#N29:0) Where to read the data (the # indicates that the
operation is to be performed on a file)

:LWK HDFK IDOVHWRWUXH UXQJ WUDQVLWLRQ WKH SURFHVVRU UHDGV RQH
HOHPHQW RI LQWHJHU ILOH 1 VWDUWLQJ DW HOHPHQW DQG ZULWHV WKH LPDJH
LQWR HOHPHQW RI LQWHJHU ILOH 1 7KH LQVWUXFWLRQ ZULWHV RYHU DQ
GDWD LQ WKH GHVWLQDWLRQ
$ ZRUGWRILOH PRYH LV VLPLODU H[FHSW WKDW WKH LQVWUXFWLRQ FRSLHV GDWD
IURP D ZRUG DGGUHVV LQWR D ILOH 7KH ZRUG DGGUHVV FDQ EH LQ WKH VDPH
RU D GLIIHUHQW ILOH

1785-6.1 November 1998


FAL Arithmetic Operations RX FDQ SHUIRUP PXOWLSOH DULWKPHWLF RSHUDWLRQV RQ ILOH GDWD LQWHJHU
RU IORDWLQJ SRLQW

ZLWK WKH IROORZLQJ RSHUDWRUV

Operator: Meaning: Operator: Meaning:

+ add | divide

– subtract – negate

* multiply 0 clear

)RU PRUH LQIRUPDWLRQ DERXW RUGHU RI RSHUDWLRQ VHH FKDSWHU

Upper and Lower Limits
7KH OLPLWV RI GDWD EHLQJ PDWKHPDWLFDOO PDQLSXODWHG GHSHQG
RQ WKH WSH RI ILOH LQ ZKLFK WKH GDWD LV VWRUHG 7KH IROORZLQJ
JXLGHOLQHV DSSO
‡ DOO GDWD H[FHSW IORDWLQJ SRLQW LV VLJQHG LQWHJHU
‡ QHJDWLYH YDOXHV DUH VWRUHG LQ WZR¶V FRPSOHPHQW
‡ IORDWLQJ SRLQW QXPEHUV DUH IRUPDWWHG DV D VXEVHW RI ,(((
VLQJOHSUHFLVLRQ IORDWLQJ SRLQW

Type of File: Range Stored in Word:

bit –32,768 to +32,767 for integers

integer –32,768 to +32,767

timer 0 to +32,767

counter –32,768 to +32,767

control 0 to +32,767

floating point ±1.1754944e–38 to ±3.4028237e+38

$Q HUURU RFFXUV ZKHQ WKH UHVXOW RI DQ RSHUDWLRQ H[FHHGV HLWKHU WKH
ORZHU RU XSSHU OLPLW RI WKH GHVWLQDWLRQ ZRUG LQ ZKLFK LW LV VWRUHG 7KH
RYHUIORZ ELW LV VHW LQ WKH SURFHVVRU¶V VWDWXV ILOH 6

7KH
LQVWUXFWLRQ DOVR VHWV WKH HUURU ELW LQ WKH VWDWXV EWH RI LWV FRQWURO ZRUG

1785-6.1 November 1998


Addition Example: :KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU DGGV YDOXHV LQ ILOH 1
FAL WR WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ WKH QXPHULFDO PRGH
FILE ARITH/LOGICAL EN RI ZRUGV SHU VFDQ 7KH RSHUDWLRQ LV SHUIRUPHG LQ VFDQV DQG WKH
Control
Length
R6:0
100 LQVWUXFWLRQ VHTXHQWLDOO DGGV WKH YDOXHV LQ WKH H[SUHVVLRQ VWRULQJ WKH
DN
Position
Mode
0
10
UHVXOW LQ ILOH 1
Dest #N13:0 ER
Expression
#N11:0 + #N12:0

File # N11:0 + File # N12:0 = File # N13:0

328 0 10 0 338 0
150 1 32 1 182 1
10 2 1 2 11 2
32 3 147 3 179 3
First Scan
0 4 99 4 99 4
45 5 572 5 617 5
1579 6 300 6 1879 6

620 7 42 7 662 7
800 8 19 8 819 8
1243 9 1000 9 2243 9
Second Scan next 10 words
Third Scan next 10 words
Fourth Scan next 10 words
//

//

//
//

//

//
Tenth Scan last 10 elements 99 99 99
13386


Control (R6:0) What control structure controls operation

Length (100) To operate on one hundred elements


Mode (10) To execute the data in 10 words per scan

Destination (#N13:0) Where to write the result data

Expression The operators, program constants, and
(#N11:0 + #N12:0) source addresses

1785-6.1 November 1998


Subtraction Example:

File #N14 -256 = File #N14
FAL
328 0 72 10
Control R6:1
Length 8 1 -106
DN 150 11
Position 0
Mode ALL
ER
10 2 -246 12
Dest #N15:10
Expression 32 3 -224 13
One
#N14:0 - 256
Scan 0 4 -256 14
Required 5
45 -211 15
1579 6 1323 16
620 7 364 17

16655a



Length (8) To operate on eight words


Mode (ALL) To execute the data in one program scan


(#N14:0 – 256) source addresses

:KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU UHDGV HLJKW HOHPHQWV RI
LQWHJHU ILOH 1 ZRUG E ZRUG VWDUWLQJ DW HOHPHQW VXEWUDFWV D
SURJUDP FRQVWDQW

IURP HDFK DQG ZULWHV WKH UHVXOW LQWR
GHVWLQDWLRQ ILOH 1 VWDUWLQJ DW HOHPHQW DOO LQ RQH VFDQ

1785-6.1 November 1998


Multiplication Example:
FAL
Control R6:2
Length 16
DN
Position 0
Mode INC
Dest #F8:16 ER
Expression
#F8:0 * #N17:0

File #F8:0 * File #N17:0 = File #F8:16

First Transition 0.01 0 314 0 3.14 16
Second Transition 0.1 1 315 1 31.5 17
Third Transition 1.0 2 316 2 316 18
Fourth Transition 10.0 3 317 3 3170 19
4 4 20
5 5 21
6 6 22
7 7 23
8 8 24
9 9 25
//

//

//

//
//

//
15 15 31
15290



Length (16) To operate on sixteen words


Mode (incremental) To execute using incremental mode

Destination (#F8:16) Where to write the result data

(#F8:0 * #N17:0) source addresses

:KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU PXOWLSOLHV YDOXHV LQ ILOH
) E WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ LQFUHPHQWDO
PRGH 2QH PXOWLSOLFDWLRQ LV SHUIRUPHG IRU HDFK IDOVH WR WUXH
WUDQVLWLRQ 7KH RSHUDWLRQ UHTXLUHV WUDQVLWLRQV VWRULQJ WKH UHVXOW LQ
ILOH )

1785-6.1 November 1998


Division Example:
FAL
Control R6:2
Length 16
DN
Position 0
Mode INC
Expression
#N11:0 | #N12:0

File N11:0 | File N12:0 = File N13:0
Word Word Word
First Transition 60 0 12 0 5 0
Second Transition 175 1 5 1 35 1
Third Transition 1128 2 8 2 141 2

Fourth Transition 45 3 9 3 5 3
4 4 4
5 5 5
6 6 6
7 7 7

8 8 8
9 9 9
//

//

//

//
//

//
15 15 15
17955



Length (16) To operate on sixteen words


Mode (incremental) To execute using incremental mode


Expression The operators and source addresses
(#N11:0 | #N12:0)

:KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU VWDUWV WR GLYLGH YDOXHV
VWDUWLQJ DW 1 E WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ
LQFUHPHQWDO PRGH 2QH GLYLVLRQ LV SHUIRUPHG IRU HDFK WUDQVLWLRQ WR
WUXH 7KH RSHUDWLRQ UHTXLUHV WUDQVLWLRQV VWRULQJ WKH UHVXOW LQ D
ZRUG ILOH VWDUWLQJ DW 1

1785-6.1 November 1998


File Square Root Example: :KHQ UXQJ FRQGLWLRQV JR WUXH WKH LQVWUXFWLRQ REWDLQV WKH SRVLWLYH
FAL VTXDUH URRW RI WKH YDOXH DW WKH VRXUFH 7KH UDWH LV GHWHUPLQHG E WKH
FILE ARITH/LOGICAL EN PRGH RX VHOHFW 7KH UHVXOW RI HDFK VTXDUH URRW RSHUDWLRQ LV VWRUHG LQ
Control
Length
R6:4
64 DN WKH FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ RQH ZRUG DW D WLPH
Position 0
Mode
Destination
4
#N23:4 ER 7KH SURFHVVRU WDNHV WKH VTXDUH URRW RI WKH DEVROXWH YDOXH LI WKH VLJQ
Expression LV QHJDWLYH WKH SURFHVVRU GLVUHJDUGV WKH VLJQ

SQR #N22:25



Length (64) To take the square root of 64 words


Mode (4) To operate on 4 words each scan


Expression (SQR #N22:25) The operator and source address

$IWHU UXQJ JRHV WUXH WKH VTXDUH URRW RI WKH ILUVW ZRUGV LQ WKH ILOH
EHJLQQLQJ DW 1 LV FDOFXODWHG DQG WKH UHVXOW LV ZULWWHQ LQ WKH
GHVWLQDWLRQ ILOH EHJLQQLQJ DW 1 (YHU WLPH WKH UXQJ LV VFDQQHG
WKHUHDIWHU WKH QH[W IRXU ZRUGV DUH FDOFXODWHG DQG WKH UHVXOW ZULWWHQ
WR WKH GHVWLQDWLRQ ILOH 7KH SURFHVVRU UHTXLUHV D WRWDO RI VFDQV
OHQJWK PRGH

WR FRPSOHWH WKH LQVWUXFWLRQ

FAL Logic Operations 3HUIRUP PXOWLSOH ORJLF RSHUDWLRQV RQ ELQDU ILOH GDWD ZLWK WKH
IROORZLQJ ELWZLVH ORJLF RSHUDWRUV
‡ $1'
‡ 25
‡ ;25
‡ 127
7R SHUIRUP PXOWLSOH ORJLF RSHUDWLRQV RX HQWHU WKH RSHUDWRUV VRXUFH
DGGUHVVHV RU SURJUDP FRQVWDQWV LQ WKH H[SUHVVLRQ DQG WKH UHVXOW
DGGUHVV LQ WKH GHVWLQDWLRQ

1785-6.1 November 1998


Logical OR Example:
FAL
Control R6:4
Length 6 DN
Position 0
Mode 2
Destination #B5:24 ER
Expression
#I:000 OR #B3:6

File I:000 Word or File B3 Word = File B5 Word
0000000000000000 0 1010101010101010 6 1010101010101010 24
First Scan
1111111111111111 1 1111111100000000 7 1111111111111111 25
1111000011110000 2 0000000000000000 8 1111000011110000 26
Second Scan
1010101010101010 3 1100110011001100 9 1110111011101110 27
4 10 28
Third Scan
5 11 29
16618a



Length (6) To OR 6 words


Mode (2) To move 2 words each scan

Destination (#B5:24) Where to write the result data

Expression The operator(s) and source addresses
(#I:000 OR #B3:6)

$IWHU UXQJ JRHV WUXH WKH SURFHVVRU SHUIRUPV D ORJLFDO RU RSHUDWLRQ RQ
WZR ZRUGV EHJLQQLQJ DW , DQG % 7KH UHVXOW LV ZULWWHQ LQ WKH
GHVWLQDWLRQ ILOH EHJLQQLQJ DW % (YHU WLPH WKH UXQJ LV VFDQQHG
WKHUHDIWHU WKH QH[W WZR ZRUGV DUH FDOFXODWHG DQG WKH UHVXOW ZULWWHQ WR
WKH GHVWLQDWLRQ ILOH 7KH SURFHVVRU UHTXLUHV D WRWDO RI VFDQV
OHQJWK PRGH

WR FRPSOHWH WKH LQVWUXFWLRQ
7KH SURFHVVRU H[HFXWHV ORJLF RSHUDWRUV LQ D SUHGHWHUPLQHG RUGHU )RU
PRUH LQIRUPDWLRQ DERXW RUGHU RI RSHUDWLRQV VHH FKDSWHU

1785-6.1 November 1998


FAL Convert Operations 7KH )$/ LQVWUXFWLRQ FDQ SHUIRUP WKHVH FRQYHUW RSHUDWLRQV
‡ FRQYHUW IURP LQWHJHU WR %' 72'

‡ FRQYHUW IURP %' WR LQWHJHU )5'

Example: Convert to BCD :KHQ UXQJ FRQGLWLRQV JR WR WUXH WKH SURFHVVRU FRQYHUWV WKH YDOXH LQ
FAL WKH VRXUFH IURP LQWHJHU WR %' 7KH UDWH LV GHWHUPLQHG E WKH PRGH
FILE ARITH/LOGICAL EN WKDW RX VHOHFW 7KH UHVXOW RI WKH RSHUDWLRQ LV VWRUHG LQ WKH
Control
Length
R6:2
12
FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ
DN
Position 0
Mode ALL
Expression
TOD #N7:0

Example: Convert from BCD :KHQ UXQJ FRQGLWLRQV JR WR WUXH WKH SURFHVVRU FRQYHUWV WKH YDOXH LQ
WKH VRXUFH IURP %' WR LQWHJHU 7KH UDWH LV GHWHUPLQHG E WKH PRGH
WKDW RX VHOHFW 7KH UHVXOW RI WKH RSHUDWLRQ LV VWRUHG LQ WKH
FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ
,PSRUWDQW RQYHUW %' YDOXHV WR LQWHJHU EHIRUH PDQLSXODWLQJ
WKHP LI RX GR QRW FRQYHUW WKH YDOXHV WKH SURFHVVRU
PDQLSXODWHV WKHP DV LQWHJHU DQG WKHLU %' YDOXH LV ORVW

File Search and Compare (FSC) 7KH )6 LQVWUXFWLRQ SHUIRUPV VHDUFK DQG FRPSDUH RSHUDWLRQV
7KHVH DUH WKH VDPH RSHUDWLRQV DV WKH 03 LQVWUXFWLRQ LQFOXGLQJ
FRPSOH[ H[SUHVVLRQV (QKDQFHG 3/ SURFHVVRUV RQO

7KH
GLIIHUHQFH LV WKDW WKH )6 LQVWUXFWLRQ SHUIRUPV ORJLFDO RSHUDWLRQV RQ
ILOHV ZKLOH WKH 03 LQVWUXFWLRQ RSHUDWHV RQ D VLQJOH ZRUG $OVR WKH
)6 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ ZKLOH WKH 03 LQVWUXFWLRQ LV
DQ LQSXW LQVWUXFWLRQ

Description: 7KH )6 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRPSDUHV YDOXHV LQ
FSC
VRXUFH ILOHV ZRUG E ZRUG IRU WKH ORJLFDO RSHUDWLRQV RX VSHFLI LQ
FILE SEARCH/COMPAR EN
WKH H[SUHVVLRQ :KHQ WKH SURFHVVRU ILQGV WKH VSHFLILHG FRPSDULVRQ LV
Control WUXH LW VHWV WKH IRXQG ELW )' DQG UHFRUGV WKH SRVLWLRQ 326 ZKHUH WKH
Length
Position
DN WUXH FRPSDULVRQ ZDV IRXQG 7KH LQKLELW ELW ,1 LV VHW WR SUHYHQW DQ
Mode IXUWKHU VHDUFKLQJ RI WKH ILOHV
Expression ER

RXU ODGGHU SURJUDP PXVW H[DPLQH WKH IRXQG ELW )' DQG WKH SRVLWLRQ
326 WR WDNH DSSURSULDWH DFWLRQ 5HVHW WKH LQKLELW ELW ,1 VR WKH
LQVWUXFWLRQ FDQ FRQWLQXH
6HOHFW KRZ WKH SURFHVVRU GLVWULEXWHV WKH RSHUDWLRQ RYHU RQH RU PRUH
SURJUDP VFDQV E RXU VHOHFWLRQ RI LQVWUXFWLRQ PRGH )RU PRUH
LQIRUPDWLRQ DERXW PRGHV RI ILOH RSHUDWLRQ VHH FKDSWHU
8VH WKLV LQVWUXFWLRQ WR SHUIRUP RSHUDWLRQV VXFK DV
‡ VHW KLJK DQG ORZ SURFHVV DODUPV IRU PXOWLSOH DQDORJ LQSXWV
‡ FRPSDUH EDWFK YDULDEOHV DJDLQVW D UHIHUHQFH ILOH EHIRUH VWDUWLQJ D
EDWFK RSHUDWLRQ

1785-6.1 November 1998


Using Status Bits
7R XVH WKH )6 LQVWUXFWLRQ FRUUHFWO RXU ODGGHU SURJUDP PXVW
H[DPLQH DQG FRQWURO VWDWXV ELWV LQ WKH FRQWURO VWUXFWXUH RX PXVW
DGGUHVV WKHVH ELWV E PQHPRQLF

This Bit: Is Set:

Enable .EN (bit 15) by a false-to-true rung transition and indicates the instruction
is enabled.
In incremental mode this bit follows the rung condition. In
Numerical and All modes, this bit remains set until the instruction
completes its operation, regardless of the rung condition. The .EN
bit is reset when rung conditions go false, but only after the
instruction has set the .DN bit.

Done .DN (bit 13) after the instruction has operated on the last set of words.
In numerical mode if the instruction is false at completion, it
resets the .DN bit one program scan after the operation is
complete. If the instruction is true at completion, the .DN bit is
reset when the instruction goes false.

Error .ER (bit 11) when the operation generates an overflow. The instruction stops
until the ladder program resets this bit.
When the processor detects an error, the position value stores
the number of the element that faulted.

Inhibit .IN (bit 9) when the processor detects a true comparison.
Your ladder program must reset this bit to continue the search
after taking an action initiated by examining the .FD bit. The
ladder program must reset this bit to continue operation.

Found .FD (bit 8) when the processor detects a true comparison. The processor
stops the search and also sets the inhibit .IN bit. The .FD bit is the
output of the FSC instruction.

:LWK WKH )6 LQVWUXFWLRQ D PD[LPXP RI FKDUDFWHUV RI WKH
UXQV SURSHUO
ILOH DQG PDNH RXU HGLWV LQ WKH 3 WH[W ILOH 7KHQ LPSRUW WKLV WH[W
ILOH 6HH RXU SURJUDPPLQJ PDQXDO IRU PRUH LQIRUPDWLRQ RQ
LPSRUWLQJH[SRUWLQJ SURFHVVRU PHPRU ILOHV

1785-6.1 November 1998


7KH IROORZLQJ WLPLQJ GLDJUDP IRU $OO PRGH VKRZV UHODWLRQVKLSV
EHWZHHQ VWDWXV ELWV DQG LQVWUXFWLRQ H[HFXWLRQ ZKHQ WKH LQVWUXFWLRQ
ILQGV WZR WUXH FRQGLWLRQV

Scan Markers

Only
1 Scan

Rung Condition

Enable Bit (.EN)

Done Bit (.DN)

Instruction Execution

Inhibit (.IN) and Found (.FD) Bit

Comparison Found

Ladder Program 16656
Resets Inhibit (.IN) Bit

)RU PRUH LQIRUPDWLRQ DERXW KRZ WKH )6 LQVWUXFWLRQ UHVSRQGV ZKHQ
LW ILQGV QR WUXH FRPSDULVRQV VHH WKH WLPLQJ GLDJUDPV LQ FKDSWHU

1785-6.1 November 1998


FSC Search and Compare 7KH )6 LQVWUXFWLRQ SHUIRUPV WKHVH FRPSDULVRQV RQ ILOH GDWD
Operations DFFRUGLQJ WR KRZ RX VSHFLI WKHP LQ WKH ([SUHVVLRQ RPSOH[
H[SUHVVLRQV DUH YDOLG LQ (QKDQFHG 3/ SURFHVVRUV RQO

Comparison: Example Expression:

Search Equal #N50:0 = #N51:0

Search Not Equal #N52:0 N52:11

Search Less Than #B3:100 #N53:0

Search Less Than or Equal #F60:0 = F60:12

Search Greater Than #N54:0 256

Search Greater Than or Equal F60:10 = #N61:0

Data Conversion
7KH SURFHVVRU FRPSDUHV ILOHV RI GLIIHUHQW GDWD WSHV E LQWHUQDOO
FRQYHUWLQJ GDWD LQWR LWV ELQDU HTXLYDOHQW EHIRUH SHUIRUPLQJ WKH
FRPSDULVRQ 7KH SURFHVVRU WUHDWV WKH IROORZLQJ GDWD WSHV DV LQWHJHU
WLPHU VWDWXV ELW FRXQWHU LQSXW $6,, FRQWURO RXWSXW %'
,PSRUWDQW :KHQ RX FRPSDUH IORDWLQJ SRLQW DQG LQWHJHU YDOXHV LQ
WKH )6 LQVWUXFWLRQ OLPLW WKH FRPSDULVRQV WR ³OHVV WKDQ
RU HTXDO´ DQG ³JUHDWHU WKDQ RU HTXDO´

,PSRUWDQW 8VH $6,, DQG %' IRU GLVSOD RQO DQG QRW DV YDOXHV
6LQFH WKH SURFHVVRU LQWHUSUHWV WKHP DV LQWHJHU WKH PD
ORVH WKHLU PHDQLQJ LI RX HQWHU WKHP DV YDOXHV

)RU WKH RUGHU LQ ZKLFK WKH LQVWUXFWLRQ SHUIRUPV ORJLFDO RSHUDWLRQV VHH
WKH VHFWLRQ ³'HWHUPLQLQJ WKH 2UGHU RI 2SHUDWLRQ´ LQ FKDSWHU

File Search Operation
:KHQ WKH UXQJ FRQGLWLRQ JRHV WR WUXH WKH GHVLUHG FRPSDULVRQ LV
SHUIRUPHG RQ GDWD DGGUHVVHG LQ WKH H[SUHVVLRQ :RUGV DUH FRPSDUHG
LQ DVFHQGLQJ RUGHU VWDUWLQJ DW WKH EHJLQQLQJ 7KH UDWH LV GHWHUPLQHG
E WKH PRGH RI RSHUDWLRQ WKDW RX VSHFLI
7KH '1 ELW ELW

LV VHW DIWHU WKH SURFHVVRU KDV FRPSDUHG WKH ODVW
SDLU ,I WKH UXQJ LV WUXH DW FRPSOHWLRQ WKH '1 ELW LV WXUQHG RII ZKHQ
WKH UXQJ LV QR ORQJHU WUXH ,Q QXPHULFDO PRGH KRZHYHU LI WKH UXQJ LV
QRW WUXH DW FRPSOHWLRQ WKH '1 ELW VWDV RQ RQH SURJUDP VFDQ DIWHU
WKH RSHUDWLRQ LV FRPSOHWH

1785-6.1 November 1998


Example of Search Not Equal:
FSC
FILE SEARCH/COMPARE EN
Control R6:0
Length 90
DN
Position 0
Mode 10
Expression ER
#B4:0 #B5:0

File B4 Word File B5 Word
0000000100000000(100) 0 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 (1 0 0 ) 0
0000000000000001(1) 1 0000000000000001(1) 1
First scan 0000000000000010(2) 2 0000000000000010(2) 2
0000000000000110(6) 3 0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 ) 3 Processor stops and
0000000000000111(7) 0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 ) sets the found and
4 4
inhibit bits. To continue,
the program must reset
the inhibit bit.
10 10
Second scan
Next 10 words Next 10 words
Next 10 words Next 10 words

Ninth scan
Last 10 words Last 10 words
89 89
16620a



Length (90) To search through 90 words

Position (0) To start at source addresses

Mode (10) To search 10 words per program scan

Expression The comparison to perform and the source addresses
(#B4:0 #B5:0)

:KHQ D UXQJ FRQWDLQLQJ WKH )6 LQVWUXFWLRQ JRHV WR WUXH WKH
SURFHVVRU SHUIRUPV WKH QRWHTXDOWR FRPSDULVRQ EHWZHHQ ZRUGV
VWDUWLQJ DW % DQG % 7KH QXPEHU RI ZRUGV FRPSDUHG SHU
SURJUDP VFDQ LQ WKLV H[DPSOH

LV GHWHUPLQHG E WKH PRGH
RX VHOHFW
:KHQ WKH SURFHVVRU ILQGV WKDW FRUUHVSRQGLQJ VRXUFH ZRUGV DUH QRW
HTXDO ZRUGV % DQG % LQ WKLV H[DPSOH

WKH SURFHVVRU VWRSV WKH
VHDUFK DQG WXUQV RQ WKH IRXQG )' DQG LQKLELW ,1 ELWV VR RXU ODGGHU
SURJUDP FDQ WDNH DSSURSULDWH DFWLRQ 7R FRQWLQXH WKH VHDUFK
FRPSDULVRQ RX PXVW WXUQ RII WKH ,1 ELW

1785-6.1 November 1998


File Copy (COP)

Description: 7KH 23 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRSLHV WKH YDOXHV LQ
COP WKH VRXUFH ILOH LQWR WKH GHVWLQDWLRQ ILOH 7KH VRXUFH UHPDLQV
COPY FILE XQFKDQJHG 7KH 23 LQVWUXFWLRQ GRHV QRW XVH VWDWXV ELWV ,I RX QHHG
Source DQ HQDEOH ELW SURJUDP D SDUDOOHO RXWSXW WKDW XVHV D VWRUDJH DGGUHVV
Destination
Length 7KH 23 LQVWUXFWLRQ GRHV QRW ZULWH RYHU ILOH ERXQGDULHV $Q
RYHUIORZ GDWD LV ORVW $OVR QR GDWD FRQYHUVLRQ RFFXUV LI WKH VRXUFH
DQG GHVWLQDWLRQ ILOHV DUH GLIIHUHQW GDWD WSHV XVH ILOHV RI WKH VDPH GDWD
WSH IRU HDFK
,I WKH GHVWLQDWLRQ LV LQ D ILOH RI ZRUGV VXFK DV DQ LQWHJHU ILOH

RX
VSHFLI WKH OHQJWK LQ ZRUGV ,I WKH GHVWLQDWLRQ LV LQ D ILOH RI VWUXFWXUHV
VXFK DV D FRXQWHU ILOH

RX VSHFLI WKH OHQJWK LQ VWUXFWXUHV )RU
H[DPSOH LI WKH VRXUFH LV LQ DQ LQWHJHU ILOH WKH GHVWLQDWLRQ LV LQ D
FRXQWHU ILOH DQG RX VSHFLI D OHQJWK RI LQWHJHU ZRUGV DUH
FRSLHG LQWR FRXQWHU VWUXFWXUHV

Entering Parameters
7R SURJUDP WKH 23 LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ


Source the starting address of the source file. The source remains unchanged.

Destination address of the destination file. The instruction writes over any data
already stored at the destination.

Length the number of the words/structures to overwrite in the destination file.

$77(17,21 ,I RX XVH WKH 23 LQVWUXFWLRQ ZLWK DQ
(QKDQFHG 3/ SURFHVVRU VHULHV $' ILOH ERXQGDULHV
PLJKW EHFRPH FURVVHG LI WKH GHVWLQDWLRQ SDUDPHWHU LV
LQGLUHFWO DGGUHVVHG
,I WKH LQGLUHFW DGGUHVV LV ZULWWHQ WR WKH SURJUDP DUHD
WKH (QKDQFHG 3/ SURFHVVRU VHULHV $' GLVSODV
PDMRU IDXOW FRGH EDG XVHU SURJUDP FKHFNVXP

,I
WKH LQGLUHFW DGGUHVV LV ZULWWHQ RXWVLGH RI WKH SURJUDP
DUHD XQH[SHFWHG UHVXOWV FRXOG RFFXU
,I RX XVH WKH 23 LQVWUXFWLRQ ZLWK DQ (QKDQFHG
3/ SURFHVVRUV VHULHV ( DQG KLJKHU WKLV FRQGLWLRQ LV
FRUUHFWO LGHQWLILHG E HLWKHU PDMRU IDXOW FRGH
LQGLUHFW DGGUHVV RXW RI UDQJH KLJK

RU PDMRU IDXOW
FRGH LQGLUHFW DGGUHVV RXW RI UDQJH ORZ


Example:

I:012 COP
[
[ COPY FILE
10
Source #N7:0
Destination #N12:0
Length 5

If input word 12, bit 10 is on, copy the values
of the first five words starting at N7:0 into the first
five words of N12:0.

File Fill (FLL)

Description: 7KH )// LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW ILOOV WKH ZRUGV RI D
ILOH ZLWK D VRXUFH YDOXH 7KH VRXUFH UHPDLQV XQFKDQJHG 7KH )//
FLL
LQVWUXFWLRQ GRHV QRW XVH VWDWXV ELWV ,I RX QHHG DQ HQDEOH ELW SURJUDP
FILL FILE
D SDUDOOHO RXWSXW WKDW XVHV D VWRUDJH DGGUHVV
Source
Destination 7KH )// LQVWUXFWLRQ GRHV QRW ZULWH RYHU ILOH ERXQGDULHV $Q
Length RYHUIORZ GDWD LV ORVW $OVR QR GDWD FRQYHUVLRQ RFFXUV LI WKH VRXUFH
DQG GHVWLQDWLRQ ILOHV DUH GLIIHUHQW GDWD WSHV XVH ILOHV RI WKH VDPH GDWD
WSH IRU HDFK
,I WKH GHVWLQDWLRQ LV LQ D ILOH RI ZRUGV VXFK DV DQ LQWHJHU ILOH

RX VSHFLI WKH OHQJWK LQ VWUXFWXUHV )RU
H[DPSOH LI WKH VRXUFH ZRUG LV DQ LQWHJHU ILOH WKH GHVWLQDWLRQ LV LQ D
FRXQWHU ILOH DQG RX VSHFLI D OHQJWK RI WKH VRXUFH ZRUG LV FRSLHG
WLPHV WR ILOO WKH FRXQWHU VWUXFWXUHV
7KH )// LQVWUXFWLRQ LV OHYHO VHQVLWLYH

Entering Parameters
7R SURJUDP WKH )// LQVWUXFWLRQ RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ


Source the address of the source word or a program constant. The source
remains unchanged.

Destination the starting address of the destination file. The instruction writes over
any data already stored at the destination.

Length the number of the words/structures to fill in the destination file

1785-6.1 November 1998


$77(17,21 ,I RX XVH WKH )// LQVWUXFWLRQ ZLWK DQ
(QKDQFHG 3/ SURFHVVRU VHULHV $' ILOH ERXQGDULHV
PLJKW EHFRPH FURVVHG LI WKH GHVWLQDWLRQ SDUDPHWHU LV
LQGLUHFWO DGGUHVVHG
,I WKH LQGLUHFW DGGUHVV LV ZULWWHQ WR WKH SURJUDP DUHD
WKH (QKDQFHG 3/ SURFHVVRU VHULHV $' GLVSODV
PDMRU IDXOW FRGH EDG XVHU SURJUDP FKHFNVXP

,I
WKH LQGLUHFW DGGUHVV LV ZULWWHQ RXWVLGH RI WKH SURJUDP
DUHD XQH[SHFWHG UHVXOWV FRXOG RFFXU
,I RX XVH WKH )// LQVWUXFWLRQ ZLWK DQ (QKDQFHG
3/ SURFHVVRUV VHULHV ( DQG KLJKHU WKLV FRQGLWLRQ LV
FRUUHFWO LGHQWLILHG E HLWKHU PDMRU IDXOW FRGH
LQGLUHFW DGGUHVV RXW RI UDQJH KLJK

Example:

I:012 FLL
[
[ FILL FILE
10
Source N7:0
Destination #N12:0
Length 5
If input word 12, bit 10 is on, copy the value
of word N7:0 into the first five words
starting at N12:0

:RUGV DUH FRSLHG IURP WKH VSHFLILHG VRXUFH ILOH LQWR WKH VSHFLILHG
GHVWLQDWLRQ ILOH HYHU VFDQ WKDW WKH UXQJ LV WUXH 7KH DUH FRSLHG LQ
DVFHQGLQJ RUGHU ZLWK QR WUDQVIRUPDWLRQ RI GDWD

XS WR WKH VSHFLILHG
QXPEHU RU XQWLO WKH ODVW ZRUG RI WKH GHVWLQDWLRQ ILOH LV UHDFKHG
ZKLFKHYHU RFFXUV ILUVW
$FFXUDWHO VSHFLI WKH VWDUWLQJ DGGUHVV DQG OHQJWK RI WKH GDWD EORFN
RX DUH ILOOLQJ 7KH LQVWUXFWLRQ ZLOO QRW ZULWH RYHU D ILOH ERXQGDU
VXFK DV EHWZHHQ ILOHV 1 DQG 1

DW WKH GHVWLQDWLRQ 7KH RYHUIORZ
ZRXOG EH ORVW

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 10
Diagnostic Instructions FBC, DDT, DTR
Using Diagnostic Instructions 7KH GLDJQRVWLF LQVWUXFWLRQV OHW RX GHWHFW SUREOHPV ZLWK GDWD LQ RXU
SURJUDPV 7DEOH $ OLVWV WKH DYDLODEOH GLDJQRVWLF LQVWUXFWLRQV
Table 10.A
Available Diagnostic Instructions

If You Want to: Use this Operation: Found on Page:

Compare I/O data against a known, good FBC 10-2
reference and record any mismatches

Compare I/O data against a known, good DDT 10-2
reference, record any mismatches, and
update the reference file to match the
source file

Pass source data through a mask and DTR 10-8
compare the result to reference data, and
then write the source word into the
reference address of the next comparison.

HDFK RSHUDQG

10-2 Diagnostic Instructions FBC, DDT, DTR

File Bit Comparison (FBC) and 7KH )% DQG ''7 GLDJQRVWLF LQVWUXFWLRQV DUH RXWSXW LQVWUXFWLRQV
Diagnostic Detect (DDT) WKDW RX XVH WR PRQLWRU PDFKLQH RU SURFHVV RSHUDWLRQV WR
GHWHFW PDOIXQFWLRQV
Table 10.B
Available Diagnostic Instructions

If You Want to Detect Malfunctions By: Use this Instruction:

Comparing bits in a file of real-time inputs with a FBC
reference bit file that represents correct operation

Change-of-state diagnostics DDT

Description: %RWK WKH )% DQG ''7 LQVWUXFWLRQV FRPSDUH ELWV LQ D ILOH RI UHDOWLPH
FBC
PDFKLQH RU SURFHVV YDOXHV LQSXW ILOH

ZLWK ELWV LQ D UHIHUHQFH ILOH
FILE BIT COMPARE EN GHWHFW GHYLDWLRQV DQG UHFRUG PLVPDWFKHG ELW QXPEHUV 7KHVH
Source DN LQVWUXFWLRQV UHFRUG WKH SRVLWLRQ RI HDFK PLVPDWFK IRXQG DQG SODFH WKLV
Reference
Result
FD LQIRUPDWLRQ LQ WKH UHVXOW ILOH ,I QR PLVPDWFKHV DUH IRXQG WKH '1 ELW
Compare Control
Length
IN
LV VHW EXW WKH UHVXOW ILOH UHPDLQV XQFKDQJHG
ER
Position
Result control 7KH GLIIHUHQFH EHWZHHQ WKH ''7 DQG )% LQVWUXFWLRQ LV WKDW HDFK
Length
Position
WLPH WKH ''7 LQVWUXFWLRQ ILQGV D PLVPDWFK WKH SURFHVVRU FKDQJHV WKH
UHIHUHQFH ELW WR PDWFK WKH VRXUFH ELW 7KH )% LQVWUXFWLRQ GRHV QRW
FKDQJH WKH UHIHUHQFH ELW 8VH WKH ''7 LQVWUXFWLRQ WR XSGDWH RXU
UHIHUHQFH ILOH WR UHIOHFW FKDQJLQJ PDFKLQH RU SURFHVV FRQGLWLRQV

Selecting the Search Mode
6HOHFW ZKHWKHU WKH GLDJQRVWLF LQVWUXFWLRQ VHDUFKHV IRU RQH PLVPDWFK
DW D WLPH RU ZKHWKHU LW VHDUFKHV IRU DOO PLVPDWFKHV GXULQJ RQH
SURJUDP VFDQ

One Mismatch at a Time
:LWK HDFK IDOVHWRWUXH UXQJ WUDQVLWLRQ WKH LQVWUXFWLRQ VHDUFKHV IRU
WKH QH[W PLVPDWFK EHWZHHQ WKH LQSXW DQG UHIHUHQFH ILOHV 8SRQ
ILQGLQJ D PLVPDWFK WKH LQVWUXFWLRQ VWRSV DQG VHWV WKH IRXQG )' ELW
7KHQ WKH LQVWUXFWLRQ HQWHUV WKH SRVLWLRQ QXPEHU RI WKH PLVPDWFK LQWR
WKH UHVXOW ILOH
7KH ''7 LQVWUXFWLRQ DOVR FKDQJHV WKH VWDWXV RI WKH UHIHUHQFH ELW WR
PDWFK WKH VWDWXV RI WKH FRUUHVSRQGLQJ LQSXW ELW 7KH LQVWUXFWLRQ UHVHWV
WKH IRXQG ELW ZKHQ WKH UXQJ JRHV IDOVH

1785-6.1 November 1998

Diagnostic Instructions FBC, DDT, DTR 10-3

:KHQ WKH LQVWUXFWLRQ UHDFKHV WKH HQG RI WKH ILOH WKH GRQH ELW ELW
'1 RI WKH FRPSDUH FRQWURO HOHPHQW

LV VHW 7KHQ ZKHQ WKH UXQJ JRHV
IDOVH WKH LQVWUXFWLRQ UHVHWV
‡ HQDEOH ELW
‡ IRXQG ELW LI VHW

‡ FRPSDUH GRQH ELW
‡ UHVXOW GRQH ELW LI VHW

‡ ERWK FRQWURO FRXQWHUV
7R HQDEOH WKLV PRGH RI RSHUDWLRQ VHW WKH LQKLELW ELW ,1

HLWKHU E
ODGGHU SURJUDP RU PDQXDOO EHIRUH SURJUDP H[HFXWLRQ

All Per Scan
7KH LQVWUXFWLRQ VHDUFKHV IRU DOO PLVPDWFKHV EHWZHHQ WKH LQSXW DQG
UHIHUHQFH ILOHV LQ RQH SURJUDP VFDQ 8SRQ ILQGLQJ PLVPDWFKHV WKH
LQVWUXFWLRQ HQWHUV WKH SRVLWLRQ QXPEHUV RI PLVPDWFKHG ELWV LQWR WKH
UHVXOW ILOH LQ WKH RUGHU LW ILQGV WKHP $IWHU UHDFKLQJ WKH HQG RI WKH
LQSXW DQG UHIHUHQFH ILOHV WKH LQVWUXFWLRQ VHWV WKH )' ELW LI LW ILQGV DW
OHDVW RQH PLVPDWFK 7KHQ WKH LQVWUXFWLRQ VHWV WKH '1 ELW
,I RX XVH D UHVXOW ILOH WKDW FDQQRW KROG DOO GHWHFWHG PLVPDWFKHV LI WKH
UHVXOW ILOH ILOOV

WKH LQVWUXFWLRQ VWRSV DQG UHTXLUHV DQRWKHU IDOVHWRWUXH
UXQJ WUDQVLWLRQ WR FRQWLQXH RSHUDWLRQ 7KH LQVWUXFWLRQ ZUDSV WKH QHZ
PLVPDWFKHG ELW SRVLWLRQV LQWR WKH EHJLQQLQJ RI WKH UHVXOW ILOH ZULWLQJ
RYHU WKH ROG
$IWHU FRPSOHWLQJ WKH FRPSDULVRQ DQG ZKHQ WKH UXQJ JRHV IDOVH WKH
LQVWUXFWLRQ UHVHWV
‡ HQDEOH ELW
‡ IRXQG ELW LI VHW

‡ ERWK FRQWURO FRXQWHUV
7R HQDEOH WKLV PRGH RI RSHUDWLRQ UHVHW WKH LQKLELW ELW ,1

E
ODGGHU SURJUDP RU PDQXDOO EHIRUH SURJUDP H[HFXWLRQ

1785-6.1 November 1998


Entering Parameters
7R SURJUDP WKHVH LQVWUXFWLRQV RX QHHG WR SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ LQIRUPDWLRQ

Parameter: Description:

Source the indexed address of your input file.

Reference the indexed address of the file that contains the data with which you
compare your input file.

Result the indexed address of the file where the instruction stores the position
(bit) number of each detected mismatch.

Cmp Control the address of the comparison control structure (R) that stores status
bits, the length of the source and reference files (both should be the
same), and the current position during operation. Use the compare
control address with mnemonic when you address these parameters:
Length (.LEN) is the decimal number of bits to be compared in the
source and reference files. Remember that bits in I/O files are
numbered in octal 00-17, but that bits in all other files are numbered in
decimal 0-15.
Position (.POS) is the current position of the bit to which the instruction
points. Enter a value only if you want the instruction to start at an
offset concurrent with a control file offset for one scan.

Result Control the address of the result control structure (R) that stores the bit
position number each time the instruction finds a mismatch between
source and reference files.

8VH WKH UHVXOW FRQWURO DGGUHVV ZLWK PQHPRQLF ZKHQ RX DGGUHVV
WKHVH SDUDPHWHUV
‡ /HQJWK /(1

LV WKH GHFLPDO QXPEHU RI HOHPHQWV LQ WKH UHVXOW
ILOH 0DNH WKH OHQJWK ORQJ HQRXJK WR UHFRUG WKH PD[LPXP
QXPEHU RI H[SHFWHG PLVPDWFKHV
‡ 3RVLWLRQ 326

LV WKH FXUUHQW SRVLWLRQ LQ WKH UHVXOW ILOH (QWHU D
YDOXH RQO LI RX ZDQW WKH LQVWUXFWLRQ WR VWDUW DW DQ RIIVHW
FRQFXUUHQW ZLWK D FRQWURO ILOH RIIVHW IRU RQH VFDQ

$77(17,21 'R QRW XVH WKH VDPH DGGUHVV IRU PRUH
WKDQ RQH FRQWURO VWUXFWXUH 'XSOLFDWLRQ RI WKHVH
DGGUHVVHV FRXOG UHVXOW LQ XQSUHGLFWDEOH RSHUDWLRQ
SRVVLEO FDXVLQJ HTXLSPHQW GDPDJH DQGRU LQMXU WR
SHUVRQQHO

1785-6.1 November 1998


Using Status Bits
7R XVH WKH )% RU ''7 LQVWUXFWLRQ FRUUHFWO H[DPLQH DQG FRQWURO
ELWV LQ ERWK WKH FRPSDULVRQ DQG UHVXOW FRQWURO HOHPHQWV RX DGGUHVV
WKHVH ELWV E PQHPRQLF

Bit: Function:

Comparison Enable .EN (bit 15) starts operation on a false-to-true rung transition
Control Bits If the .IN bit is set for one-at-a-time operation, the ladder program
must toggle the .EN bit after the instruction detects each mismatch.

Done .DN (bit 13) is set when the processor reaches the end of the source and reference files

Error .ER (bit 11) is set when the processor detects an error and stops operation of
the instruction
For example, an error occurs if the length (.LEN) is less than or equal to zero
or if the position (.POS) is less than zero. The ladder program must reset the
.ER bit if the instruction detects an error.

Inhibit .IN (bit 09) determines the mode of operation
When this bit is reset, the processor detects all mismatches in one scan.
When this bit is set, the processor stops the search at each mismatch and
waits for the ladder program to re-enable the instruction before continuing
the search.

Found .FD (bit 08) is set each time the processor records a mismatch bit number in the result file
(one-at-a-time operation) or after recording all mismatches (all per scan).

Result Done .DN (bit 13) is set when the result file fills
Control Bits The instruction stops and requires another false-to-true rung transition to
reset the result .DN bit and then continue. If the instruction finds another
mismatch, it wraps the new position number around to the beginning of the
file, writing over previous position numbers.

$IWHU WKH )% RU ''7 LQVWUXFWLRQ VHWV WKH FRPSDUH '1 ELW WKH
LQVWUXFWLRQ LV UHVHW ZKHQ WKH UXQJ¶V LQSXW FRQGLWLRQV JR IDOVH 7KH
LQVWUXFWLRQ UHVHWV LWV VWDWXV ELWV DQG ERWK FRQWURO HOHPHQWV

1785-6.1 November 1998


Example: 7KH ''7 LQVWUXFWLRQ DERYH FRPSDUHV WKH ELWV LQ WKH VRXUFH ILOH
DDT ,

ZLWK WKH ELWV LQ WKH UHIHUHQFH ILOH %

UHFRUGLQJ WKH
DIAGNOSTIC DETECT EN PLVPDWFKHG ELW SRVLWLRQV LQ WKH UHVXOW ILOH 1

Source #I:030 DN
Reference #B3:0
Result #N10:0 FD
Compare control R6:0 IN
Length 48
Position 0 ER
Result control R6:1
Length 10
Position 0

Input Reference Result File 2
File File 1 (mismatched bit #s)
bit 3 #N10
#I:030 #B3
17 10 07 00 15 08 07 00
0 3
1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 31
1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
2 32
1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
bit 31
3 40

bit 40 bit32
9

The FBC and DDT instructions detect mismatches and record their locations by bit number in a result file.
1
The DDT instruction changes the status of the corresponding bit in the reference file to match the input file
when it detects a mismatch.
2
The length of the result file is the length that you enter for RESULT CONTROL.
16657a


Source (#I:030) Where to find input data for comparison

Reference (#B3:0) Where to find the reference file

Result (#N10:0) Where to store mismatched bit numbers

CMP Control (R6:0) What control structure controls the comparison

Length (48) The number of bits to be compared

Position (0) To start at the beginning of the file

Result Control (R6:1) What control structure controls the result

Length (10) The number of words reserved for mismatches

Position (0) To start at the beginning of the file

1785-6.1 November 1998


,PSRUWDQW 7KH )% DQG ''7 LQVWUXFWLRQV PD FDXVH DQ
(QKDQFHG 3/ SURFHVVRU WR IDXOW LI WKH LQGH[HG
DGGUHVVLQJ RIIVHW FRQWDLQV D YDOXH WKDW H[FHHGV GDWD
WDEOH ERXQGDULHV 7R ZRUN DURXQG WKLV DGG D ODGGHU
UXQJ WKDW FOHDUV 6 LQGH[HG DGGUHVVLQJ RIIVHW

LPPHGLDWHO EHIRUH DQ )% RU ''7 LQVWUXFWLRQ
CLR
Clear
Destination S:24

FBC
EN
Source #I0:30
Reference #B3:0 DN
Result #N10:0 FD
Compare Control R6:0
or Length 48 IN
Position 0
ER
Result Control R6:1
Length 10
Position 0

DDT
EN
Source #I0:30
Reference #B3:0 DN
Result #N10:0 FD
Compare Control R6:0
Length 48 IN
Position 0
ER
Result Control R6:1
Length 10
Position 0

1785-6.1 November 1998


Data Transitional (DTR) 7KH '75 LQVWUXFWLRQ LV DQ LQSXW LQVWUXFWLRQ WKDW SDVVHV D VRXUFH YDOXH
WKURXJK D PDVN DQG FRPSDUHV WKH UHVXOW WR D UHIHUHQFH YDOXH 8VH WKLV
LQVWUXFWLRQ WR GHWHFW DQG LGHQWLI LQYDOLG LQSXWV DQG WR SUHYHQW LQYDOLG
LQSXWV IURP VKXWWLQJ GRZQ D EDWFK SURFHVVRU RU PDFKLQH RSHUDWLRQ

Description: 7KH '75 LQVWUXFWLRQ FRPSDUHV D VRXUFH ZRUG WKURXJK D PDVN ZLWK D
DTR UHIHUHQFH ZRUG 7KH LQVWUXFWLRQ DOVR ZULWHV WKH VRXUFH ZRUG LQWR WKH
DATA TRANSITION UHIHUHQFH DGGUHVV IRU WKH QH[W FRPSDULVRQ 7KH VRXUFH ZRUG UHPDLQV
Source XQFKDQJHG
Mask
Reference :KHQ WKH PDVNHG VRXUFH GLIIHUV IURP WKH UHIHUHQFH WKH LQVWUXFWLRQ
JRHV WUXH IRU RQO RQH VFDQ 7KH SURFHVVRU ZULWHV WKH PDVNHG VRXUFH
YDOXH LQWR WKH UHIHUHQFH DGGUHVV :KHQ WKH PDVNHG VRXUFH DQG WKH
UHIHUHQFH DUH WKH VDPH WKH LQVWUXFWLRQ UHPDLQV IDOVH

$77(17,21 2QOLQH SURJUDPPLQJ ZLWK WKLV
LQVWUXFWLRQ FDQ EH GDQJHURXV ,I WKH GHVWLQDWLRQ YDOXH LV
GLIIHUHQW IURP WKH VRXUFH YDOXH WKH LQVWUXFWLRQ JRHV WUXH
8VH FDXWLRQ LI RX LQVHUW WKLV LQVWUXFWLRQ ZKHQ WKH
SURFHVVRU LV LQ 5XQ RU 5HPRWH 5XQ PRGH

Entering Parameters
7R SURJUDP WKH '75 LQVWUXFWLRQ RX QHHG WR SURYLGH WKH SURFHVVRU
ZLWK WKH IROORZLQJ LQIRUPDWLRQ


Source the address of the input word, typically real inputs.

Mask the hexadecimal value or address that contains the mask value

Reference the address of the reference word
The reference contains the source data from the last DTR scan

Example: 7KH '75 LQVWUXFWLRQ DERYH SDVVHV WKH VRXUFH ,

WKURXJK D PDVN
RI OFFF DQG FRPSDUHV WKH UHVXOW WR WKH UHIHUHQFH ZRUG 1

7KH
DTR
VRXUFH ZRUG LV WKHQ ZULWWHQ LQWR WKH UHIHUHQFH DGGUHVV IRU WKH QH[W
DATA TRANSITION
FRPSDULVRQ WKH VRXUFH UHPDLQV XQFKDQJHG

Source I:002
Mask 0FFF
Reference N63:11

1785-6.1 November 1998


15 08 07 00 15 08 07 00
Source Word
1 8 3 I:002 1 8 7

15 08 07 00 15 08 07 00
Mask Value
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFF 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

15 08 07 00 15 08 07 00
Current Current
Scan 1 8 3 Reference Word 1 8 7 Scan
N63:11
Previous 1 8 3 1 8 3 Previous
Scan Scan
Rung remains false as long as Rung goes true for one scan
input value does not change when change is detected 13385

1785-6.1 November 1998


1RWHV

1785-6.1 November 1998

Chapter 11
Shift Register Instructions BSL, BSR, FFL,
FFU, LFL, LFU
Applying Shift Registers 8VH WKH VKLIW UHJLVWHU LQVWUXFWLRQ WR VLPXODWH WKH PRYHPHQW RU IORZ RI
SDUWV DQG LQIRUPDWLRQ

If You Use a Shift Register for: Data in the Shift Register Could Represent:

Tracking parts through an assembly line Part types, quality, size, and status

Controlling machine or process operations The order in which events occur

Inventory control Identification numbers or locations

System diagnostics A fault condition that caused a shutdown

7DEOH $ OLVWV WKH DYDLODEOH VKLIW LQVWUXFWLRQV
Table 11.A
Available Shift Instructions

If You Want to: Use these Instructions: Found on Page:

Load bits into, shift bits through, and unload bits from a bit array one bit at BSL, BSR 11-2
a time, such as for tracking bottles through a bottling line where each bit
represents a bottle

Load and unload values in the same order, such as for tracking parts FFL, FFU 11-5
through an assembly line where parts are represented by values that have
a part number and assembly code

Load and unload values in reverse order, such as tracking stacked LFL, LFU * 11-8
inventory in a warehouse, where goods are represented by serial number
and inventory codes

* These instructions are only supported by Enhanced PLC-5 processors.

HDFK RSHUDQG

11-2 Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU

Using Bit Shift Instructions

Description: %LW VKLIW LQVWUXFWLRQV VKLIW DOO ELWV ZLWKLQ WKH VSHFLILHG DGGUHVV
BSL
RQH ELW SRVLWLRQ ZLWK HDFK IDOVHWRWUXH UXQJ WUDQVLWLRQ 7KHVH
BIT SHIFT LEFT EN LQVWUXFWLRQV DUH
File
Control DN
‡ %LW 6KLIW /HIW %6/

Bit address
Length ‡ %LW 6KLIW 5LJKW %65

Entering Parameters
7R SURJUDP D ELW VKLIW LQVWUXFWLRQ RX QHHG WR SURYLGH WKH SURFHVVRU
ZLWK WKH IROORZLQJ LQIRUPDWLRQ


File the address of the bit array you want to manipulate. You must start the
array at a 16-bit word boundary. For example, use bit 0 of word number
1, 2, 3, etc. You can end the array at any bit number up to 15,999.
However, you cannot use the remaining bits in that particular element
because the instruction invalidates them.

Control The address of the control structure (48 bits – three 16-bit words) in the
control area (R) of memory that stores the instruction’s status bits, the
size of the array (number of bits), and the bit pointer.

Position the current position of the bit to which the instruction points. Enter a
value only if you want the instruction to start at an offset concurrent with
a control file offset for one scan. Use the control address with mnemonic
when you address this parameter.

Bit Address the address of the source bit. The instruction inserts the status of this bit
in either the first (lowest) bit position (for the BSL instruction) or the last
(highest) bit position (for the BSR instruction) in the array.

Length the decimal number of bits to be shifted. Remember that bits in I/O files
are numbered in octal 00-17, but that bits in all other files are numbered
in decimal 0-15. Use the control address with mnemonic when you
address this parameter.

$77(17,21 'R QRW XVH WKH VDPH FRQWURO DGGUHVV IRU
PRUH WKDQ RQH LQVWUXFWLRQ 8QH[SHFWHG RSHUDWLRQ FRXOG
UHVXOW LQ SRVVLEOH HTXLSPHQW GDPDJH DQGRU SHUVRQDO
LQMXU

1785-6.1 November 1998

Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU 11-3

Using Status Bits
7R XVH WKH %6/ RU %65 LQVWUXFWLRQ FRUUHFWO H[DPLQH VWDWXV ELWV LQ
WKH FRQWURO HOHPHQW RX DGGUHVV WKHVH ELWV E PQHPRQLF

Bit: Definition:

Enable .EN (bit 15) is set when the rung makes a false-to-true rung transition to
indicate the instruction is enabled.

Done .DN (bit 13) is set to indicate that the bit array shifted one bit position

Error .ER (bit 11) is set to indicate that the instruction detected an error, such as if
you entered a negative file length

Unload .UL (bit 10) is the instruction’s output.
The .UL bit stores the status of the bit removed from the array
each time the instruction is enabled. Avoid using the .UL bit when
the .ER bit is set.

,PSRUWDQW :KHQ HQDEOHG WKH ELW SRLQWHU LV VHW WR WKH YDOXH RI WKH
OHQJWK WKH ELW DUUD LV VKLIWHG $IWHU DOO RI WKH ELWV DUH
VKLIWHG WKH LQVWUXFWLRQ UHVHWV WKH (1 (5 DQG '1 ELWV
DQG WKH ELW SRLQWHU ZKHQ LQSXW FRQGLWLRQV JR IDOVH

Bit Shift Left (BSL) Example:
Source
BSL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I:022/12
BIT SHIFT LEFT EN
File #B3:1 31 16
Control R6:53 DN L
Bit address I:022/12
Length 58 47 32
58-Bit
L
#B3/16
63 48 (B3:1)
L

invalid 73 64
Unload Bit
L

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
16658


File (#B3:1) The location of the bit array

Control (R6:53) The instruction’s address and control element

Bit Address (I:022/12) The location of the source bit (bit 12 of input word 22)

Length (58) The number of bits in the bit array

1785-6.1 November 1998

11-4 Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU

:KHQ D UXQJ FRQWDLQLQJ WKH %6/ LQVWUXFWLRQ JRHV IURP IDOVH WR WUXH
WKH SURFHVVRU VHWV WKH (1 ELW 7KHQ WKH SURFHVVRU VKLIWV ELWV LQ ELW
ILOH % VWDUWLQJ ZLWK ELW WR WKH OHIW KLJKHU ELW QXPEHU

RQH ELW
SRVLWLRQ 7KH ODVW ELW VKLIWV RXW DW ELW SRVLWLRQ LQWR WKH 8/ ELW 7KH
VSHFLILHG VRXUFH ELW ELW RI LQSXW ZRUG VKLIWV LQWR WKH ILUVW ELW
SRVLWLRQ ELW RI ELW ILOH %
$IWHU WKH SURFHVVRU FRPSOHWHV WKH VKLIW RSHUDWLRQ LQ RQH SURJUDP
VFDQ ZKHQ WKH UXQJ JRHV IDOVH WKH LQVWUXFWLRQ UHVHWV WKH (1 (5 LI
VHW

DQG '1 ELWV DQG UHVHWV WKH SRLQWHU
)RU ZUDSDURXQG RSHUDWLRQ PDNH WKH VRXUFH DGGUHVV WKH VDPH DV WKH
KLJKHVW RXWJRLQJ

Instruction set reference [by allen bradley]

More Related Content

What's hot

Viewers also liked

Similar to Instruction set reference [by allen bradley]

More from Iamtubalcain

Recently uploaded

Instruction set reference [by allen bradley]